IRDC3842 [INFINEON]
USER GUIDE FOR IR3842 EVALUATION BOARD; 用户指南IR3842评估板型号: | IRDC3842 |
厂家: | Infineon |
描述: | USER GUIDE FOR IR3842 EVALUATION BOARD |
文件: | 总17页 (文件大小:919K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IRDC3842
TM
SupIRBuck
USER GUIDE FOR IR3842 EVALUATION BOARD
DESCRIPTION
An output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
rectifier MOSFET for optimum cost and
performance.
The IR3842 is
converter, providing
performance and flexible solution in a small
5mmx6mm Power QFN package.
a
synchronous buck
compact, high
a
Key features offered by the IR3842 include
programmable soft-start ramp, precision
This user guide contains the schematic and bill
of materials for the IR3842 evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed application
information for IR3842 is available in the
IR3842 data sheet.
0.7V reference voltage, Power Good,
thermal protection, programmable switching
frequency, Sequence input, Enable input,
input under-voltage lockout for proper start-
up, and pre-bias start-up.
BOARD FEATURES
• Vin = +12V (13.2V Max)
• Vcc=+5V (5.5V Max)
• Vout = +1.8V @ 0- 4A
• Fs=600kHz
• L= 1.5uH
• Cin= 2x10uF (ceramic 1206) + 330uF (electrolytic)
• Cout= 4x22uF (ceramic 0805)
02/02/2009
1
IRDC3842
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 4A load should be
connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the
board are listed in Table I.
IR3842 has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate supplies
should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it would be
connected to Vcc+ and Vcc-.
If single 12V application is required connect R7 (zero Ohm resistor) which enables the on board bias
regulator (see schematic). In this case there is no need of external Vcc supply.
The output can track a sequencing input at the start-up. For sequencing application, R16 should be
removed and the external sequencing source should be applied between Seq. and Agnd. The value of R14
and R28 can be selected to provide the desired ratio between the output voltage and the tracking input. For
proper operation of IR3842, the voltage at Seq. pin should not exceed Vcc.
Table I. Connections
Connection
VIN+
Signal Name
Vin (+12V)
VIN-
Ground of Vin
Vcc input
Vcc+
Vcc-
Ground for Vcc input
Ground of Vout
Vout (+1.8V)
VOUT-
VOUT+
Enable
Seq.
Enable
Sequence Input
Power Good Signal
P_Good
LAYOUT
The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3842 SupIRBuck and all of the
passive components are mounted on the top side of the board.
Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located
close to IR3842. The feedback resistors are connected to the output voltage at the point of regulation
and are located close to the SupIRBuck. To improve efficiency, the circuit board is designed to
minimize the length of the on-board power ground current path.
02/02/2009
2
IRDC3842
Connection Diagram
Vin
GND
Enable
GND
Vo
Seq
AGND
Vcc GND
SS
PGood
Fig. 1: Connection diagram of IR384x evaluation boards
02/02/2009
3
IRDC3842
Fig. 2: Board layout, top overlay
Fig. 3: Board layout, bottom overlay (rear view)
02/02/2009
4
IRDC3842
PGND
Plane
Single point
connection
between AGND
and PGND.
AGND
Plane
Fig. 4: Board layout, mid-layer I.
Fig. 5: Board layout, mid-layer II.
02/02/2009
5
IRDC3842
2
1
1
1
1
1 d n A G
1 5
t o B o
E n
c V c
1 3
1 4
9
8
d o o P G
1
1
1
1
1
1
1
02/02/2009
6
IRDC3842
Bill of Materials
Item Quantity Part Reference
Value
330uF
10uF
Description
Manufacturer
Part Number
EEV-FK1E331P
ECJ-3YB1C106M
1
2
1 C1
2 C3 C2
SMD Elecrolytic, Fsize, 25V, 20% Panasonic
1206, 16V, X5R, 20%
0805, 10V, X5R, 20%
Panasonic - ECG
3
1 C34
10uF
Panasonic - ECG
ECJ-GVB1A106M
4
5
6
6 C7 C10 C13 C14 C24 C32 0.1uF
0603, 25V, X7R, 10%
0603, 50V, NP0, 5%
0603, 50V, NP0, 5%
Panasonic - ECG
Murata
Panasonic- ECG
ECJ-1VB1E104K
GRM1885C1H222JA01D
ECJ-1VC1H221J
1 C8
2200pF
220pF
1 C11
C15 C16 C17 C18
7
8
9
4
22uF
0805, 6.3V, X5R, 20%
0603, 50V, X7R, 10%
MM3Z5V6B,Zener, 5.6V
11.5x10x4mm, 20%, 3.8mOhm
Panasonic- ECG
Panasonic - ECG
Fairchild
Delta
ECJ-2FB0J226M
ECJ-1VB1H822K
MM3Z5V6B
1 C26
1 D1
1 L1
8200pF
MM3Z5V6B
1.5uH
10
11
12
13
14
15
16
17
18
19
20
21
22
23
MPO104-1R5
1 Q1
1 R5
1 R18
1 R4
1 R6
1 R9
1 R16
2 R3 R12
1 R17
1 R19
1 R1
1 R2
1 U1
MMBT3904/SOT NPN, 40V, 200mA, SOT-23
Fairchild
Rohm
Rohm
Panasonic - ECG
Vishey/Dale
Rohm
Vishay/Dale
Rohm
Rohm
Rohm
Rohm
Rohm
MMBT3904/SOT
3.3k
4.99k
130
20
23.7k
0
2.49k
10.0k
750
2.15k
3.92k
IR3842
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10 W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10 W,5%
Thick Film, 0603,1/10 W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
MCR03EZPFX3301
MCR03EZPFX4991
ERJ-3EKF1300V
CRCW060320R0FKEA
MCR03EZPFX2372
CRCW06030000Z0EA
MCR03EZPFX2491
MCR03EZPFX1002
MCR03EZPFX7500
MCR03EZPFX2151
MCR03EZPFX3921
PQFN 6mmx5mm, 4A SupIRBuck International Rectifier IR3842MPbF
02/02/2009
7
IRDC3842
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-4A, Room Temperature, No Air Flow
Fig. 17. Start up at 4A Load
Fig. 18. Start up at 4A Load,
Ch1:Vo, Ch2:Vin, Ch3:Vss, Ch4:Enable
Ch1:Vo, Ch2:Vin, Ch3:Vss, Ch4:VPGood
Fig. 20. Output Voltage Ripple, 4A load
Ch1: Vo
Fig. 19. Start up with 1.62V Pre Bias, 0A
Load, Ch1:Vo, Ch3:VSS
Fig. 22. Short (Hiccup) Recovery
Ch1:Vo , Ch3:VSS
Fig. 21. Inductor node at 4A load
Ch2:LX
02/02/2009
8
IRDC3842
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=0-4A, Room Temperature, No Air Flow
Fig. 23. Transient Response, 2A to 4A step 2.5A/μs
Ch1:Vo, Ch4:Io
02/02/2009
9
IRDC3842
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow
Fig. 24. Bode Plot at 4A load shows a bandwidth of 103.76 kHz and phase margin of 52.878
degrees
02/02/2009
10
IRDC3842
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vo=1.8V, Io=0- 4A, Room Temperature, No Air Flow
92
91
90
89
88
87
86
85
84
83
82
10
20
30
40
50
60
70
80
90
100
Load Percentage (%)
Fig.15: Efficiency versus load current
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
10
20
30
40
50
60
70
80
90
100
Load Percentage(%)
Fig.16: Power loss versus load current
02/02/2009
11
IRDC3842
THERMAL IMAGES
Vin=12V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow
Fig. 17: Thermal Image at 4A load
Test points 1 and 2 are IR3842 and inductor, respectively.
02/02/2009
12
IRDC3842
Simultaneous Tracking at Power Up and Power Down
Vin=12V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow
In order to run the IR3841 in the simultaneous tracking mode, the following steps should be
taken:
- Remove R16 from the board.
- Set the value of R14 and R28 as R2 (3.92K) and R3 (2.49K), respectively.
- Connect the controlling input across SEQ and AGND test points on the board. This voltage
should be at least 1.15 time greater than Vo. For the following test results a 0-3.3V source is
applied to SEQ pin.
- The controlling input should be applied after the SS pin is clamped to 3.0V.
Fig. 18: Simultaneous Tracking a 3.3V input at power-up and shut-down
Ch2: SEQ Ch3:Vout Ch4: SS
02/02/2009
13
IRDC3842
PCB Metal and Components Placement
The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum
lead to lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large and inspectable toe fillet.
The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to
maximum part pad length and width. However, the minimum metal to metal spacing should be no less
than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz.
Copper.
02/02/2009
IRDC3842
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD
pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
02/02/2009
IRDC3842
Stencil Design
•
The Stencil apertures for the lead lands should be approximately 80% of the area of the
lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead
shorts. If too much solder is deposited on the center pad the part will float and the lead
lands will be open.
•
The maximum length and width of the land pad stencil aperture should be equal to the
solder resist opening minus an annular 0.2mm pull back to decrease the incidence of
shorting the center land to the lead lands when the part is pushed into the solder paste.
02/02/2009
IRDC3842
BOTTOM VIEW
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Consumer market.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 11/07
02/02/2009
相关型号:
IRDCIP1001-A
IRDCiP1001-A, 200kHz, 20A, 3.3VIN to 4.5VIN Single Phase Synchronous Buck Converter using iP1001
INFINEON
©2020 ICPDF网 联系我们和版权申明