IRF1407STRRPBF [INFINEON]
暂无描述;型号: | IRF1407STRRPBF |
厂家: | Infineon |
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PD - 93907
AUTOMOTIVE MOSFET
IRF1407
HEXFET® Power MOSFET
Typical Applications
●
Integrated Starter Alternator
D
●
42 Volts Automotive Electrical Systems
VDSS = 75V
Benefits
●
●
●
●
●
●
Advanced Process Technology
R
DS(on) = 0.0078Ω
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
G
ID = 130A
S
Repetitive Avalanche Allowed up to Tjmax
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the lastest processing
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this HEXFET power MOSFET are a 175°C junction
operating temperature, fast switching speed and improved repetitive
avalancherating.Thesebenefitscombinetomakethisdesignanextremely
efficient and reliable device for use in Automotive applications and a wide
variety of other applications.
TO-220AB
Absolute Maximum Ratings
Parameter
Max.
130
92
520
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
A
PD @TC = 25°C
Power Dissipation
330
W
W/°C
V
Linear Derating Factor
2.2
VGS
EAS
IAR
Gate-to-Source Voltage
± 20
390
Single Pulse Avalanche Energy
Avalanche Current
mJ
See Fig.12a, 12b, 15, 16
A
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
mJ
4.6
V/ns
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
Units
RθJC
RθCS
RθJA
0.45
–––
62
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
°C/W
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1
10/11/01
IRF1407
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
75 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.09 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– ––– 0.0078
Ω
V
S
VGS = 10V, ID = 78A
VDS = 10V, ID = 250µA
VDS = 25V, ID = 78A
VDS = 75V, VGS = 0V
VDS = 60V, VGS = 0V, TJ = 150°C
VGS = 20V
2.0
74
––– 4.0
Forward Transconductance
––– –––
––– ––– 20
––– ––– 250
––– ––– 200
––– ––– -200
––– 160 250
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
IGSS
VGS = -20V
Qg
ID = 78A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
35
54
52
81
nC VDS = 60V
VGS = 10V
VDD = 38V
11 –––
––– 150 –––
––– 150 –––
––– 140 –––
ID = 78A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 2.5Ω
VGS = 10V
D
Between lead,
4.5
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
–––
–––
–––
6mm (0.25in.)
nH
G
from package
7.5
and center of die contact
S
Ciss
Input Capacitance
––– 5600 –––
––– 890 –––
––– 190 –––
––– 5800 –––
––– 560 –––
––– 1100 –––
VGS = 0V
Coss
Output Capacitance
pF
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0KHz, See Fig. 5
Coss
VGS = 0V, VDS = 1.0V, ƒ = 1.0KHz
VGS = 0V, VDS = 60V, ƒ = 1.0KHz
VGS = 0V, VDS = 0V to 60V
Coss
Output Capacitance
Coss eff.
Effective Output Capacitance ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
IS
MOSFET symbol
––– –––
130
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 520
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 110 170
––– 390 590
V
TJ = 25°C, IS = 78A, VGS = 0V
TJ = 25°C, IF = 78A
ns
Qrr
ton
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.13mH
RG = 25Ω, IAS = 78A. (See Figure 12).
ISD ≤ 78A, di/dt ≤ 320A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
ꢀCoss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
,
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF1407
1000
100
10
1000
100
10
VGS
15V
10V
VGS
15V
10V
TOP
TOP
8.0V
8.0V
7.0V
6.0V
5.5V
5.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
1000.00
100.00
10.00
130A
=
I
D
T
= 25°C
2.5
2.0
1.5
1.0
0.5
0.0
J
T
= 175°C
J
V
= 15V
DS
20µs PULSE WIDTH
V
= 10V
GS
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
3.0
5.0
7.0
9.0
11.0
13.0
°
T , Junction Temperature
( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
vs. Temperature
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3
IRF1407
15
12
9
100000
D
I
=
78A
V
= 0V,
f = 1 MHZ
GS
V
V
V
=
=
=
60V
37V
15V
DS
DS
DS
C
= C + C
,
C
ds
SHORTED
iss
gs
gd
C
= C
rss
gd
C
= C + C
oss
ds gd
10000
1000
Ciss
6
Coss
Crss
3
100
1
0
0
40
Q
80
120
160
200
10
, Drain-to-Source Voltage (V)
100
, Total Gate Charge (nC)
G
V
DS
Fig 6. Typical Gate Charge vs.
Fig 5. Typical Capacitance vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
1.00
10000
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
1000
100
10
J
100µsec
1msec
T
= 25°C
J
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
10msec
100
GS
1
0.10
1
10
1000
0.0
1.0
2.0
3.0
V
, Drain-toSource Voltage (V)
V
, Source-toDrain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF1407
140
120
100
80
RD
VDS
LIMITED BY PACKAGE
VGS
10V
D.U.T.
RG
+VDD
-
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60
Fig 10a. Switching Time Test Circuit
40
V
20
DS
90%
0
25
50
75
100
125
150
175
°
( C)
T
, Case Temperature
C
10%
V
GS
Fig 9. Maximum Drain Current vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.10
0.1
0.05
SINGLE PULSE
(THERMAL RESPONSE)
0.02
0.01
P
DM
0.01
t
1
t
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1407
650
520
390
260
130
0
1 5V
I
D
TOP
32A
55A
78A
DRIVER
BOTTOM
L
V
G
DS
D.U.T
AS
R
+
V
D D
-
I
A
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
( C)
Starting T , Junction Temperature
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
3.5
V
G
3.0
2.5
2.0
1.5
I
= 250µA
D
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
-75 -50 -25
0
25 50 75 100 125 150 175 200
3mA
T
, Temperature ( °C )
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRF1407
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
∆
avalanche losses
0.05
0.10
1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
TOP
BOTTOM 10% Duty Cycle
= 78A
Single Pulse
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
Starting T , Junction Temperature (°C)
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = ∆T/ ZthJC
Iav = 2∆T/ [1.3·BV·Zth]
Fig 16. Maximum Avalanche Energy
EAS (AR) = PD (ave)·tav
vs. Temperature
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7
IRF1407
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T*
-
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
+
-
VDD
VGS
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
Period
D =
P.W.
V
[
=10V
] ***
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
[
[
]
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
]
SD
Ripple ≤ 5%
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 17. For N-channel HEXFET® power MOSFETs
8
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IRF1407
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
- B
-
3.78 (.149)
3.54 (.139)
10.29 (.405)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
1.32 (.052)
1.22 (.048)
- A
-
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
LEAD ASSIG NMENTS
1 - GATE
1
2
3
2 - DRAIN
3 - SOU RCE
4 - DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B
A
M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
N OTES:
1
2
DIMENSIO NING & TO LER ANCING PER ANS I Y14.5M, 1982.
CO NTROLLING DIMEN SIO N : INC H
3
4
O UTLINE CO NFOR MS TO JEDEC O UTLIN E TO -220AB.
HEATSIN K & LEAD M EASUREM ENTS D O NO T INCLU DE B URRS .
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLYLINE "C"
DATE CODE
YEAR 7 = 1997
ASSEMBLY
LOT CODE
WE E K 19
LINE C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/01
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9
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