IRF1503STRLPBF [INFINEON]

Power Field-Effect Transistor, 75A I(D), 30V, 0.0033ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, LEAD FREE, PLASTIC, D2PAK-3;
IRF1503STRLPBF
型号: IRF1503STRLPBF
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 75A I(D), 30V, 0.0033ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, LEAD FREE, PLASTIC, D2PAK-3

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PD-94526A  
AUTOMOTIVE MOSFET  
IRF1503  
HEXFET® Power MOSFET  
Typical Applications  
14V Automotive Electrical Systems  
14V Electronic Power Steering  
D
VDSS = 30V  
Features  
Advanced Process Technology  
Ultra Low On-Resistance  
175°C Operating Temperature  
Fast Switching  
Repetitive Avalanche Allowed up to Tjmax  
RDS(on) = 3.3mΩ  
G
ID = 75A  
S
Description  
Specifically designed for Automotive applications, this  
design of HEXFET® Power MOSFETs utilizes the lastest  
processing techniques to achieve extremely low on-  
resistance per silicon area. Additional features of this  
HEXFET power MOSFET are a 175°C junction operating  
temperature,fastswitchingspeedandimprovedrepetitive  
avalanche rating. These combine to make this design an  
extremelyefficientandreliabledeviceforuseinAutomotive  
applications and a wide variety of other applications.  
TO-220AB  
Absolute Maximum Ratings  
Parameter  
Max.  
240  
170  
75  
Units  
ID @ TC = 25°C  
ID @ TC = 100°C  
ID @ TC = 25°C  
IDM  
Continuous Drain Current, VGS @ 10V (Silicon limited)  
Continuous Drain Current, VGS @ 10V (See Fig.9)  
Continuous Drain Current, VGS @ 10V (Package limited)  
Pulsed Drain Current   
A
960  
330  
2.2  
PD @TC = 25°C  
Power Dissipation  
W
W/°C  
V
Linear Derating Factor  
VGS  
Gate-to-Source Voltage  
20  
EAS  
Single Pulse Avalanche Energy‚  
Single Pulse Avalanche Energy Tested Value†  
Avalanche Current  
510  
980  
mJ  
EAS (tested)  
IAR  
See Fig.12a, 12b, 15, 16  
A
EAR  
Repetitive Avalanche Energyꢀ  
Operating Junction and  
mJ  
TJ  
-55 to + 175  
TSTG  
Storage Temperature Range  
°C  
Soldering Temperature, for 10 seconds  
300 (1.6mm from case )  
Thermal Resistance  
Parameter  
Junction-to-Case  
Case-to-Sink, Flat, Greased Surface  
Junction-to-Ambient  
Typ.  
–––  
0.50  
–––  
Max.  
0.45  
–––  
62  
Units  
RθJC  
RθCS  
RθJA  
°C/W  
www.irf.com  
1
12/11/02  
IRF1503  
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)  
Parameter  
Min. Typ. Max. Units  
30 ––– –––  
Conditions  
VGS = 0V, ID = 250µA  
V(BR)DSS  
Drain-to-Source Breakdown Voltage  
V
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.028 ––– V/°C Reference to 25°C, ID = 1mA  
RDS(on)  
VGS(th)  
gfs  
Static Drain-to-Source On-Resistance  
Gate Threshold Voltage  
–––  
2.0  
75  
2.6 3.3  
––– 4.0  
––– –––  
mVGS = 10V, ID = 140A ƒ  
V
S
VDS = 10V, ID = 250µA  
VDS = 25V, ID = 140A  
Forward Transconductance  
––– ––– 20  
––– ––– 250  
––– ––– 200  
––– ––– -200  
––– 130 200  
VDS = 30V, VGS = 0V  
IDSS  
Drain-to-Source Leakage Current  
µA  
nA  
VDS = 30V, VGS = 0V, TJ = 125°C  
VGS = 20V  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Total Gate Charge  
IGSS  
VGS = -20V  
Qg  
ID = 140A  
Qgs  
Qgd  
td(on)  
tr  
Gate-to-Source Charge  
Gate-to-Drain ("Miller") Charge  
Turn-On Delay Time  
Rise Time  
–––  
–––  
–––  
36  
41  
54  
62  
nC VDS = 24V  
VGS = 10V  
17 –––  
VDD = 15V  
––– 130 –––  
ID = 140A  
ns  
td(off)  
tf  
Turn-Off Delay Time  
Fall Time  
–––  
–––  
59 –––  
48 –––  
RG = 2.5Ω  
VGS = 10V ƒ  
D
S
Between lead,  
5.0  
LD  
LS  
Internal Drain Inductance  
Internal Source Inductance  
–––  
–––  
–––  
–––  
6mm (0.25in.)  
nH  
G
from package  
13  
and center of die contact  
Ciss  
Input Capacitance  
––– 5730 –––  
––– 2250 –––  
––– 290 –––  
––– 7580 –––  
––– 2290 –––  
––– 3420 –––  
VGS = 0V  
Coss  
Output Capacitance  
pF  
VDS = 25V  
Crss  
Reverse Transfer Capacitance  
Output Capacitance  
ƒ = 1.0MHz, See Fig. 5  
Coss  
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz  
VGS = 0V, VDS = 24V, ƒ = 1.0MHz  
VGS = 0V, VDS = 0V to 24V  
Coss  
Output Capacitance  
Coss eff.  
Effective Output Capacitance „  
Source-Drain Ratings and Characteristics  
Parameter  
Continuous Source Current  
(Body Diode)  
Min. Typ. Max. Units  
Conditions  
MOSFET symbol  
D
IS  
240  
––– –––  
showing the  
A
G
ISM  
Pulsed Source Current  
(Body Diode)   
integral reverse  
––– ––– 960  
S
p-n junction diode.  
VSD  
trr  
Diode Forward Voltage  
Reverse Recovery Time  
Reverse RecoveryCharge  
Forward Turn-On Time  
––– ––– 1.3  
––– 71 110  
––– 110 170  
V
TJ = 25°C, IS = 140A, VGS = 0V ƒ  
TJ = 25°C, IF = 140A, VDD = 15V  
di/dt = 100A/µs ƒ  
ns  
nC  
Qrr  
ton  
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)  
Notes:  
 Repetitive rating; pulse width limited by  
max. junction temperature. (See fig. 11).  
‚ Starting TJ = 25°C, L = 0.049mH  
RG = 25, IAS = 140A. (See Figure 12).  
ƒ Pulse width 400µs; duty cycle 2%.  
„ Coss eff. is a fixed capacitance that gives the same charging time  
as Coss while VDS is rising from 0 to 80% VDSS  
.
†
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive  
avalanche performance.  
This value determined from sample failure population. 100%  
tested to this value in production.  
2
www.irf.com  
IRF1503  
1000  
100  
10  
1000  
100  
10  
VGS  
15V  
VGS  
15V  
TOP  
TOP  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
10V  
8.0V  
7.0V  
6.0V  
5.5V  
5.0V  
BOTTOM4.5V  
BOTTOM4.5V  
4.5V  
4.5V  
20µs PULSE WIDTH  
Tj = 25°C  
20µs PULSE WIDTH  
Tj = 175°C  
1
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
V
, Drain-to-Source Voltage (V)  
DS  
DS  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
1000  
200  
T
= 25°C  
T
= 175°C  
J
J
T
= 175°C  
160  
120  
80  
J
T
= 25°C  
J
100  
40  
V
= 25V  
V
= 25V  
DS  
20µs PULSE WIDTH  
DS  
20µs PULSE WIDTH  
10  
0
4.0  
5.0  
V
6.0  
7.0  
8.0  
9.0  
10.0  
0
40  
80  
120  
160  
200  
, Gate-to-Source Voltage (V)  
I
D,  
Drain-to-Source Current (A)  
GS  
Fig 3. Typical Transfer Characteristics  
Fig 4. Typical Forward Transconductance  
Vs. Drain Current  
www.irf.com  
3
IRF1503  
10000  
8000  
6000  
4000  
2000  
20  
16  
12  
8
V
C
= 0V,  
= C  
f = 1 MHZ  
+ C C  
GS  
I = 140A  
D
,
V
= 24V  
iss  
gs  
gd  
ds  
DS  
SHORTED  
C
= C  
rss  
gd  
C
= C + C  
oss  
ds  
gd  
Ciss  
Coss  
4
Crss  
10  
0
0
1
0
40  
Q
80  
120  
160  
200  
100  
Total Gate Charge (nC)  
G
V
, Drain-to-Source Voltage (V)  
DS  
Fig 6. Typical Gate Charge Vs.  
Fig 5. Typical Capacitance Vs.  
Gate-to-Source Voltage  
Drain-to-Source Voltage  
1000.0  
10000  
OPERATION IN THIS AREA  
LIMITED BY R (on)  
DS  
1000  
100  
10  
100.0  
10.0  
1.0  
T
= 175°C  
J
100µsec  
1msec  
T
= 25°C  
10msec  
J
Tc = 25°C  
Tj = 175°C  
Single Pulse  
V
= 0V  
GS  
1
0.1  
1
10  
100  
0.0  
0.4  
0.8  
1.2  
1.6  
2.0  
V
, Drain-toSource Voltage (V)  
V
, Source-toDrain Voltage (V)  
DS  
SD  
Fig 8. Maximum Safe Operating Area  
Fig 7. Typical Source-Drain Diode  
Forward Voltage  
4
www.irf.com  
IRF1503  
2.0  
1.5  
1.0  
0.5  
0.0  
240  
200  
160  
120  
80  
240A  
=
I
D
LIMITED BY PACKAGE  
40  
V
= 10V  
GS  
0
-60 -40 -20  
0
20 40 60 80 100 120 140 160 180  
°
25  
50  
75  
100  
125  
150  
175  
T , Junction Temperature  
( C)  
°
( C)  
T
, Case Temperature  
J
C
Fig 10. Normalized On-Resistance  
Fig 9. Maximum Drain Current Vs.  
Vs. Temperature  
Case Temperature  
1
D = 0.50  
0.20  
0.1  
0.10  
0.05  
SINGLE PULSE  
(THERMAL RESPONSE)  
0.02  
0.01  
P
DM  
0.01  
t
1
t
2
Notes:  
1. Duty factor D =  
t
/ t  
1
2
2. Peak T  
= P  
x
Z
+ T  
J
DM  
thJC  
C
0.001  
0.00001  
0.0001  
0.001  
0.01  
0.1  
t , Rectangular Pulse Duration (sec)  
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case  
www.irf.com  
5
IRF1503  
1000  
800  
600  
400  
200  
0
I
15V  
D
TOP  
59A  
100A  
140A  
BOTTOM  
DRIVER  
+
L
V
DS  
D.U.T  
AS  
R
G
V
DD  
-
I
A
2
V0GVS  
0.01  
t
p
Fig 12a. Unclamped Inductive Test Circuit  
V
(BR)DSS  
t
p
25  
50  
75  
100  
125  
150  
175  
°
( C)  
Starting T , Junction Temperature  
J
I
AS  
Fig 12c. Maximum Avalanche Energy  
Fig 12b. Unclamped Inductive Waveforms  
Vs. Drain Current  
Q
G
10 V  
Q
Q
GD  
GS  
4.0  
3.0  
2.0  
1.0  
V
G
I
= 250µA  
D
Charge  
Fig 13a. Basic Gate Charge Waveform  
Current Regulator  
Same Type as D.U.T.  
50KΩ  
.2µF  
12V  
.3µF  
+
V
DS  
D.U.T.  
-
V
GS  
-75 -50 -25  
0
25 50 75 100 125 150 175 200  
, Temperature ( °C )  
3mA  
T
J
I
I
D
G
Current Sampling Resistors  
Fig 14. Threshold Voltage Vs. Temperature  
Fig 13b. Gate Charge Test Circuit  
6
www.irf.com  
IRF1503  
10000  
1000  
100  
10  
Duty Cycle = Single Pulse  
Allowed avalanche Current vs  
avalanche pulsewidth, tav  
assuming Tj = 25°C due to  
avalanche losses. Note: In no  
case should Tj be allowed to  
exceed Tjmax  
0.01  
0.05  
0.10  
1
1.0E-07  
1.0E-06  
1.0E-05  
1.0E-04  
1.0E-03  
1.0E-02  
1.0E-01  
tav (sec)  
Fig 15. Typical Avalanche Current Vs.Pulsewidth  
600  
500  
400  
300  
200  
100  
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:  
(For further info, see AN-1005 at www.irf.com)  
1. Avalanche failures assumption:  
Purely a thermal phenomenon and failure occurs at a  
temperature far in excess of Tjmax. This is validated for  
every part type.  
2. Safe operation in Avalanche is allowed as long asTjmax is  
not exceeded.  
3. Equation below based on circuit and waveforms shown in  
Figures 12a, 12b.  
TOP  
BOTTOM 50% Duty Cycle  
= 140A  
Single Pulse  
I
D
4. PD (ave) = Average power dissipation per single  
avalanche pulse.  
5. BV = Rated breakdown voltage (1.3 factor accounts for  
voltage increase during avalanche).  
6. Iav = Allowable avalanche current.  
7. T = Allowable rise in junction temperature, not to exceed  
Tjmax (assumed as 25°C in Figure 15, 16).  
tav = Average time in avalanche.  
25  
50  
75  
100  
125  
150  
175  
D = Duty cycle in avalanche = tav ·f  
ZthJC(D, tav) = Transient thermal resistance, see figure 11)  
Starting T , Junction Temperature (°C)  
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC  
Fig 16. Maximum Avalanche Energy  
Iav = 2DT/ [1.3·BV·Zth]  
EAS (AR) = PD (ave)·tav  
Vs. Temperature  
www.irf.com  
7
IRF1503  
Driver Gate Drive  
P.W.  
P.W.  
Period  
Period  
D =  
D.U.T  
+
*
=10V  
V
GS  
ƒ
Circuit Layout Considerations  
Low Stray Inductance  
Ground Plane  
Low Leakage Inductance  
Current Transformer  
-
D.U.T. I Waveform  
SD  
+
‚
-
Reverse  
Recovery  
Current  
Body Diode Forward  
„
Current  
di/dt  
-
+
D.U.T. V Waveform  
DS  
Diode Recovery  
dv/dt  

V
DD  
VDD  
Re-Applied  
Voltage  
dv/dt controlled by RG  
RG  
+
-
Body Diode  
Forward Drop  
Driver same type as D.U.T.  
ISD controlled by Duty Factor "D"  
D.U.T. - Device Under Test  
Inductor Curent  
I
SD  
Ripple 5%  
* VGS = 5V for Logic Level Devices  
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel  
HEXFET® Power MOSFETs  
RD  
VDS  
VGS  
D.U.T.  
RG  
+VDD  
-
10V  
Pulse Width ≤ 1 µs  
Duty Factor ≤ 0.1 %  
Fig 18a. Switching Time Test Circuit  
V
DS  
90%  
10%  
V
GS  
t
t
r
t
t
f
d(on)  
d(off)  
Fig 18b. Switching Time Waveforms  
8
www.irf.com  
IRF1503  
Package Outline  
TO-220AB  
Dimensions are shown in millimeters (inches)  
10.54 (.415)  
10.29 (.405)  
- B -  
3.78 (.149)  
3.54 (.139)  
2.87 (.113)  
2.62 (.103)  
4.69 (.185)  
4.20 (.165)  
1.32 (.052)  
1.22 (.048)  
- A -  
6.47 (.255)  
6.10 (.240)  
4
15.24 (.600)  
14.84 (.584)  
1.15 (.045)  
MIN  
LEAD ASSIGNMENTS  
1 - GATE  
1
2
3
2 - DRAIN  
3 - SOURCE  
4 - DRAIN  
14.09 (.555)  
13.47 (.530)  
4.06 (.160)  
3.55 (.140)  
0.93 (.037)  
0.69 (.027)  
0.55 (.022)  
0.46 (.018)  
3X  
3X  
1.40 (.055)  
3X  
1.15 (.045)  
0.36 (.014)  
M
B A M  
2.92 (.115)  
2.64 (.104)  
2.54 (.100)  
2X  
NOTES:  
1
2
DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.  
CONTROLLING DIMENSION : INCH  
3
4
OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.  
HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.  
Part Marking Information  
TO-220AB  
EXAMPLE : THIS IS AN IRF1010  
WITH ASSEMBLY  
A
INTERNATIONAL  
RECTIFIER  
LOGO  
PART NUMBER  
LOT CODE 9B1M  
IRF1010  
9246  
9B 1M  
DATE CODE  
(YYWW)  
ASSEMBLY  
LOT CODE  
YY = YEAR  
WW = WEEK  
TO-220AB package is not recommended for Surface Mount Application.  
Data and specifications subject to change without notice.  
This product has been designed and qualified for Automotive [Q101] market.  
Qualification Standards can be found on IR’s Web site.  
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105  
TAC Fax: (310) 252-7903  
Visit us at www.irf.com for sales contact information. 12/02  
www.irf.com  
9

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