IRF3610S [INFINEON]
Power Field-Effect Transistor, 103A I(D), 100V, 0.0116ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, PLASTIC, D2PAK-3;
| 型号： | IRF3610S |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 103A I(D), 100V, 0.0116ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, PLASTIC, D2PAK-3 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97638A
IRF3610SPbF
HEXFET® Power MOSFET
Applications
D
S
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
VDSS
RDS(on) typ.
100V
9.3m
Ω
G
max.
11.6m
Ω
ID
103A
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
D
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
G
D2Pak
IRF3610SPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Max.
103
Units
A
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
73
410
Pulsed Drain Current
PD @TC = 25°C
W
333
Maximum Power Dissipation
Linear Derating Factor
2.2
W/°C
V
VGS
± 20
Gate-to-Source Voltage
23
Peak Diode Recovery
dv/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
°C
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case)
Avalanche Characteristics
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
EAS
460
mJ
A
IAR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.50
40
Units
°C/W
RθJC
Junction-to-Case
RθJA
–––
Junction-to-Ambient (PCB Mount)
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1
09/23/11
IRF3610SPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
100 ––– –––
––– 0.10 ––– V/°C Reference to 25°C, ID = 1.0mA
Conditions
VGS = 0V, ID = 250μA
V
–––
2.0
9.3 11.6
––– 4.0
VGS = 10V, ID = 62A
VDS = VGS, ID = 250μA
VDS = 25V, ID = 62A
mΩ
V
Forward Transconductance
110 ––– –––
S
RG
Internal Gate Resistance
–––
2.2
–––
20
Ω
IDSS
Drain-to-Source Leakage Current
––– –––
μA VDS = 100V, VGS = 0V
DS = 100V, VGS = 0V, TJ = 125°C
nA VGS = 20V
GS = -20V
––– ––– 250
––– ––– 200
––– ––– -200
V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Total Gate Charge
Gate-to-Source Charge
Min. Typ. Max. Units
––– 100 150 nC ID = 62A
DS =50V
VGS = 10V
ID = 62A, VDS =0V, VGS = 10V
ns VDD = 65V
Conditions
Qg
Qgs
–––
–––
–––
–––
–––
–––
–––
23
42
58
15
55
77
43
–––
–––
–––
–––
–––
–––
–––
V
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Qsync
td(on)
Turn-On Delay Time
tr
Rise Time
ID = 62A
td(off)
Turn-Off Delay Time
R = 2.7
Ω
G
tf
Fall Time
VGS = 10V
Ciss
Input Capacitance
––– 5380 –––
––– 690 –––
––– 100 –––
––– 560 –––
––– 750 –––
pF VGS = 0V
Coss
Output Capacitance
VDS = 25V
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0 MHz, See Fig. 5
Coss eff. (ER)
Coss eff. (TR)
V
GS = 0V, VDS = 0V to 80V , See Fig. 11
GS = 0V, VDS = 0V to 80V
V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
––– –––
––– ––– 410
––– ––– 1.3
A
MOSFET symbol
103
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
showing the
integral reverse
G
ISM
A
S
p-n junction diode.
TJ = 25°C, IS = 62A, VGS = 0V
VSD
trr
V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
––– 110 –––
––– 120 –––
––– 570 –––
––– 710 –––
––– -9.5 –––
ns
IF = 62A
di/dt = 100A/μs
Qrr
Reverse Recovery Charge
nC
A
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.24mH
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom-
RG = 50Ω, IAS = 62A, VGS =10V. Part not recommended for use
above this value.
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
ISD ≤ 62A, di/dt ≤ 1935A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same charging
time as Coss while VDS is rising from 0 to 80% VDSS
.
2
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IRF3610SPbF
1000
100
10
1000
100
10
VGS
15V
10V
6.0V
5.0V
4.7V
4.5V
4.2V
4.0V
VGS
15V
10V
6.0V
5.0V
4.7V
4.5V
4.2V
4.0V
TOP
TOP
BOTTOM
BOTTOM
4.0V
1
4.0V
60μs PULSE WIDTH
Tj = 175°C
≤
60μs PULSE WIDTH
Tj = 25°C
≤
1
0.1
0.1
1
10
100
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 62A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
DS
= 50V
≤
60μs PULSE WIDTH
0.1
2
3
4
5
6
7
8
9
10 11
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
14.0
100000
10000
1000
100
V
= 0V,
= C
f = 1 MHZ
GS
I = 62A
D
C
C
C
+ C , C
SHORTED
ds
iss
gs
gd
12.0
= C
rss
oss
gd
= C + C
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
ds
gd
10.0
8.0
6.0
4.0
2.0
0.0
C
C
iss
oss
C
rss
10
0
20
40
60
80
100 120 140
1
10
, Drain-to-Source Voltage (V)
100
Q , Total Gate Charge (nC)
V
G
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRF3610SPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100
10
100μsec
1msec
10msec
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
DC
V
= 0V
GS
Single Pulse
1.0
0.1
0.0
0.5
1.0
1.5
2.0
0.1
1
10
100
V
, Source-to-Drain Voltage (V)
V
DS
, Drain-toSource Voltage (V)
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
125
120
115
110
105
100
95
120
100
80
60
40
20
0
I
= 1.0mA
D
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T , Temperature ( °C )
J
Fig 10. Drain-to-Source Breakdown Voltage
T
, Case Temperature (°C)
C
Fig 9. Maximum Drain Current vs.
Case Temperature
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2000
I
D
TOP
13A
27A
BOTTOM 62A
1600
1200
800
400
0
-20
0
20
40
60
80
100 120
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
Drain-to-Source Voltage (V)
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRF3610SPbF
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
0.02
0.01
0.001
SINGLE PULSE
Notes:
1. Duty Factor D = t1/t2
( THERMAL RESPONSE )
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
Δ
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
ΔΤ
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
500
400
300
200
100
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
= 62A
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRF3610SPbF
60
50
40
30
20
10
0
4.5
4.0
3.5
3.0
I = 41A
F
V
= 85V
R
T = 25°C
J
T = 125°C
J
I
I
I
= 250μA
D
D
D
2.5
2.0
1.5
= 1.0mA
= 1.0A
100 200 300 400 500 600 700 800 900 1000
-100
-50
0
50
100
150
200
di /dt (A/μs)
T , Temperature ( °C )
F
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
4000
60
I = 62A
I = 41A
F
F
3500
3000
2500
2000
1500
1000
500
V
= 85V
V
= 85V
R
R
50
40
30
20
10
0
T = 25°C
T = 25°C
J
J
T = 125°C
T = 125°C
J
J
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
4000
I = 62A
F
3500
3000
2500
2000
1500
1000
500
V
= 85V
R
T = 25°C
J
T = 125°C
J
100 200 300 400 500 600 700 800 900 1000
di /dt (A/μs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRF3610SPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2μF
12V
.3μF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRF3610SPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRF3610SPbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/2011
www.irf.com
9
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