IRF3707ZCLPBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRF3707ZCLPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总11页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95464
IRF3707ZCSPbF
IRF3707ZCLPbF
HEXFET® Power MOSFET
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l Lead-Free
VDSS RDS(on) max
Qg
9.5m:
30V
9.7nC
Benefits
l Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D2Pak
TO-262
IRF3707ZCS
IRF3707ZCL
Absolute Maximum Ratings
Parameter
Max.
Units
VDS
Drain-to-Source Voltage
30
± 20
59
V
V
Gate-to-Source Voltage
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
@ TC = 25°C
A
D
D
42
@ TC = 100°C
230
57
DM
P
P
@TC = 25°C
Maximum Power Dissipation
Maximum Power Dissipation
W
D
D
@TC = 100°C
28
Linear Derating Factor
Operating Junction and
0.38
-55 to + 175
W/°C
°C
T
J
T
Storage Temperature Range
STG
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case)
10 lbf in (1.1 N m)
Thermal Resistance
Parameter
Typ.
–––
Max.
2.653
40
Units
°C/W
RθJC
Junction-to-Case
RθJA
–––
Junction-to-Ambient (PCB Mount)
Notes through are on page 11
www.irf.com
1
6/29/04
IRF3707ZCS/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
30 ––– –––
Conditions
VGS = 0V, ID = 250µA
BVDSS
V
∆ΒVDSS/∆TJ
RDS(on)
Breakdown Voltage Temp. Coefficient ––– 0.023 ––– mV/°C Reference to 25°C, ID = 1mA
mΩ
Static Drain-to-Source On-Resistance
–––
–––
7.5
10
9.5
VGS = 10V, ID = 21A
GS = 4.5V, ID = 17A
VDS = VGS, ID = 250µA
12.5
V
VGS(th)
Gate Threshold Voltage
1.35 1.80 2.25
V
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
81
-5.3
–––
–––
–––
––– mV/°C
1.0
150
100
µA
V
V
DS = 24V, VGS = 0V
DS = 24V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
nA VGS = 20V
GS = -20V
––– -100
V
gfs
–––
9.7
2.8
1.0
3.4
2.5
4.4
6.2
9.8
41
–––
15
S
VDS = 15V, ID = 17A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
td(on)
tr
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
VDS = 15V
nC
VGS = 4.5V
ID = 17A
Gate Charge Overdrive
See Fig. 16
Switch Charge (Qgs2 + Qgd)
Output Charge
nC
V
V
DS = 16V, VGS = 0V
Turn-On Delay Time
Rise Time
DD = 15V, VGS = 4.5V
ID = 17A
ns Clamped Inductive Load
td(off)
tf
Turn-Off Delay Time
Fall Time
12
3.6
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 1210 –––
V
V
GS = 0V
–––
–––
260
130
–––
–––
pF
DS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Typ.
–––
–––
–––
Max.
Units
mJ
A
Single Pulse Avalanche Energy
EAS
IAR
40
23
Avalanche Current
Repetitive Avalanche Energy
EAR
5.7
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
59
IS
D
S
Continuous Source Current
–––
–––
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
ISM
–––
–––
230
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
14
1.0
21
V
T = 25°C, I = 17A, V = 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
ns T = 25°C, I = 17A, VDD = 15V
J F
Qrr
di/dt = 100A/µs
5.2
7.8
nC
2
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IRF3707ZCS/LPbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
BOTTOM
BOTTOM
30V
3.0V
30µs PULSE WIDTH
Tj = 175°C
30µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
0.1
1
10
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
1.5
1.0
0.5
I
= 42A
D
V
= 10V
GS
T
= 25°C
J
T
= 175°C
J
100
V
= 10V
DS
30µs PULSE WIDTH
10.0
2
3
4
5
6
7
8
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
vs. Temperature
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3
IRF3707ZCS/LPbF
100000
6.0
5.0
4.0
3.0
2.0
1.0
0.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 17A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
= C
rss
oss
gd
= C + C
V
V
= 24V
= 15V
DS
DS
ds
gd
10000
1000
100
C
iss
C
C
oss
rss
10
1
10
100
0
2
4
6
8
10
12
V
, Drain-to-Source Voltage (V)
Q
Total Gate Charge (nC)
DS
G
Fig 6. Typical Gate Charge vs.
Fig 5. Typical Capacitance vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
1.00
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100µsec
1msec
T
= 25°C
J
1
0.10
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.01
0.1
0.0
0.5
1.0
1.5
2.0
0
1
10
100
1000
V
, Source-to-Drain Voltage (V)
V
DS
, Drain-to-Source Voltage (V)
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF3707ZCS/LPbF
60
50
40
30
20
10
0
2.5
2.0
1.5
1.0
0.5
Limited By Package
I
= 250µA
D
-75 -50 -25
0
25 50 75 100 125 150 175 200
25
50
75
100
125
150
175
T
, Temperature ( °C )
T
, Case Temperature (°C)
J
C
Fig 9. Maximum Drain Current vs.
Fig 10. Threshold Voltage vs. Temperature
Case Temperature
10
D = 0.50
1
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
0.1
0.01
τ
JτJ
τ
τ
0.02
0.01
Cτ
1.163
1.073
0.419
0.000257
0.001040
0.003089
τ
1τ1
τ
2τ2
3τ3
Ci= τi/Ri
Ci= τi/Ri
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3707ZCS/LPbF
15V
175
150
125
100
75
I
D
TOP
4.5A
6.8A
DRIVER
L
V
DS
BOTTOM 23A
D.U.T
AS
R
G
+
-
V
DD
I
A
V
2
GS
0.01
Ω
t
p
Fig 12a. Unclamped Inductive Test Circuit
50
V
25
(BR)DSS
t
p
0
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
LD
I
AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
-
VDD
D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
.2µF
12V
.3µF
Fig 14a. Switching Time Test Circuit
VDS
+
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
VGS
I
I
D
G
Current Sampling Resistors
td(on)
td(off)
tr
tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF3707ZCS/LPbF
Driver Gate Drive
P.W.
Period
Period
D =
D.U.T
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
•
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF3707ZCS/LPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
loss
conduction
drive
output
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
⎛
⎜
Qoss
⎞
⎠
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
(
)
in
rr
in
⎝ 2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on)
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
⎛
⎛
Qgd
ig
⎞
Qgs2
ig
⎞
⎟
⎜
⎟
⎜
+ I ×
× V × f + I ×
× V × f
in
in
⎝
⎠
⎝
⎠
+ Q × V × f
(
)
g
g
⎛ Qoss
⎞
⎠
+
×V × f
in
⎝
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
www.irf.com
IRF3707ZCS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 530S WIT H
P AR T N U MB E R
D AT E COD E
L OT COD E 8024
AS S E MB L E D ON WW 02, 2000
IN T H E AS S E MB L Y L IN E "L "
IN T E R N AT IONAL
R E CT IF IE R
L OGO
F 530S
N ote: "P " in as s embly line
pos ition indicates "L ead-F ree"
YE AR
WE E K 02
L IN E
0 = 2000
AS S E MB L Y
L OT COD E
L
OR
P AR T N U MB E R
IN T E R N AT ION AL
R E CT IF IE R
L OGO
F 530S
D AT E CODE
P
=
DE S IGN AT E S L E AD -F R E E
P R OD U CT (OP T ION AL )
AS S E MB L Y
L OT CODE
YE AR
W E E K 02
A = AS S E M B L Y S IT E CODE
0 = 2000
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9
IRF3707ZCS/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 7 = 1997
WEEK 19
Note: "P" in assembly line
position indicates "Lead-Free"
AS S E MB LY
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
AS S E MB LY
LOT CODE
WEEK 19
A= ASSEMBLY SITE CODE
10
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IRF3707ZCS/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.15mH, RG = 25Ω,
IAS = 23A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
ꢀ This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 42A.
charging time as Coss while VDS is rising from 0 to
80% VDSS
.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 6/04
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11
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