IRF3709ZL [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET型号: | IRF3709ZL |
厂家: | Infineon |
描述: | HEXFET Power MOSFET |
文件: | 总12页 (文件大小:334K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 95835
IRF3709Z
IRF3709ZS
IRF3709ZL
HEXFET® Power MOSFET
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
VDSS RDS(on) max
Qg
6.3m:
30V
17nC
Benefits
l Low RDS(on) at 4.5V VGS
l Low Gate Charge
l Fully Characterized Avalanche Voltage
and Current
D2Pak
IRF3709ZS
TO-262
IRF3709ZL
TO-220AB
IRF3709Z
Absolute Maximum Ratings
Parameter
Max.
Units
VDS
Drain-to-Source Voltage
30
± 20
87
V
V
Gate-to-Source Voltage
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
@ TC = 25°C
A
D
D
62
@ TC = 100°C
350
79
DM
P
P
@TC = 25°C
Maximum Power Dissipation
Maximum Power Dissipation
W
D
D
@TC = 100°C
40
Linear Derating Factor
Operating Junction and
0.53
W/°C
°C
T
-55 to + 175
J
T
Storage Temperature Range
STG
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case)
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
Max.
1.89
40
Units
°C/W
RθJC
Junction-to-Case
RθJA
–––
Junction-to-Ambient (PCB Mount)
Notes through are on page 12
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1
1/16/04
IRF3709Z/S/L
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
30 ––– –––
Conditions
VGS = 0V, ID = 250µA
BVDSS
V
∆ΒVDSS/∆TJ
RDS(on)
Breakdown Voltage Temp. Coefficient ––– 0.021 ––– mV/°C Reference to 25°C, ID = 1mA
mΩ
Static Drain-to-Source On-Resistance
–––
–––
1.35
–––
–––
–––
–––
–––
88
5.0
6.2
6.3
7.8
VGS = 10V, ID = 21A
VGS = 4.5V, ID = 17A
VDS = VGS, ID = 250µA
VGS(th)
Gate Threshold Voltage
–––
-5.5
–––
–––
–––
2.25
V
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
––– mV/°C
1.0
150
100
µA
V
V
DS = 24V, VGS = 0V
DS = 24V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
nA VGS = 20V
GS = -20V
––– -100
V
gfs
–––
17
–––
26
S
VDS = 15V, ID = 17A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
td(on)
tr
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
4.4
1.7
6.0
4.9
7.7
11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
VDS = 15V
nC
VGS = 4.5V
ID = 17A
Gate Charge Overdrive
See Fig. 14a&b
Switch Charge (Qgs2 + Qgd)
Output Charge
nC VDS = 16V, VGS = 0V
DD = 15V, VGS = 4.5V
Turn-On Delay Time
Rise Time
13
V
41
ID = 17A
td(off)
tf
Turn-Off Delay Time
Fall Time
16
ns Clamped Inductive Load
4.7
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 2130 –––
V
V
GS = 0V
–––
–––
450
220
–––
–––
pF
DS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
Units
mJ
A
EAS
IAR
60
17
Avalanche Current
Repetitive Avalanche Energy
EAR
7.9
mJ
Diode Characteristics
Parameter
Continuous Source Current
Min. Typ. Max. Units
Conditions
MOSFET symbol
87
D
IS
–––
–––
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
ISM
–––
–––
350
S
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
16
1.0
24
V
T = 25°C, I = 17A, V = 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
ns T = 25°C, I = 17A, VDD = 15V
J F
Qrr
di/dt = 100A/µs
6.2
9.3
nC
2
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IRF3709Z/S/L
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
9.0V
7.0V
5.0V
4.5V
4.0V
3.5V
3.0V
BOTTOM
BOTTOM
3.0V
3.0V
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
≤
Tj = 25°C
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.0
1.5
1.0
0.5
I
= 42A
D
V
= 10V
GS
T
= 175°C
J
1
T
= 25°C
J
V
= 15V
DS
≤
60µs PULSE WIDTH
0.1
0
1
2
3
4
5
6
7
8
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
vs. Temperature
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3
IRF3709Z/S/L
10000
6.0
5.0
4.0
3.0
2.0
1.0
0.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 17A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
= C
rss
oss
gd
= C + C
V
V
= 24V
= 15V
DS
DS
ds
gd
C
iss
1000
C
oss
C
rss
100
1
10
100
0
5
10
15
20
25
Q
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge vs.
Fig 5. Typical Capacitance vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100µsec
1msec
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
10msec
V
= 0V
GS
1.00
0.1
0.0
0.5
1.0
1.5
2.0
2.5
0
1
10
100
1000
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF3709Z/S/L
2.5
2.0
1.5
1.0
0.5
90
80
70
60
50
40
30
20
10
0
Limited By Package
I
= 250µA
D
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
25
50
75
100
125
150
175
T
T
, Case Temperature (°C)
J
C
Fig 9. Maximum Drain Current vs.
Fig 10. Threshold Voltage vs. Temperature
Case Temperature
10
1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
Ri (°C/W) τi (sec)
0.1
0.01
τ
J τJ
τ
0.832
0.000221
τ
Cτ
0.02
0.01
1τ1
Ci= τi/Ri
τ
2τ2
1.058
0.001171
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3709Z/S/L
9.00
16
14
12
10
8
Vgs = 10V
I
= 21A
D
8.00
T
= 125°C
J
7.00
6.00
5.00
4.00
T
= 125°C
J
6
T
= 25°C
J
T
= 25°C
4
J
2
0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
2
3
4
5
6
7
8
9
10
I , Drain Current (A)
D
V
Gate -to -Source Voltage (V)
GS,
Fig 12. On-Resistance vs. Drain Current
Fig 13. On-Resistance vs. Gate Voltage
Current Regulator
Same Type as D.U.T.
Id
Vds
50KΩ
.2µF
Vgs
12V
.3µF
250
+
I
V
DS
D
D.U.T.
-
TOP
5.4A
8.0A
Vgs(th)
V
GS
200
150
100
50
3mA
BOTTOM 17A
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 14a&b. Basic Gate Charge Test Circuit
and Waveform
15V
V
(BR)DSS
DRIVER
L
t
p
V
DS
D.U.T
AS
R
G
+
-
0
V
DD
I
A
25
50
75
100
125
150
175
20V
0.01
Ω
t
p
I
AS
Starting T , Junction Temperature (°C)
J
Fig 16. Maximum Avalanche Energy
Fig 15a&b. Unclamped Inductive Test circuit
vs. Drain Current
and Waveforms
6
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IRF3709Z/S/L
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
•
dv/dt controlled by RG
• Driver same type as D.U.T.
RG
+
-
Body Diode
Forward Drop
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
LD
VDS
+
-
VDD
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
td(off)
tr
tf
Fig 18b. Switching Time Waveforms
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7
IRF3709Z/S/L
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
loss
conduction
drive
output
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
⎛
⎜
Qoss
⎞
⎠
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
(
)
in
rr
in
⎝ 2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on)
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
⎛
⎛
Qgd
ig
⎞
Qgs2
ig
⎞
⎟
⎜
⎟
⎜
+ I ×
× V × f + I ×
× V × f
in
in
⎝
⎠
⎝
⎠
+ Q × V × f
(
)
g
g
⎛ Qoss
⎞
⎠
+
×V × f
in
⎝
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF3709Z/S/L
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
- B -
3.78 (.149)
3.54 (.139)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
HEXFET
IGBTs, CoPACK
2- DRAIN
3- SOURCE
1
2
3
1- GATE
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4- DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
4
TO-220AB Part Marking Information
Note: "P" in assembly line
position indicates "Lead-Free"
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9
IRF3709Z/S/L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
10
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IRF3709Z/S/L
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
IGBT
1- GATE
2- COLLEC-
TOR
TO-262 Part Marking Information
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11
IRF3709Z/S/L
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.42mH, RG = 25Ω,
IAS = 17A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
ꢀ This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 42A.
R is measured at TJ of approximately 90°C.
θ
charging time as Coss while VDS is rising from 0 to
80% VDSS
.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 01/04
12
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