IRF4104SPBF [INFINEON]
HEXFET㈢ Power MOSFET; HEXFET㈢功率MOSFET
| 型号： | IRF4104SPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET㈢ Power MOSFET |
| 文件： | 总13页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95468
IRF4104PbF
IRF4104SPbF
IRF4104LPbF
AUTOMOTIVE MOSFET
Features
HEXFET® Power MOSFET
l
Advanced Process Technology
l
l
l
l
l
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 40V
RDS(on) = 5.5mΩ
G
Description
ID = 75A
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processingtechniquestoachieveextremelylowon-
resistance per silicon area. Additional features of
thisdesign area175°Cjunctionoperatingtempera-
ture, fast switching speed and improved repetitive
avalanche rating . These features combine to make
thisdesignanextremelyefficientandreliabledevice
foruseinAutomotiveapplicationsandawidevariety
of other applications.
S
D2Pak
TO-262
IRF4104L
TO-220AB
IRF4104
IRF4104S
Absolute Maximum Ratings
Parameter
Max.
120
84
Units
(Silicon Limited)
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
I
@ T = 25°C
C
D
D
D
@ T = 100°C
C
A
(Package limited)
@ T = 25°C
C
75
470
140
DM
P
@T = 25°C
Power Dissipation
C
W
D
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
0.95
± 20
W/°C
V
V
GS
EAS (Thermally limited)
120
220
mJ
Single Pulse Avalanche Energy Tested Value
Avalanche Current
EAS (Tested )
IAR
See Fig.12a, 12b, 15, 16
A
Repetitive Avalanche Energy
EAR
mJ
T
J
Operating Junction and
-55 to + 175
T
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
Max.
1.05
–––
62
Units
°C/W
Rθ
JC
CS
JA
JA
Junction-to-Case
Rθ
Rθ
Rθ
0.50
–––
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
–––
40
Junction-to-Ambient (PCB Mount)
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1
6/30/04
IRF4104S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
40 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
V
Breakdown Voltage Temp. Coefficient ––– 0.032 ––– V/°C Reference to 25°C, ID = 1mA
mΩ
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
4.3
–––
–––
–––
–––
–––
–––
68
5.5
4.0
VGS = 10V, ID = 75A
VDS = VGS, ID = 250µA
VDS = 10V, ID = 75A
VGS(th)
V
V
gfs
Forward Transconductance
63
–––
20
IDSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA
V
DS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TJ = 125°C
250
200
-200
100
–––
–––
–––
–––
–––
–––
–––
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA VGS = 20V
VGS = -20V
Qg
Qgs
Qgd
td(on)
tr
ID = 75A
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
21
nC VDS = 32V
VGS = 10V
27
16
VDD = 20V
Rise Time
130
38
ID = 75A
td(off)
tf
Turn-Off Delay Time
ns RG = 6.8 Ω
VGS = 10V
Fall Time
77
LD
Internal Drain Inductance
4.5
Between lead,
nH 6mm (0.25in.)
from package
LS
Internal Source Inductance
–––
7.5
–––
and center of die contact
Ciss
Input Capacitance
––– 3000 –––
VGS = 0V
Coss
Output Capacitance
–––
–––
660
380
–––
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
pF ƒ = 1.0MHz
Coss
––– 2160 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
–––
560
850
–––
–––
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 32V
Coss eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
Continuous Source Current
–––
–––
75
MOSFET symbol
S
(Body Diode)
A
showing the
I
Pulsed Source Current
–––
–––
470
integral reverse
SM
(Body Diode)
p-n junction diode.
V
t
Diode Forward Voltage
–––
–––
–––
–––
23
1.3
35
10
V
T = 25°C, I = 75A, V = 0V
SD
J
S
GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T = 25°C, I = 75A, VDD = 20V
J F
rr
di/dt = 100A/µs
Q
t
6.8
nC
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
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IRF4104S/LPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
1
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 175°C
4.5V
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
120
T
= 25°C
T
= 25°C
J
J
100
80
60
40
20
0
T
= 175°C
J
100
10
1
T = 175°C
J
V
= 10V
V
= 15V
DS
380µs PULSE WIDTH
DS
20µs PULSE WIDTH
4
6
8
10 12
0
20
40
60
80
100
V
, Gate-to-Source Voltage (V)
I
Drain-to-Source Current (A)
GS
D,
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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3
IRF4104S/LPbF
5000
20
16
12
8
V
= 0V,
= C
f = 1 MHZ
GS
I = 75A
D
C
C
C
+ C , C
SHORTED
ds
iss
gs
gd
V
= 32V
= C
DS
VDS= 20V
rss
oss
gd
4000
3000
2000
1000
0
= C + C
ds
gd
Ciss
Coss
Crss
4
0
0
20
40
60
80
100
1
10
, Drain-to-Source Voltage (V)
100
Q
Total Gate Charge (nC)
V
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.0
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 175°C
J
T
= 25°C
100µsec
1msec
J
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
10msec
100
1
0.1
0
1
10
1000
0.2
0.6
1.0
1.4
1.8
V
, Drain-toSource Voltage (V)
V
, Source-toDrain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF4104S/LPbF
120
100
80
60
40
20
0
2.0
1.5
1.0
0.5
LIMITED BY PACKAGE
I
= 75A
D
V
= 10V
GS
25
50
75
100
125
150
175
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
, Junction Temperature (°C)
J
Fig 10. Normalized On-Resistance
Fig 9. Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
10
1
0.1
D = 0.50
0.20
R1
R2
R2
R3
R3
0.10
0.05
Ri (°C/W) τi (sec)
R1
τ
J τJ
τ
τ
Cτ
0.371
0.337
0.337
0.000272
0.001375
0.018713
τ
1τ1
τ
0.02
0.01
2 τ2
3τ3
0.01
Ci= τi/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF4104S/LPbF
500
400
300
200
100
0
15V
ID
11A
16A
TOP
BOTTOM 75A
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
2
V0GVS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
4.0
3.0
2.0
1.0
V
G
I
= 250µA
D
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
-75 -50 -25
0
25 50 75 100 125 150 175
3mA
T , Temperature ( °C )
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
www.irf.com
IRF4104S/LPbF
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
140
120
100
80
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
TOP
BOTTOM 1% Duty Cycle
= 75A
Single Pulse
I
D
60
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
40
6. Iav = Allowable avalanche current.
20
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
0
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Fig 16. Maximum Avalanche Energy
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRF4104S/LPbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b. Switching Time Waveforms
8
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IRF4104S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
3.78 (.149)
- B -
10.29 (.405)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
3.54 (.139)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
HEXFET
IGBTs, CoPACK
1
2
3
1- GATE
1- GATE
2- DRAIN
3- SOURCE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
4- DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1
2
DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
CONTROLLING DIMENSION : INCH
3
4
OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
PART NUMBER
AS S EMB LED ON WW 19, 1997
IN THE AS S EMBLY LINE "C"
INTE RNAT IONAL
RECT IFIER
LOGO
Note: "P" in assembly line
position indicates "Lead-Free"
DAT E CODE
YEAR 7 = 1997
WEEK 19
AS S EMBLY
LOT CODE
LINE C
www.irf.com
9
IRF4104S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 530S WIT H
P AR T N U MB E R
L OT CODE 8024
IN T E R N AT IONAL
R E CT IF IE R
L OGO
AS S E MB L E D ON WW 02, 2000
IN T H E AS S E MB L Y L INE "L "
F 530S
DAT E CODE
YE AR 0 = 2000
WE E K 02
N ote: "P " in as s embly line
pos ition indicates "L ead-F ree"
AS S E MB L Y
L OT CODE
L INE
L
OR
P AR T N U MB E R
IN T E R N AT ION AL
R E CT IF IE R
L OGO
F 530S
D AT E COD E
P
=
D E S IGN AT E S L E AD -F R E E
P R OD U CT (OP T ION AL )
AS S E MB L Y
L OT COD E
YE AR
W E E K 02
A = AS S E MB L Y S IT E COD E
0 = 2000
10
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IRF4104S/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
E XAMPLE : THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
LOGO
DATE CODE
YEAR 7 = 1997
WEEK 19
Note: "P" in assembly line
pos ition indicates "Lead-Free"
AS S E MBL Y
LOT CODE
LINE C
OR
PART NUMBER
DATE CODE
INTERNATIONAL
RECTIFIER
LOGO
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
ASSEMBLY
LOT CODE
WE EK 19
A= ASSEMBLY SITE CODE
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11
IRF4104S/LPbF
D2Pak Tape & Reel Infomation
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Notes:
ꢀ
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.04mH
This value determined from sample failure population. 100%
tested to this value in production.
R
G = 25Ω, IAS = 75A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the
same charging time as Coss while VDS is rising
This is only applied to TO-220AB pakcage.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
from 0 to 80% VDSS
.
TO-220AB package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101]market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 6/04
12
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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