IRF60R217 [INFINEON]

Power Field-Effect Transistor, 58A I(D), 60V, 0.0099ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, DPAK-3/2;


型号：	IRF60R217
厂家：	Infineon
描述：	Power Field-Effect Transistor, 58A I(D), 60V, 0.0099ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, DPAK-3/2 开关脉冲晶体管
文件：	总11页 (文件大小：464K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR MOSFET

StrongIRFET™

IRF60R217

Application

V_DSS

60V

 Brushed Motor drive applications

 BLDC Motor drive applications

Battery powered circuits

 Half-bridge and full-bridge topologies

 Synchronous rectifier applications

 Resonant mode power supplies

 OR-ing and redundant power switches

 DC/DC and AC/DC converters

 DC/AC Inverters

R_DS(on)typ.

max

8.0m

9.9m

58A

I_D

Benefits

 Improved Gate, Avalanche and Dynamic dV/dt Ruggedness

 Fully Characterized Capacitance and Avalanche SOA

 Enhanced body diode dV/dt and dI/dt Capability

 Lead-Free, RoHS Compliant

D-Pak

IRF60R217

Gate

Drain

Source

Base part number Package Type

Standard Pack

Form

Orderable Part Number

Quantity

Tape and Reel

2000

IRF60R217

D-Pak

= 35A

= 125°C

= 25°C

10 12 14 16 18 20

100

125

150

175

, Case Temperature (°C)

Gate -to -Source Voltage (V)

GS,

Fig 2. Maximum Drain Current vs. Case Temperature

Fig 1. Typical On-Resistance vs. Gate Voltage

2016-01-05

IRF60R217

Absolute Maximum Rating

Symbol

Parameter

Max.

Units

I_D@ T_C= 25°C

Continuous Drain Current, V_GS@ 10V (Silicon Limited)

I_D@ T_C= 100°C Continuous Drain Current, V_GS@ 10V (Silicon Limited)

I_DM

Pulsed Drain Current 

Maximum Power Dissipation

Linear Derating Factor

217

P_D@T_C= 25°C

W/°C

0.56

± 20

V_GS

Gate-to-Source Voltage

T_J

T_STG

Operating Junction and

Storage Temperature Range

Soldering Temperature, for 10 seconds (1.6mm from case)

-55 to + 175

300

°C

Avalanche Characteristics

E_{AS (Thermally limited)}

I_AR

E_AR

124

Single Pulse Avalanche Energy 

Single Pulse Avalanche Energy 

Avalanche Current 

See Fig 15, 16, 23a, 23b

Repetitive Avalanche Energy 

Thermal Resistance

Symbol

Parameter

Typ.

–––

Max.

1.8

Units

Junction-to-Case 

R_JC

R_JA

Junction-to-Ambient (PCB Mount) 

Junction-to-Ambient 

°C/W

110

Static @ T_J= 25°C (unless otherwise specified)

Symbol

Parameter

Min. Typ. Max. Units

60 ––– –––

––– 0.047 –––

Conditions

V_(BR)DSS

Drain-to-Source Breakdown Voltage

V_GS= 0V, I_D= 250µA

Breakdown Voltage Temp. Coefficient

V/°C Reference to 25°C, I_D= 1mA 

V_(BR)DSS/T_J

–––

2.1 –––

––– –––

––– ––– 150

––– ––– 100

––– ––– -100

8.0

9.9

–––

3.7

1.0

_GS= 10V, I_D= 35A 

_GS= 6.0V, I_D= 18A 

R_DS(on)

V_GS(th)

I_DSS

Static Drain-to-Source On-Resistance

Gate Threshold Voltage

m

V_DS= V_GS, I_D= 50µA

_DS= 60V, V_GS= 0V

V_DS= 60V,V_GS= 0V,T_J=125°C

Drain-to-Source Leakage Current

µA

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Gate Resistance

_GS= 20V

_GS= -20V

I_GSS

R_G

–––

2.0

–––



Notes:

Repetitive rating; pulse width limited by max. junction temperature.



Limited by T_Jmax, starting T_J= 25°C, L = 0.14mH, R_G= 50, I_AS= 35A, V_GS=10V.

I_SD 35A, di/dt  862A/µs, V_DD V_(BR)DSS, T_J175°C.

Pulse width  400µs; duty cycle  2%.







C_osseff. (TR) is a fixed capacitance that gives the same charging time as C_osswhile V_DSis rising from 0 to 80% V_DSS.

C_osseff. (ER) is a fixed capacitance that gives the same energy as C_osswhile V_DSis rising from 0 to 80% V_DSS

R_is measured at T_Japproximately 90°C.

When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to

application note #AN-994.please refer to application note to AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf



Limited by T_Jmax, starting T_J= 25°C, L = 1mH, R_G= 50, I_AS= 16A, V_GS=10V.

2016-01-05

IRF60R217

Dynamic Electrical Characteristics @ T_J= 25°C (unless otherwise specified)

Symbol

gfs

Parameter

Forward Transconductance

Total Gate Charge

Min.

120

–––

Typ. Max. Units

Conditions

–––

V_DS= 10V, I_D= 35A

Q_g

I_D= 35A

Q_gs

Gate-to-Source Charge

Gate-to-Drain Charge

Total Gate Charge Sync. (Qg– Qgd)

Turn-On Delay Time

–––

V_DS= 30V

V_GS= 10V

Q_gd

Q_sync

t_d(on)

t_r

7.6

V_DD=30V

I_D= 35A

Rise Time

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

–––

R_G= 2.7

_GS= 10V 

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

2170

210

130

V_GS= 0V

V_DS= 25V

ƒ = 1.0MHz, See Fig. 7

Effective Output Capacitance

(Energy Related)

C_{oss eff.(ER)}

C_{oss eff.(TR)}

–––

228

283

–––

V_GS= 0V, VDS = 0V to 48V

V_GS= 0V, VDS = 0V to 48V

Output Capacitance (Time Related)

Diode Characteristics

Symbol

Parameter

Min.

Typ. Max. Units

Conditions

MOSFET symbol

Continuous Source Current

(Body Diode)

I_S

–––

showing the

Pulsed Source Current

(Body Diode)

integral reverse

p-n junction diode.

I_SM

–––

217

1.2

V_SD

Diode Forward Voltage

T_J= 25°C,I_S= 35A,V_GS= 0V 

dv/dt

Peak Diode Recovery dv/dt 

–––

1.7

––– V/ns T_J= 175°C,I_S= 35A,V_DS= 60V

–––

T_J= 25°C

V_DD= 51V

I_F= 35A,

t_rr

Reverse Recovery Time

T_J= 125°C

T_J= 25°C di/dt = 100A/µs 

Q_rr

Reverse Recovery Charge

Reverse Recovery Current

T_J= 125°C

T_J= 25°C



I_RRM

2016-01-05

IRF60R217

1000

100

1000

100

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

TOP

BOTTOM

4.5V

60µs

Tj = 175°C

PULSE WIDTH



PULSE WI DTH

Tj = 25°C



0.1

100

0.1

100

, Drain-to-Source Voltage (V)

Fig 4. Typical Output Characteristics

Fig 3. Typical Output Characteristics

2.5

2.0

1.5

1.0

0.5

1000

100

= 35A

= 10V

= 175°C

= 25°C

= 25V

 60µs PULSE WIDTH

0.1

-60 -40 -20 0 20 40 60 80 100120140160180

, Junction Temperature (°C)

, Gate-to-Source Voltage (V)

Fig 6. Normalized On-Resistance vs. Temperature

Fig 5. Typical Transfer Characteristics

10000

= 0V,

= C

f = 1 MHZ

I = 35A

+ C , C

SHORTED

iss

= C

rss

oss

= 48V

= 30V

= C + C

iss

VDS= 12V

1000

oss

rss

100

0.1

100

Q , Total Gate Charge (nC)

, Drain-to-Source Voltage (V)

Fig 7. Typical Capacitance vs. Drain-to-Source Voltage

Fig 8. Typical Gate Charge vs. Drain-to-Source Voltage

2016-01-05

IRF60R217

1000

100

1000

100

OPERATION IN THIS AREA

LIMITED BY RDS(on)

= 175°C

100µsec

= 25°C

1msec

10msec

0.1

0.01

Tc = 25°C

Tj = 175°C

Single Pulse

= 0V

0.1

100

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

, Drain-toSource Voltage (V)

, Source-to-Drain Voltage (V)

Fig 9. Typical Source-Drain Diode Forward Voltage

Fig 10. Maximum Safe Operating Area

0.4

Id = 1.0mA

0.3

0.2

0.1

0.0

-60 -40 -20

20 40 60 80 100120140160180

, Temperature ( °C )

Drain-to-Source Voltage (V)

DS,

Fig 11. Drain-to-Source Breakdown Voltage

Fig 12. Typical C_ossStored Energy

VGS = 6.0V

VGS = 7.0V

VGS = 8.0V

VGS = 10V

20 40 60 80 100 120 140 160

, Drain Current (A)

Fig 13. Typical On-Resistance vs. Drain Current

2016-01-05

IRF60R217

D = 0.50

0.20

0.10

0.05

0.1

0.02

0.01

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming Tj = 150°C and

Tstart = 25°C (Single Pulse)

Allowed avalanche Current vs avalanche



pulsewidth, tav, assuming j = 25°C and

Tstart = 150°C.

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 15. Avalanche Current vs. Pulse Width

100

Notes on Repetitive Avalanche Curves, Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1.Avalanche failures assumption:

TOP

BOTTOM 1.0% Duty Cycle

= 35A

Single Pulse

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of T_jmax. This is validated for every

part type.

2. Safe operation in Avalanche is allowed as long asT_jmaxis not

exceeded.

3. Equation below based on circuit and waveforms shown in Figures

23a, 23b.

4. P_{D (ave)}= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage

increase during avalanche).

6. I_av= Allowable avalanche current.

7. T = Allowable rise in junction temperature, not to exceed T_jmax

(assumed as 25°C in Figures 14, 15).

t_av= Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

Z_thJC(D, t_av) = Transient thermal resistance, see Figure 14)

100

125

150

175

Starting T , Junction Temperature (°C)

PD (ave) = 1/2 ( 1.3·BV·I_av) = T/ Z_thJC

I_av= 2T/ [1.3·BV·Z_th]

E_{AS (AR)}= P_{D (ave)· av}

Fig 16. Maximum Avalanche Energy vs. Temperature

2016-01-05

IRF60R217

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

= 23A

= 51V

T = 25°C

T = 125°C

ID = 50µA

ID = 250µA

ID = 1.0mA

ID = 1.0A

-75

-25

125

175

200

400

600

800

1000

, Temperature ( °C )

di /dt (A/µs)

Fig 17. Threshold Voltage vs. Temperature

Fig 18. Typical Recovery Current vs. dif/dt

200

I = 23A

I = 35A

180

160

140

120

100

= 51V

T = 25°C

T = 125°C

T = 25°C

T = 125°C

200

400

600

800

1000

200

400

600

800

1000

di /dt (A/µs)

Fig 19. Typical Recovery Current vs. dif/dt

Fig 20. Typical Stored Charge vs. dif/dt

200

I = 35A

180

= 51V

160

140

120

100

T = 25°C

T = 125°C

200

400

600

800

1000

di /dt (A/µs)

Fig 21. Typical Stored Charge vs. dif/dt

2016-01-05

IRF60R217

Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET^®Power MOSFETs

(BR)DSS

15V

DRIVER

D.U.T

20V

0.01



Fig 23a. Unclamped Inductive Test Circuit

Fig 23b. Unclamped Inductive Waveforms

Fig 24a. Switching Time Test Circuit

Fig 24b. Switching Time Waveforms

Vds

Vgs

VDD

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 25b. Gate Charge Waveform

Fig 25a. Gate Charge Test Circuit

2016-01-05

IRF60R217

D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER

WITH ASSEMBLY

LOT CODE 1234

INTERNATIONAL

RECTIFIER

LOGO

DATE CODE

YEAR 1 = 2001

WEEK 16

IRFR120

116A

ASSEMBLED ON WW 16, 2001

IN THE ASSEMBLY LINE "A"

LINE A

Note: "P" in assembly line position

ASSEMBLY

LOT CODE

indicates "Lead-Free"

"P" in assembly line position indicates

"Lead-Free" qualification to the consumer-level

PART NUMBER

DATE CODE

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

INTERNATIONAL

RECTIFIER

IRFR120

12 34

LOGO

P = DESIGNATES LEAD-FREE

PRODUCT QUALIFIED TO THE

CONSUMER LEVEL (OPTIONAL)

ASSEMBLY

LOT CODE

YEAR 1 = 2001

WEEK 16

A = ASSEMBLY SITE CODE

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

2016-01-05

IRF60R217

D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches)

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

2016-01-05

IRF60R217

Qualification Information^†

Qualification Level

Industrial

(per JEDEC JESD47F) ^††

D-Pak

MSL1

Yes

Moisture Sensitivity Level

RoHS Compliant

†

Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/

†† Applicable version of JEDEC standard at the time of product release.

Published by

Infineon Technologies AG

81726 München, Germany

IMPORTANT NOTICE

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics

(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any

information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and

liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third

party.

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this

document and any applicable legal requirements, norms and standards concerning customer’s products and any use of

the product of Infineon Technologies in customer’s applications.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of

customer’s technical departments to evaluate the suitability of the product for the intended application and the

completeness of the product information given in this document with respect to such application.

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies office (www.infineon.com).

WARNINGS

Due to technical requirements products may contain dangerous substances. For information on the types in question

please contact your nearest Infineon Technologies office.

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized

representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a

failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.

2016-01-05

IRF60R217 [INFINEON]

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