IRF7101_技术文档

PD - 94594D

IRF7832

HEXFET^®Power MOSFET

Applications

l Synchronous MOSFET for Notebook

Processor Power

l Synchronous Rectifier MOSFET for

Isolated DC-DC Converters in

Networking Systems

V_DSS

R_DS(on)max

Qg

4.0m @V_GS= 10V

30V

34nC

A

D

1

2

3

4

8

S

G

Benefits

7

D

l Very Low R_DS(on)at 4.5V V_GS

l Ultra-Low Gate Impedance

l Fully Characterized Avalanche Voltage

and Current

6

D

5

D

SO-8

Top View

l 20V V_GSMax. Gate Rating

Absolute Maximum Ratings

Parameter

Max.

30

Units

V

V_DS

Drain-to-Source Voltage

V

Gate-to-Source Voltage

± 20

20

GS

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

I

@ T_A= 25°C

D

@ T_A= 70°C

16

A

160

2.5

DM

P

@T_A= 25°C

@T_A= 70°C

Power Dissipation

W

D

1.6

Linear Derating Factor

Operating Junction and

0.02

-55 to + 155

W/°C

°C

T

J

T

Storage Temperature Range

STG

Thermal Resistance

Parameter

Junction-to-Drain Lead

Junction-to-Ambient

Typ.

–––

Max.

20

Units

°C/W

R_θJL

R_θJA

–––

50

Notes through are on page 10

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1

1/14/04

IRF7832

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Drain-to-Source Breakdown Voltage

Min. Typ. Max. Units

30 ––– –––

Conditions

V_GS= 0V, I_D= 250µA

BV_DSS

∆Β

V

∆

V_DSS/ T_J

Breakdown Voltage Temp. Coefficient ––– 0.023 ––– V/°C Reference to 25°C, I_D= 1mA

R_DS(on)

Static Drain-to-Source On-Resistance

–––

3.1

3.7

4.0

4.8

V_GS= 10V, I_D= 20A

Ω

m

V_GS= 4.5V, I_D= 16A

_DS= V_GS, I_D= 250µA

V_GS(th)

Gate Threshold Voltage

1.39 –––

2.32

V

∆

V_GS(th)

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

–––

77

5.7

–––

34

––– mV/°C

I_DSS

1.0

150

100

-100

–––

51

µA V_DS= 24V, V_GS= 0V

V

_DS= 24V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

nA

S

_GS= 20V

_GS= -20V

gfs

Q_g

_DS= 15V, I_D= 16A

–––

Q_gs1

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

8.6

2.9

12

–––

V_DS= 15V

Q_gs2

Q_gd

nC V_GS= 4.5V

I_D= 16A

Q_godr

Gate Charge Overdrive

10.5

14.9

23

See Fig. 16

Q_sw

Switch Charge (Q_gs2+ Q_gd)

Q_oss

t_d(on)

t_r

Output Charge

nC

V_DS= 16V, V_GS= 0V

Turn-On Delay Time

Rise Time

12

V_DD= 15V, V_GS= 4.5V

I_D= 16A

6.7

21

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

ns Clamped Inductive Load

13

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 4310 –––

V_GS= 0V

–––

990

450

–––

pF

V_DS= 15V

ƒ = 1.0MHz

Avalanche Characteristics

Parameter

Single Pulse Avalanche Energy

Typ.

–––

Max.

Units

mJ

E_AS

I_AR

260

16

Avalanche Current

A

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

D

I_S

Continuous Source Current

–––

3.1

MOSFET symbol

(Body Diode)

A

showing the

G

I_SM

Pulsed Source Current

–––

160

integral reverse

S

(Body Diode)

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

–––

41

1.0

62

59

V

T = 25°C, I = 16A, V = 0V

J S GS

Reverse Recovery Time

Reverse Recovery Charge

Forward Turn-On Time

ns T = 25°C, I = 16A, V_DD= 10V

J F

Q_rr

t_on

di/dt = 100A/µs

39

nC

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

2

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IRF7832

1000

100

10

1000

100

10

VGS

10V

VGS

10V

TOP

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

2.25V

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

2.25V

BOTTOM

1

2.25V

0.1

0.01

20µs PULSE WIDTH

Tj = 150°C

20µs PULSE WIDTH

Tj = 25°C

1

0.1

1

10

100

1000

0.1

1

10

100

1000

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

1000

2.0

1.5

1.0

0.5

0.0

I

= 16A

D

V

= 4.5V

GS

100

10

1

T = 150°C

J

T

= 25°C

J

V

= 15V

DS

20µs PULSE WIDTH

0

-60 -40 -20

T

0

20 40 60 80 100 120 140 160

2.0

2.5

3.0 3.5

4.0

Junction Temperature (°C )

V

, Gate-to-Source Voltage (V)

J,

GS

Fig 4. Normalized On-Resistance

Fig 3. Typical Transfer Characteristics

Vs. Temperature

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3

IRF7832

6

5

4

3

2

1

0

100000

V

= 0V,

f = 1 MHZ

I = 16A

GS

D

C

= C + C , C SHORTED

iss

gs gd ds

V

= 24V

= 15V

DS

C

= C

gd

rss

C

= C + C

oss

ds

gd

10000

1000

C

iss

C

oss

rss

100

1

10

100

0

10

20

30

40

50

V

, Drain-to-Source Voltage (V)

Q

Total Gate Charge (nC)

DS

G

Fig 6. Typical Gate Charge Vs.

Fig 5. Typical Capacitance Vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000

100

10

1000

100

10

1

T

= 150°C

J

100µsec

T

= 25°C

J

1msec

Tc = 25°C

Tj = 150°C

Single Pulse

10msec

V

GS

= 0V

1

0.1

1

10

, Drain-to-Source Voltage (V)

100

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

, Source-to-Drain Voltage (V)

V

DS

SD

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

4

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IRF7832

2.5

2.0

1.5

1.0

0.5

24

20

16

12

8

I

= 250µA

D

4

0

-60 -40 -20

0

20 40 60 80 100 120 140 160

, Temperature (°C)

25

50

T

75

100

125

150

T

J

, Case Temperature (°C)

C

Fig 9. Maximum Drain Current Vs.

Fig 10. Threshold Voltage Vs. Temperature

Case Temperature

100

10

D = 0.50

0.20

0.10

0.05

1

0.02

0.01

0.1

0.01

SINGLE PULSE

( THERMAL RESPONSE )

1E-006

1E-005

0.0001

0.001

0.01

0.1

1

10

100

t

, Rectangular Pulse Duration (sec)

1

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

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5

IRF7832

10

600

500

400

300

200

100

0

I

= 20A

D

I

D

TOP

7.0A

13A

8

BOTTOM 16A

6

T = 125°C

J

4

T = 25°C

J

2

0

2

3

4

5

6

7

8

9

10

25

50

75

100

125

150

Starting T , Junction Temperature (°C)

J

V

, Gate -to -Source Voltage (V)

GS

Fig 13. Maximum Avalanche Energy

Fig 12. On-Resistance vs. Gate Voltage

vs. Drain Current

Current Regulator

Same Type as D.U.T.

V

(BR)DSS

t

15V

p

50KΩ

.2µF

12V

.3µF

DRIVER

+

L

V

DS

+

V

DS

D.U.T.

-

D.U.T

AS

R

G

V

DD

-

I

A

V

GS

20V

VGS

Ω

0.01

t

p

I

AS

3mA

I

D

G

Fig 14. Unclamped Inductive Test Circuit

Current Sampling Resistors

andWaveform

Fig 15. Gate Charge Test Circuit

L_D

V_DS

90%

+

-

V_DD

D.U.T

10%

V_GS

Pulse Width < 1µs

Duty Factor < 0.1%

t_d(on)

t_d(off)

t_r

t_f

Fig 17. Switching Time Waveforms

Fig 16. Switching Time Test Circuit

6

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IRF7832

Driver Gate Drive

P.W.

D =

D.U.T

Period

+

-

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

-

+

di/dt

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

I

SD

Ripple

≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 19. Gate Charge Waveform

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7

IRF7832

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

loss

conduction

drive

output

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

g

⎛

⎜

Q_oss

⎞

⎠

P_loss= P_conduction+ P_switching+ P_drive+ P_output

+

×V × f + Q × V × f

(

)

in

rr

in

⎝ 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

P

= I ²× R_{ds(on )}

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

⎛

Q_gd

i_g

⎞

Q_gs2

i_g

⎞

⎟

⎜

⎟

⎜

+ I ×

× V × f + I ×

× V × f

in

⎝

⎠

⎝

⎠

+ Q × V × f

(

)

g

⎛ Q_oss

⎞

⎠

+

×V × f

in

⎝

2

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFET data sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

8

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IRF7832

SO-8 Package Details

SO-8 Part Marking

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9

IRF7832

SO-8 Tape and Reel

TERMINAL NUMBER 1

12.3 ( .484 )

11.7 ( .461 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES:

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

330.00

(12.992)

MAX.

14.40 ( .566 )

12.40 ( .488 )

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

Notes:

Repetitive rating; pulse width limited by max. junction temperature.

Starting T_J= 25°C, L = 2.0mH, R_G= 25Ω, I_AS= 16A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

When mounted on 1 inch square copper board.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.01/04

10

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型号：	IRF7101
厂家：	Infineon
描述：	HEXFET Power MOSFET HEXFET功率MOSFET 晶体晶体管开关光电二极管
文件：	总10页 (文件大小：211K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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