IRF840ALPBF [INFINEON]
SMPS MOSFET HEXFET㈢ Power MOSFET; 开关电源MOSFET HEXFET㈢功率MOSFET
| 型号： | IRF840ALPBF |
| 厂家： | 
Infineon |
| 描述： | SMPS MOSFET HEXFET㈢ Power MOSFET |
| 文件： | 总10页 (文件大小：667K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-95143
IRF840ASPbF
IRF840ALPbF
SMPS MOSFET
HEXFET® Power MOSFET
Applications
VDSS
500V
RDS(on) max
ID
8.0A
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High Speed Power Switching
l Lead-Free
0.85Ω
Benefits
l Low Gate Charge Qg Results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN 1001)
D2Pak
IRF840AS
TO-262
IRF840AL
Absolute Maximum Ratings
Parameter
Max.
8.0
5.1
Units
A
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
32
PD @TC = 25°C
PD @TA = 25°C
125
3.1
W
Power Dissipation
Linear Derating Factor
1.0
W/°C
V
VGS
dv/dt
TJ
Gate-to-Source Voltage
± 30
5.0
Peak Diode Recovery dv/dt
Operating Junction and
V/ns
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Typical SMPS Topologies
l Two Transistor Forward
l Haft Bridge
l Full Bridge
Notes through are on page 10
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1
04/21/04
IRF840AS/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
500 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.58 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– ––– 0.85
2.0 ––– 4.0
Ω
VGS = 10V, ID = 4.8A
VDS = VGS, ID = 250µA
VDS = 500V, VGS = 0V
VDS = 400V, VGS = 0V, TJ = 125°C
VGS = 30V
V
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
µA
IDSS
IGSS
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
3.7 ––– –––
Conditions
VDS = 50V, ID = 4.8A
ID = 8.0A
gfs
S
Qg
––– ––– 38
––– ––– 9.0
––– ––– 18
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 400V
VGS = 10V, See Fig. 6 and 13
–––
–––
–––
–––
11 –––
23 –––
26 –––
19 –––
VDD = 250V
ID = 8.0A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 9.1Ω
RD = 31Ω,See Fig. 10
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 1018 –––
––– 155 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
VDS = 25V
–––
8.0 –––
pF
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 480V ꢀ
––– 1490 –––
–––
–––
42 –––
56 –––
Avalanche Characteristics
Parameter
Typ.
Max.
510
8.0
Units
mJ
A
EAS
IAR
Single Pulse Avalanche Energy
–––
–––
–––
Avalanche Current
EAR
Repetitive Avalanche Energy
13
mJ
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
1.0
Units
°C/W
RθJC
RθJA
Junction-to-Ambient ( PCB Mounted, steady-state)*
–––
40
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
S
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
8.0
32
––– –––
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 2.0
––– 422 633
––– 2.0 3.0
V
TJ = 25°C, IS = 8.0A, VGS = 0V
ns
TJ = 25°C, IF = 8.0A
Qrr
ton
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF840AS/LPbF
100
10
1
100
10
1
VGS
15V
VGS
15V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
°
°
T = 25 C
J
T = 150 C
J
0.1
0.1
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
10
1
8.0
A
=
I
D
°
T = 150 C
J
°
T = 25 C
J
V
= 50V
DS
20µs PULSE WIDTH
V
=10V
GS
0.1
4.0
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
5.0
6.0
7.0 8.0
9.0
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF840AS/LPbF
20
16
12
8
100000
8.0
= A
I
D
V
= 0V,
f = 1 MHZ
GS
V
V
V
= 400V
= 250V
= 100V
DS
DS
DS
C
iss
= C + C
gs gd
,
C
ds
SHORTED
C
rss
= C
gd
10000
1000
100
10
C
oss
= C + C
ds
gd
Ciss
Coss
4
Crss
FOR TEST CIRCUIT
SEE FIGURE 13
1
0
0
10
20
30
40
1
10
100
1000
Q
, Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100
10
1
100
10
1
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10us
°
T = 150 C
J
100us
1ms
°
T = 25 C
J
10ms
°
T = 25 C
C
°
T = 150 C
Single Pulse
J
V
= 0 V
GS
0.1
0.1
0.2
10
100
1000
10000
0.5
0.8
1.1
1.4
V
, Drain-to-Source Voltage (V)
V
,Source-to-Drain Voltage (V)
DS
SD
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
4
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IRF840AS/LPbF
RD
8.0
6.0
4.0
2.0
0.0
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
T
75
100
125
°
150
, Case Temperature ( C)
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
1
D = 0.50
0.20
P
2
DM
0.10
0.05
0.1
0.01
t
1
t
2
0.02
0.01
Notes:
SINGLE PULSE
1. Duty factor D =
t / t
1
(THERMAL RESPONSE)
2. Peak T =P
x Z
+ T
C
J
DM
thJC
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
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5
IRF840AS/LPbF
1200
1000
800
600
400
200
0
1 5V
I
D
TOP
3.6A
5.1A
BOTTOM 8.0A
DRIVER
L
V
G
DS
D.U.T
AS
R
+
V
D D
-
I
A
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
°
Starting T , Junction Temperature ( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
610
600
590
580
570
560
550
540
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
0.0
1.0
2.0
3.0
4.0
5.0
6.0
3mA
I
, Avalanche Current ( A)
AV
I
I
D
G
Current Sampling Resistors
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Fig 13b. Gate Charge Test Circuit
6
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IRF840AS/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
-
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRF840AS/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T HIS IS AN IR F 530S WIT H
PART NU MB E R
LOT CODE 8024
INT E R NAT IONAL
R E CT IF IE R
LOGO
AS S E MB LE D ON WW 02, 2000
IN T H E AS S E MB L Y LINE "L "
F 530S
DAT E CODE
YE AR 0 = 2000
WE E K 02
Note: "P" in as s embly line
pos ition indicates "Lead-F ree"
AS S E MB LY
LOT CODE
LINE
L
OR
PART NUMB E R
INT E RNAT IONAL
RE CT IF IE R
LOGO
F 530S
DAT E CODE
P = DE S IGNAT E S LE AD-F RE E
PRODUCT (OPT IONAL)
YE AR 0 = 2000
AS S E MB LY
LOT CODE
WE E K 02
A = AS S E MB LY S IT E CODE
8
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IRF840AS/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T H IS IS AN IRL3103L
LOT CODE 1789
PAR T NU MBER
INT ER NAT IONAL
R ECT IF IER
LOGO
AS S EMB LE D ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
DAT E CODE
YE AR 7 = 1997
WE EK 19
Note: "P" in as s embly line
pos ition indicates "L ead-F ree"
AS S EMBLY
LOT CODE
LINE C
OR
PAR T NU MBER
DAT E CODE
INT ER NAT IONAL
R ECT IF IER
LOGO
P = DES IGNAT ES LEAD-F REE
PR ODU CT (OPT IONAL)
YE AR 7 = 1997
AS S EMBLY
LOT CODE
WE EK 19
A = AS S EMBLY S IT E CODE
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9
IRF840AS/LPbF
D2Pak Tape & Reel Infor-
TR R
1.60 (.063)
1.50 (.059)
1 .60 (.06 3)
1 .50 (.05 9)
4.10 (.161)
3.90 (.153)
0.3 68 (.014 5)
0.3 42 (.013 5)
F E ED D IR E C TIO N
1 1.60 (.457 )
1 1.40 (.449 )
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.4 2 (.609)
15.2 2 (.601)
TR L
1.7 5 (.069 )
1.2 5 (.049 )
10.90 (.429 )
10.70 (.421 )
4.7 2 (.136)
4.5 2 (.178)
16.10 (.63 4)
15.90 (.62 6)
FE E D D IRE CT IO N
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
M AX.
N OT ES
1. C O M F OR M S TO EIA-418.
2. C O NTR O LLING DIM ENS IO N: M ILLIM ETER.
3. D IM ENS IO N M EASUR ED
:
26.40 (1.039)
24.40 (.961)
4
@ HU B.
3
4. INC LUD ES F LAN G E DIS TO RTIO N
@
O UTE R EDG E.
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11)
ꢀCoss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Starting TJ = 25°C, L = 16mH
RG = 25Ω, IAS = 8.0A. (See Figure 12)
Uses IRF840A data and test conditions
ISD ≤ 8.0A, di/dt ≤ 100A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C
,
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/04
10
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