IRFBA1404 [INFINEON]
Power MOSFET(Vdss=40V, Rds(on)=3.7mohm, Id=206A); 功率MOSFET （ VDSS = 40V ，导通电阻Rds （ ON）= 3.7mohm ，ID = 206A ）
| 型号： | IRFBA1404 |
| 厂家： | 
Infineon |
| 描述： | Power MOSFET(Vdss=40V, Rds(on)=3.7mohm, Id=206A) |
| 文件： | 总9页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 93806
AUTOMOTIVE MOSFET
IRFBA1404P
HEXFET® Power MOSFET
Typical Applications
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Anti-lock Braking Systems (ABS)
Electric Power Steering (EPS)
Electric Braking
D
VDSS = 40V
Radiator Fan Control
Benefits
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Advanced Process Technology
RDS(on) = 3.7mΩ
Ultra Low On-Resistance
G
Increase Current Handling Capability
175°C Operating Temperature
Fast Switching
ID = 206A
S
Dynamic dv/dt Rating
Repetitive Avalanche Allowed up to Tjmax
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the latest processing
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this MOSFET are a 175oC junction operating
temperature, fast switching speed and improved ruggedness in
single and repetitive avalanche. The Super-220 TM is a package that
has been designed to have the same mechanical outline and pinout
as the industry standard TO-220 but can house a considerably
larger silicon die. The result is significantly increased current
handling capability over both the TO-220 and the much larger TO-
247 package. The combination of extremely low on-resistance
silicon and the Super-220 TM package makes it ideal to reduce the
component count in multiparalled TO-220 applications, reduce
system power dissipation, upgrade existing designs or have TO-247
performance in a TO-220 outline. This package has been designed
to meet automotive, Q101, qualification standard.
Super-220™
These benefits make this design an extremely efficient and reliable
device for use in Automotive applications and a wide variety of other
applications.
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
206
145
A
650
PD @TC = 25°C
Power Dissipation
300
W
W/°C
V
Linear Derating Factor
2.0
± 20
VGS
EAS
IAR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
See Fig.12a, 12b, 15, 16
mJ
A
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
30
5.0
mJ
V/ns
-40 to + 175
-55 to + 175
300 (1.6mm from case )
20
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Recommended clip force
°C
N
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1
10/24/00
IRFBA1404P
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
40 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.036 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance ––– ––– 3.7
mΩ VGS = 10V, ID = 95A
Gate Threshold Voltage
2.0
––– 4.0
V
S
VDS = 10V, ID = 250µA
VDS = 25V, ID = 60A
VDS = 40V, VGS = 0V
VDS = 32V, VGS = 0V, TJ = 150°C
VGS = 20V
Forward Transconductance
106 ––– –––
––– ––– 20
––– ––– 250
––– ––– 200
––– ––– -200
––– 160 200
IDSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
IGSS
VGS = -20V
Qg
ID = 95A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
35 –––
42 60
17 –––
nC
ns
VDS = 32V
VGS = 10V
VDD = 20V
––– 140 –––
ID = 95A
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
72 –––
26 –––
RG = 2.5Ω
RD = 0.21Ω
Between lead,
6mm (0.25in.)
D
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
–––
2.0 –––
nH
pF
G
from package
–––
5.0
and center of die contact
VGS = 0V
S
Ciss
Input Capacitance
––– 7360 –––
––– 1680 –––
––– 240 –––
––– 6630 –––
––– 1490 –––
––– 1540 –––
Coss
Output Capacitance
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
Coss
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 32V
Coss
Output Capacitance
Coss eff.
Effective Output Capacitance ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
D
IS
MOSFET symbol
––– –––
206
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 650
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
––– ––– 1.3
––– 71 110
––– 180 270
V
TJ = 25°C, IS = 95A, VGS = 0V
ns
TJ = 25°C, IF = 95A
Qrr
ton
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
0.5
Max.
0.50
–––
58
Units
RθJC
RθCS
RθJA
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
°C/W
–––
2
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IRFBA1404P
1000
100
10
1000
100
10
VGS
15V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
20µs PULSE WIDTH
°
T = 175 C
J
20µs PULSE WIDTH
T = 25 C
J
°
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.5
159A
=
I
D
°
T = 25 C
J
°
2.0
1.5
1.0
0.5
0.0
T = 175 C
J
100
V
= 25V
DS
V
= 10V
GS
20µs PULSE WIDTH
10
4.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
5.0
6.0
7.0 8.0 9.0
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRFBA1404P
20
16
12
8
12000
I
D
= 95A
V
= 0V,
f = 1MHz
C
GS
C
= C + C
SHORTED
ds
iss
gs
gd ,
gd
C
= C
gd
V
V
= 32V
= 20V
rss
DS
DS
10000
8000
6000
4000
2000
0
C
= C + C
oss
ds
C
iss
C
oss
4
FOR TEST CIRCUIT
SEE FIGURE 13
C
rss
0
1
10
100
0
40
80
120
160
200
240
V
, Drain-to-Source Voltage (V)
Q
, Total Gate Charge (nC)
DS
G
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
10000
1000
100
10
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
°
T = 175 C
J
10us
100
10
1
100us
°
T = 25 C
J
1ms
10ms
°
T = 25 C
C
J
°
T = 175 C
V
= 0 V
Single Pulse
GS
2.0
1
1
10
100
0.4
0.8
1.2
1.6
2.4
V
, Drain-to-Source Voltage (V)
V
,Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFBA1404P
RD
240
180
120
60
VDS
LIMITED BY PACKAGE
VGS
10V
D.U.T.
RG
+VDD
-
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
0
25
50
75
100
125
150
175
°
, Case Temperature ( C)
T
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
SINGLE PULSE
(THERMAL RESPONSE)
0.02
0.01
P
DM
0.01
t
1
t
2
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T = P
x Z
+ T
thJC C
J
DM
0.001
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFBA1404P
1000
800
600
400
200
0
15V
I
D
TOP
39A
67A
95A
BOTTOM
DRIVER
L
V
G
D S
D.U .T
R
+
V
D D
-
I
A
AS
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T , Junction Temperature ( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
50
48
46
44
42
40
Q
Q
GD
GS
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
0
20
I
40
60
80
100
V
GS
, Avalanche Current ( A)
3mA
AV
I
I
D
G
Current Sampling Resistors
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
Fig 13b. Gate Charge Test Circuit
6
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IRFBA1404P
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
Tj = 25°C due to
∆
avalanche losses
0.05
0.10
1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
500
400
300
200
100
0
TOP
BOTTOM 10% Duty Cycle
= 95A
Single Pulse
I
D
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = ∆T/ ZthJC
Fig 16. Maximum Avalanche Energy
Iav = 2∆T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRFBA1404P
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
Period
Period
D =
P.W.
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. For N-Channel HEXFET Power MOSFETs
8
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IRFBA1404P
Super-220™ Package Outline
9.00 [.354]
8.00 [.315]
11.00 [.433]
B
A
5.00 [.196]
4.00 [.158]
10.00 [.394]
0.25 [.010]
B A
1.50 [.059]
0.50 [.020]
13.50 [.531]
12.50 [.493]
4
15.00 [.590]
14.00 [.552]
1
2
3
4.00 [.157]
3.50 [.138]
14.50 [.570]
13.00 [.512]
1.00 [.039]
0.70 [.028]
4X
1.30 [.051]
0.90 [.036]
3X
3.00 [.118]
2.50 [.099]
2.55 [.100]
2X
0.25 [.010]
B
A
LEAD ASSIGNMENTS
NOTES :
MOS F E T
IGBT
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONT R OL L ING DIME NS ION: MIL L IME T E R .
1 - GATE
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
2 - COL L E CT OR
3 - EMITTER
4 - COL L E CT OR
3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES ].
4. OU T L INE CONF OR MS T O JE DE C OU T L INE T O-273AA.
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 400µs; duty cycle ≤ 2%.
max. junction temperature.
ꢀCoss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25°C, L = 0.12mH
RG = 25Ω, IAS = 95A.
as Coss while VDS is rising from 0 to 80% VDSS . Refer to AN-1001
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 95A.
ISD ≤ 95A, di/dt ≤ 150A/µs, VDD ≤ V(BR)DSS
TJ ≤ 175°C
,
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Data and specifications subject to change without notice. 10/00
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9
相关型号：
IRFBA31N50LPBF
Power Field-Effect Transistor, 31A I(D), 500V, 0.152ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SUPER-220, 4 PIN
INFINEON
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