IRFIB8N50KPBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRFIB8N50KPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总8页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95751
SMPS MOSFEITRFIB8N50KPbF
HEXFET® Power MOSFET
Applications
VDSS
RDS(on) typ.
ID
l Switch Mode Power Supply (SMPS)
l UninterruptIble Power Supply
l High Speed Power Switching
l Lead-Free
500V
290mΩ
6.7A
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
TO-220
FULL-PAK
Absolute Maximum Ratings
Parameter
Max.
6.7
4.2
27
Units
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
@ T = 25°C
C
D
D
@ T = 100°C
C
A
DM
P
@T = 25°C
C
Power Dissipation
45
W
D
Linear Derating Factor
Gate-to-Source Voltage
0.36
±30
W/°C
V
V
GS
Peak Diode Recovery dv/dt
Operating Junction and
dv/dt
17
V/ns
T
J
-55 to + 150
T
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting torqe, 6-32 or M3 screw
300 (1.6mm from case )
1.1(10)
N•m (lbf•in)
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
290
6.7
Units
mJ
A
EAS
IAR
Avalanche Current
Repetitive Avalanche Energy
EAR
4.5
mJ
Thermal Resistance
Parameter
Typ.
–––
Max.
2.76
65
Units
Rθ
Rθ
Junction-to-Case
Junction-to-Ambient
°C/W
JC
JA
–––
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1
8/23/04
IRFIB8N50KPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
500
–––
–––
V
V
/ T
∆
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 4.0A
VDS = VGS, ID = 250µA
VDS = 500V, VGS = 0V
VDS = 400V, VGS = 0V, TJ = 125°C
VGS = 30V
∆
Breakdown Voltage Temp. Coefficient –––
0.59 ––– V/°C
(BR)DSS
J
m
Ω
RDS(on)
VGS(th)
IDSS
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
3.0
290
–––
–––
–––
–––
350
5.0
50
V
Drain-to-Source Leakage Current
–––
–––
–––
–––
µA
250
100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
VGS = -30V
––– -100
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 4.0A
gfs
4.7
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
17
–––
V
Qg
ID = 6.7A
89
Qgs
Qgd
td(on)
tr
VDS = 400V
VGS = 10V
VDD = 250V
ID = 6.7A
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
24
nC
44
–––
–––
–––
–––
16
td(off)
tf
RG = 38
Ω
Turn-Off Delay Time
Fall Time
28
ns
VGS = 10V
VGS = 0V
8.4
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 2160 –––
V
DS = 25V
pF ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
240
27
–––
–––
––– 2600 –––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 400V
–––
–––
62
–––
–––
120
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
I
Continuous Source Current
–––
–––
6.7
MOSFET symbol
S
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
I
–––
–––
27
SM
S
(Body Diode)
p-n junction diode.
V
t
T = 25°C, I = 6.7A, V = 0V
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
–––
–––
–––
430
2.0
V
SD
J
S
GS
T = 25°C, I = 6.7A
640
ns
nC
rr
J
F
di/dt = 100A/µs
Q
t
––– 2840 4270
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
Notes:
Pulse width ≤ 300µs; duty cycle ≤ 2%.
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11).
Starting TJ = 25°C, L = 13mH, RG = 25Ω,
IAS = 6.7A, dv/dt = 17V/ns (See Figure 12a).
as Coss while VDS is rising from 0 to 80% VDSS
.
ISD ≤ 6.7A, di/dt ≤ 330A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C.
,
2
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IRFIB8N50KPbF
100
10
1000
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
5.0V
BOTTOM
5.0V
1
1
0.1
0.1
0.01
5.0V
0.01
0.001
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
100.00
6.7A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
T
= 150°C
J
10.00
1.00
0.10
0.01
T
= 25°C
J
V
= 50V
DS
20µs PULSE WIDTH
V
=10V
GS
4.0
5.0
6.0
7.0
8.0
9.0
10.0
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
T , Junction Temperature ( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRFIB8N50KPbF
100000
12
10
8
V
= 0V,
f = 1 MHZ
GS
I
= 6.7A
D
C
= C + C , C SHORTED
iss
gs
= C
gd
ds
400V
250V
100V
C
rss
gd
10000
1000
100
10
C
= C + C
oss
ds gd
C
C
iss
6
oss
4
C
rss
2
0
1
0
10
Q
20
30
40
50
60
70
1
10
100
1000
, Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100
10
1
100.00
10.00
1.00
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 150°C
J
100µsec
1msec
T
= 25°C
J
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
1000
V
= 0V
GS
0.1
0.10
1
10
100
10000
0.0
0.5
1.0
1.5
V
, Drain-to-Source Voltage (V)
V
, Source-toDrain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFIB8N50KPbF
RD
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
°
T , Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
1
0.20
0.10
0.05
P
2
DM
0.1
t
0.02
1
0.01
t
2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
t / t
1
2. Peak T =P
J
x Z
+ T
C
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFIB8N50KPbF
700
I
D
600
500
400
300
200
100
0
TOP
3.0A
4.2A
15V
BOTTOM 6.7A
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01
Ω
t
p
Fig 12c. Unclamped Inductive Test Circuit
25
50
75
100
125
150
Starting T , Junction Temperature (°C)
J
Fig 12a. Maximum Avalanche Energy
V
(BR)DSS
Vs. Drain Current
t
p
I
AS
Fig 12d. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
Q
G
50KΩ
.2µF
12V
VGS
.3µF
Q
Q
GD
GS
+
V
DS
D.U.T.
-
V
V
GS
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b. Basic Gate Charge Waveform
Fig 13a. Gate Charge Test Circuit
6
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IRFIB8N50KPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRFIB8N50KPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
EXAMP LE: THIS IS AN IRFI840 G
WITH AS S EMBLY
LO T CO DE 3 43 2
INT E RNAT IO NAL
AS S EMBLED O N WW 24 199 9
P ART NUMBER
IRFI840G
RE CT IF IE R
LO G O
924K
32
IN THE AS S EMBLY LINE "K"
34
DATE CO DE
YEAR 9 = 199 9
WEEK 24
Note: "P" in assembly line
position indicates "Lead-Free"
AS S EMBLY
LO T CO DE
LINE K
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/04
8
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