IRFR3704ZTRLPBF [INFINEON]
Power Field-Effect Transistor, 30A I(D), 20V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, PLASTIC, DPAK-3;型号: | IRFR3704ZTRLPBF |
厂家: | Infineon |
描述: | Power Field-Effect Transistor, 30A I(D), 20V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE, PLASTIC, DPAK-3 |
文件: | 总12页 (文件大小:263K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 95442A
IRFR3704ZPbF
IRFU3704ZPbF
Applications
HEXFET® Power MOSFET
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l Lead-Free
VDSS RDS(on) max
Qg
8.4m
20V
9.3nC
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D-Pak
IRFR3704Z
I-Pak
IRFU3704Z
Absolute Maximum Ratings
Parameter
Max.
20
Units
VDS
V
Drain-to-Source Voltage
V
± 20
60
Gate-to-Source Voltage
GS
I
I
I
@ TC = 25°C
A
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
D
D
@ TC = 100°C
42
240
48
DM
P
P
@TC = 25°C
@TC = 100°C
W
Maximum Power Dissipation
Maximum Power Dissipation
Linear Derating Factor
D
D
24
0.32
W/°C
°C
T
-55 to + 175
Operating Junction and
J
T
Storage Temperature Range
Soldering Temperature, for 10 seconds
STG
300 (1.6mm from case)
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
3.1
Units
Rθ
°C/W
JC
JA
JA
Junction-to-Case
Rθ
Rθ
50
Junction-to-Ambient (PCB Mount)
Junction-to-Ambient
110
Notes through ꢀ are on page 11
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1
12/03/04
IRFR/U3704ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
20 ––– –––
Conditions
VGS = 0V, ID = 250µA
BVDSS
V
∆ΒVDSS/∆TJ
RDS(on)
Breakdown Voltage Temp. Coefficient ––– 0.015 ––– V/°C Reference to 25°C, ID = 1mA
Ω
m
Static Drain-to-Source On-Resistance
–––
–––
1.65
–––
–––
–––
–––
–––
41
6.7
9.2
2.1
-5.5
–––
–––
–––
–––
–––
9.3
3.0
1.1
2.7
2.5
3.8
5.6
41
8.4
VGS = 10V, ID = 15A
11.4
2.55
VGS = 4.5V, ID = 12A
VDS = VGS, ID = 250µA
VGS(th)
Gate Threshold Voltage
V
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
––– mV/°C
1.0
150
100
-100
–––
14
µA
VDS =16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
nA VGS = 20V
VGS = -20V
gfs
S
VDS = 10V, ID = 12A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
td(on)
tr
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
VDS = 10V
nC VGS = 4.5V
ID = 12A
Gate Charge Overdrive
See Fig. 16
Switch Charge (Qgs2 + Qgd)
Output Charge
nC VDS = 10V, VGS = 0V
Turn-On Delay Time
Rise Time
VDD = 10V, VGS = 4.5V
8.9
4.9
12
ID = 12A
td(off)
tf
Turn-Off Delay Time
Fall Time
ns Clamped Inductive Load
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 1190 –––
VGS = 0V
–––
–––
380
170
–––
–––
pF VDS = 10V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
Units
mJ
A
EAS
IAR
41
12
Avalanche Current
Repetitive Avalanche Energy
EAR
4.8
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
60
IS
D
–––
–––
MOSFET symbol
Continuous Source Current
(Body Diode)
A
showing the
G
ISM
–––
–––
240
integral reverse
Pulsed Source Current
(Body Diode)
S
p-n junction diode.
VSD
trr
–––
–––
–––
–––
13
1.0
19
V
T = 25°C, I = 12A, V = 0V
J S GS
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T = 25°C, I = 12A, VDD = 10V
J
F
Qrr
ton
di/dt = 100A/µs
4.2
6.3
nC
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR/U3704ZPbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
6.0V
4.5V
4.0V
3.3V
2.8V
2.6V
2.4V
6.0V
4.5V
4.0V
3.3V
2.8V
2.6V
2.4V
BOTTOM
BOTTOM
1
2.4V
1
0.1
2.4V
0.1
0.01
0.01
0.001
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.01
0.1
1
10
0.01
0.1
1
10
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.0
1.5
1.0
0.5
I
= 30A
D
V
= 10V
GS
T
= 175°C
J
1
T
= 25°C
J
0.1
0.01
V
= 10V
DS
20µs PULSE WIDTH
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
2
3
4
5
6
7
8
9
, Junction Temperature (°C)
V
, Gate-to-Source Voltage (V)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
vs. Temperature
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3
IRFR/U3704ZPbF
10000
6.0
5.0
4.0
3.0
2.0
1.0
0.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 12A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
V
V
= 18V
= 10V
= C
DS
DS
rss
oss
gd
= C + C
ds
gd
C
iss
1000
C
oss
C
rss
100
1
10
100
0
2
4
6
8
10
12
14
V
, Drain-to-Source Voltage (V)
Q
Total Gate Charge (nC)
G
DS
Fig 6. Typical Gate Charge vs.
Fig 5. Typical Capacitance vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
1.00
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100µsec
T = 25°C
J
1msec
Tc = 25°C
Tj = 175°C
V
= 0V
Single Pulse
GS
10msec
0.10
1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
, Source-to-Drain Voltage (V)
0
1
10
100
V
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFR/U3704ZPbF
2.5
2.0
1.5
1.0
0.5
60
50
40
30
20
10
0
Limited By Package
I
= 250µA
D
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
25
50
75
100
125
150
175
T
J
T
, Case Temperature (°C)
C
Fig 9. Maximum Drain Current vs.
Fig 10. Threshold Voltage vs. Temperature
Case Temperature
10
D = 0.50
1
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.1
0.01
0.02
0.01
0.8190
1.6018
0.6592
0.0418
0.000092
0.000698
0.009033
0.046618
τ
τ
J τJ
τ
Cτ
1τ1
Ci= τi/Ri
τ
τ
τ
2 τ2
3τ3
4τ4
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U3704ZPbF
15V
180
160
140
120
100
80
I
D
TOP
4.9A
6.5A
DRIVER
L
V
DS
BOTTOM 12A
D.U.T
AS
R
+
-
G
V
DD
I
A
2VGS
Ω
0.01
t
p
60
Fig 12a. Unclamped Inductive Test Circuit
40
V
(BR)DSS
20
t
p
0
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
LD
I
AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
-
VDD
D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
.2µF
12V
.3µF
Fig 14a. Switching Time Test Circuit
VDS
+
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
VGS
I
I
D
G
Current Sampling Resistors
td(on)
td(off)
tr
tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRFR/U3704ZPbF
Driver Gate Drive
P.W.
Period
D.U.T
Period
D =
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRFR/U3704ZPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
loss
conduction
drive
output
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
⎛
⎜
Qoss
⎞
⎠
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
(
)
in
rr
in
⎝ 2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on )
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
⎛
⎛
Qgd
ig
⎞
Qgs2
ig
⎞
⎟
⎜
⎟
⎜
+ I ×
× V × f + I ×
× V × f
in
in
⎝
⎠
⎝
⎠
+ Q × V × f
(
)
g
g
⎛ Qoss
⎞
⎠
+
×V × f
in
⎝
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFETdata sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRFR/U3704ZPbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
DATE CODE
WIT H AS S E MB LY
LOT CODE 1234
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
AS SEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
YEAR 9 = 1999
WEE K 16
916A
34
12
LINE A
Note: "P" in as sembly line position
AS S E MB L Y
LOT CODE
indicates "Lead-F ree"
OR
PART NUMBER
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12 34
YEAR 9 = 1999
AS S E MB L Y
LOT CODE
WE EK 16
A = AS S E MB L Y S IT E CODE
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9
IRFR/U3704ZPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
INTERNATIONAL
WITH ASSEMBLY
DAT E CODE
YEAR 9 = 1999
WEEK 19
RECTIFIER
LOGO
IRFU120
919A
78
LOT CODE 5678
AS S EMBLED ON WW 19, 1999
IN THE ASSEMBLY LINE "A"
56
LINE A
ASSEMBLY
LOT CODE
Note: "P" in assembly line
position indicates "Lead-Free"
OR
PART NUMBER
DATE CODE
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
56 78
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
AS S E MB L Y
LOT CODE
WE E K 19
A = AS S E MB L Y S I T E CODE
10
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IRFR/U3704ZPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.57mH, RG = 25Ω,
IAS = 12A.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/04
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11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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