IRFR4104PBF [INFINEON]
HEXFET㈢ Power MOSFET ( VDSS = 40V , RDS(on) = 5.5mヘ , ID = 42A ); HEXFET㈢功率MOSFET （ VDSS = 40V ， RDS （ ON） = 5.5米ヘ， ID = 42A ）
| 型号： | IRFR4104PBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET㈢ Power MOSFET ( VDSS = 40V , RDS(on) = 5.5mヘ , ID = 42A ) |
| 文件： | 总12页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95425A
IRFR4104PbF
AUTOMOTIVE MOSFET
IRFU4104PbF
HEXFET® Power MOSFET
Features
D
l
l
l
l
l
l
Advanced Process Technology
VDSS = 40V
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
RDS(on) = 5.5mΩ
G
ID = 42A
S
Description
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating tempera-
ture, fast switching speed and improved repetitive avalanche
rating . These features combine to make this design an extremely
efficientandreliabledeviceforuseinAutomotiveapplicationsand
a wide variety of other applications.
D-Pak
IRFR4104
I-Pak
IRFU4104
Absolute Maximum Ratings
Parameter
Max.
119
84
Units
(Silicon Limited)
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
I
@ T = 25°C
C
D
D
D
@ T = 100°C
C
A
(Package Limited)
@ T = 25°C
C
42
480
140
DM
P
@T = 25°C
Power Dissipation
C
W
D
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
0.95
± 20
W/°C
V
V
GS
EAS (Thermally limited)
145
310
mJ
Single Pulse Avalanche Energy Tested Value
Avalanche Current
EAS (Tested )
IAR
See Fig.12a, 12b, 15, 16
A
Repetitive Avalanche Energy
EAR
mJ
T
J
Operating Junction and
-55 to + 175
T
Storage Temperature Range
°C
STG
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
300 (1.6mm from case )
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
–––
–––
Max.
1.05
40
Units
Rθ
Rθ
Rθ
Junction-to-Case
Junction-to-Ambient (PCB mount)
JC
JA
JA
°C/W
Junction-to-Ambient
110
HEXFET® is a registered trademark of International Rectifier.
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1
12/06/04
IRFR/U4104PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
40 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
V
∆
∆
V(BR)DSS/ TJ
Breakdown Voltage Temp. Coefficient ––– 0.032 ––– V/°C Reference to 25°C, ID = 1mA
Ω
m
RDS(on)
VGS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
2.0
4.3
–––
–––
–––
–––
–––
–––
59
5.5
4.0
VGS = 10V, ID = 42A
V
VDS = VGS, ID = 250µA
VDS = 10V, ID = 42A
gfs
Forward Transconductance
58
–––
20
S
IDSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA VDS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
250
200
-200
89
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Qg
Qgs
Qgd
td(on)
tr
ID = 42A
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
19
–––
–––
–––
–––
–––
–––
–––
nC VDS = 32V
VGS = 10V
24
17
VDD = 20V
Rise Time
69
ID = 42A
td(off)
tf
Ω
ns RG = 6.8
Turn-Off Delay Time
37
Fall Time
36
VGS = 10V
LD
Internal Drain Inductance
4.5
Between lead,
nH 6mm (0.25in.)
from package
LS
Internal Source Inductance
–––
7.5
–––
and center of die contact
Ciss
Input Capacitance
––– 2950 –––
VGS = 0V
Coss
Output Capacitance
–––
–––
660
370
–––
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
pF ƒ = 1.0MHz
Coss
––– 2130 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
–––
590
850
–––
–––
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 32V
Coss eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
I
Continuous Source Current
–––
–––
42
MOSFET symbol
S
(Body Diode)
A
showing the
I
Pulsed Source Current
–––
–––
480
integral reverse
SM
(Body Diode)
p-n junction diode.
V
t
Diode Forward Voltage
–––
–––
–––
–––
28
1.3
42
36
V
T = 25°C, I = 42A, V = 0V
SD
J
S
GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T = 25°C, I = 42A, VDD = 20V
J F
rr
di/dt = 100A/µs
Q
t
24
nC
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
2
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IRFR/U4104PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
TOP
TOP
BOTTOM 4.5V
BOTTOM 4.5V
4.5V
4.5V
60µs PULSE WIDTH
Tj = 25°C
60µs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
1
10
1
100
1
0.1
1
1
10
1
100
1
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
120
T
= 25°C
J
T
= 175°C
J
100
80
60
40
20
0
T
= 175°C
J
100
10
1
T = 25°C
J
V
= 20V
DS
V
= 10V
DS
60µs PULSE WIDTH
380µs PULSE WIDTH
4
6
8 10
0
20
40
60
80
100
V
, Gate-to-Source Voltage (V)
GS
I
Drain-to-Source Current (A)
D,
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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3
IRFR/U4104PbF
5000
20
16
12
8
V
= 0V,
= C
f = 1 MHZ
GS
I = 42A
D
V
= 32V
C
C
C
+ C , C
SHORTED
DS
VDS= 20V
iss
gs
gd
ds
= C
rss
oss
gd
4000
3000
2000
1000
0
= C + C
ds
gd
Ciss
Coss
Crss
4
0
0
20
Q
40
60
80
100
1
10
, Drain-to-Source Voltage (V)
100
Total Gate Charge (nC)
G
V
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
10000
1000
100
10
1000.0
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 175°C
J
100µsec
T
= 25°C
J
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.1
0
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
V
, Drain-toSource Voltage (V)
DS
V
, Source-toDrain Voltage (V)
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRFR/U4104PbF
2.0
1.5
1.0
0.5
120
100
80
60
40
20
0
I
= 42A
= 10V
D
LIMITED BY PACKAGE
V
GS
25
50
75
100
125
150
175
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
, Junction Temperature (°C)
C
J
Fig 10. Normalized On-Resistance
Fig 9. Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
10
1
D = 0.50
0.20
R1
R1
R2
R2
0.10
0.1
0.01
Ri (°C/W) τi (sec)
τ
J τJ
τ
0.5067
0.000414
τ
0.05
Cτ
τ
1 τ1
Ci= τi/Ri
2τ2
0.02
0.01
0.5428
0.004081
Notes:
1. Duty Factor D = t1/t2
SINGLE PULSE
2. Peak Tj = P dm x Zthjc + Tc
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U4104PbF
600
500
400
300
200
100
0
15V
I
D
TOP
9.2A
13A
42A
DRIVER
+
L
V
BOTTOM
DS
D.U.T
AS
R
G
V
DD
-
I
A
2
V0GVS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
4.0
3.0
2.0
1.0
GS
GD
V
G
I
= 250µA
D
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
V
GS
3mA
T
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRFR/U4104PbF
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
∆
assuming
Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
160
Notes on Repetitive Avalanche Curves , Figures 15, 16:
TOP
BOTTOM 1% Duty Cycle
= 42A
Single Pulse
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
I
D
120
80
40
0
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25
50
75
100
125
150
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Fig 16. Maximum Avalanche Energy
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRFR/U4104PbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 18b. Switching Time Waveforms
8
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IRFR/U4104PbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WIT H AS S EMBLY
LOT CODE 1234
INTERNATIONAL
RECTIFIER
LOGO
DAT E CODE
YEAR 9 = 1999
WE EK 16
IRFU120
916A
34
AS S E MB LED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
12
LINE A
Note: "P" in assembly line position
AS S E MB L Y
LOT CODE
indicates "Lead-F ree"
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
IRFU120
12 34
YEAR 9 = 1999
AS S E MB L Y
LOT CODE
WEE K 16
A = AS S E MB L Y S IT E CODE
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9
IRFR/U4104PbF
I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
PART NUMBER
EXAMPLE: THIS IS AN IRFU120
WIT H AS S EMBL Y
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
YEAR 9 = 1999
WE EK 19
IRFU120
919A
78
LOT CODE 5678
ASS EMBLED ON WW 19, 1999
56
IN THE ASSEMBLY LINE "A"
LINE A
AS S E MB L Y
LOT CODE
Note: "P" in ass embly line
pos ition indi cates "L ead-F ree"
OR
PART NUMBER
DAT E CODE
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
56
78
YEAR 9 = 1999
ASSEMBLY
LOT CODE
WEE K 19
A = AS S E MB L Y S IT E CODE
10
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IRFR/U4104PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRL
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.16mH
as Coss while VDS is rising from 0 to 80% VDSS
.
ꢀ
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
RG = 25Ω, IAS = 42A, VGS =10V. Part not
recommended for use above this value.
This value determined from sample failure population. 100%
tested to this value in production.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
www.irf.com
11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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