IRFS3307TRR [INFINEON]
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| 型号： | IRFS3307TRR |
| 厂家： | 
Infineon |
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PD - 96901A
IRFB3307
IRFS3307
IRFSL3307
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
S
VDSS
RDS(on) typ.
max.
75V
5.0m
6.3m
:
:
G
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
ID
130A
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
G D S
G D S
G D S
D2Pak
IRFS3307
TO-262
IRFSL3307
TO-220AB
IRFB3307
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current d
Max.
130c
91c
Units
A
510
PD @TC = 25°C
250
W
Maximum Power Dissipation
Linear Derating Factor
1.6
W/°C
V
VGS
± 20
Gate-to-Source Voltage
11
Peak Diode Recovery f
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
270
mJ
A
Avalanche Currentꢀc
IAR
See Fig. 14, 15, 16a, 16b
Repetitive Avalanche Energy g
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.61
–––
62
Units
RθJC
Junction-to-Case k
RθCS
RθJA
RθJA
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220 k
2
–––
40
Junction-to-Ambient (PCB Mount) , D Pak
jk
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1
11/04/04
IRFB3307/IRFS3307/IRFSL3307
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
75 ––– –––
––– 0.069 ––– V/°C Reference to 25°C, ID = 1mAd
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
5.0
6.3
4.0
20
VGS = 10V, ID = 75A g
mΩ
V
VGS(th)
–––
V
V
V
DS = VGS, ID = 150µA
IDSS
Drain-to-Source Leakage Current
––– –––
µA
DS = 75V, VGS = 0V
––– ––– 250
––– ––– 200
––– ––– -200
DS = 75V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
nA VGS = 20V
GS = -20V
f = 1MHz, open drain
V
RG
–––
1.5
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
98 ––– –––
––– 120 180
Conditions
VDS = 50V, ID = 75A
nC ID = 75A
DS = 60V
VGS = 10V g
DD = 48V
S
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
–––
–––
–––
35
46
26
–––
–––
–––
V
ns
V
––– 120 –––
ID = 75A
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
51
63
–––
–––
RG = 3.9Ω
VGS = 10V g
Ciss
Coss
Crss
Input Capacitance
––– 5150 –––
––– 460 –––
––– 250 –––
––– 570 –––
––– 700 –––
pF VGS = 0V
DS = 50V
ƒ = 1.0MHz
Output Capacitance
Reverse Transfer Capacitance
V
Coss eff. (ER)
Effective Output Capacitance (Energy Related)
VGS = 0V, VDS = 0V to 60V i, See Fig.11
GS = 0V, VDS = 0V to 60V h, See Fig. 5
Coss eff. (TR)
V
Effective Output Capacitance (Time Related)
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
D
S
Continuous Source Current
––– –––
A
MOSFET symbol
130
c
(Body Diode)
Pulsed Source Current
(Body Diode)ꢀd
showing the
integral reverse
G
ISM
––– ––– 510
A
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
57
V
TJ = 25°C, IS = 75A, VGS = 0V g
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 64V,
–––
–––
–––
–––
–––
38
46
65
86
2.8
ns
IF = 75A
di/dt = 100A/µs g
69
Qrr
Reverse Recovery Charge
98
nC
130
–––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.096mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
ISD ≤ 75A, di/dt ≤ 530A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢁ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRFB3307/IRFS3307/IRFSL3307
1000
1000
100
10
VGS
15V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
100
10
1
BOTTOM
BOTTOM
1
4.5V
4.5V
0.1
0.01
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
≤
Tj = 25°C
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
2
4
6
8
10
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
, Junction Temperature (°C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
12.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 75A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
= C
10.0
8.0
6.0
4.0
2.0
0.0
V
V
V
= 60V
= 38V
= 15V
rss
oss
gd
DS
DS
DS
= C + C
ds
gd
C
iss
C
oss
C
rss
100
0
20
40
60
80
100 120 140
1
10
, Drain-to-Source Voltage (V)
100
Q
Total Gate Charge (nC)
V
G
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB3307/IRFS3307/IRFSL3307
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100
10
1
1msec 100µsec
10msec
T
= 25°C
J
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
, Source-to-Drain Voltage (V)
1
10
, Drain-to-Source Voltage (V)
100
V
V
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
100
95
90
85
80
75
70
140
120
100
80
60
40
20
0
Limited By Package
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
, Temperature ( °C )
25
50
75
100
125
150
175
T
T
, Case Temperature (°C)
J
C
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
1.4
1200
I
D
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TOP
8.6A
12A
1000
800
600
400
200
0
BOTTOM 75A
0
10 20 30 40 50 60 70 80
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
DS,
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
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IRFB3307/IRFS3307/IRFSL3307
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
0.02
0.01
Ri (°C/W) τi (sec)
0.2911 0.000484
0.01
τ
J τJ
τ
τ
Cτ
1τ1
Ci= τi/Ri
τ
2τ2
0.3196 0.005529
SINGLE PULSE
( THERMAL RESPONSE )
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
0.01
∆
assuming
Tj = 25°C due to
avalanche losses
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
Single Pulse
BOTTOM 1% Duty Cycle
= 75A
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB3307/IRFS3307/IRFSL3307
5.0
4.5
4.0
3.5
20
15
10
5
I
I
I
I
= 150µA
= 250µA
= 1.0mA
= 1.0A
D
D
D
D
3.0
2.5
2.0
1.5
I
= 30A
= 64V
F
V
T
R
= 25°C _____
= 125°C ----------
J
T
J
0
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
100 200 300 400 500 600 700 800 900 1000
T
di /dt (A/µs)
f
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
400
20
350
300
250
200
150
100
50
15
10
5
I
= 30A
= 64V
I
= 45A
= 64V
F
F
V
T
V
T
R
R
= 25°C _____
= 125°C ----------
= 25°C _____
= 125°C ----------
J
J
T
T
J
J
0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di /dt (A/µs)
f
di /dt (A/µs)
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
400
350
300
250
200
150
100
50
I
= 45A
= 64V
F
V
R
T
= 25°C _____
= 125°C ----------
J
T
J
0
100 200 300 400 500 600 700 800 900 1000
di /dt (A/µs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB3307/IRFS3307/IRFSL3307
Driver Gate Drive
P.W.
Period
Period
D =
D.U.T
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
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7
IRFB3307/IRFS3307/IRFSL3307
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
- B -
3.78 (.149)
3.54 (.139)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
LEAD ASSIGNMENTS
1 - GATE
1
2
3
2 - DRAIN
3 - SOURCE
4 - DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
Note: "P" in assembly line
position indicates "Lead-Free"
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRFB3307/IRFS3307/IRFSL3307
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
TO-262 Part Marking Information
OR
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9
IRFB3307/IRFS3307/IRFSL3307
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
OR
10
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IRFB3307/IRFS3307/IRFSL3307
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/04
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11
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