IRFS3806 [INFINEON]
60V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 封装;型号: | IRFS3806 |
厂家: | Infineon |
描述: | 60V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 封装 |
文件: | 总12页 (文件大小:573K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 97310
IRFB3806PbF
IRFS3806PbF
Applications
IRFSL3806PbF
HEXFET® Power MOSFET
60V
l High Efficiency Synchronous Rectification in
SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
S
VDSS
RDS(on) typ.
max.
12.6m
15.8m
43A
Ω
Ω
G
Benefits
ID
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
D
D
D
l Enhanced body diode dV/dt and dI/dt
Capability
S
S
S
D
D
G
G
G
D2Pak
TO-262
TO-220AB
IRFB3806PbF
IRFS3806PbF
IRFSL3806PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current c
Max.
43
Units
A
ID @ TC = 100°C
IDM
31
170
71
PD @TC = 25°C
W
Maximum Power Dissipation
Linear Derating Factor
0.47
20
W/°C
V
VGS
Gate-to-Source Voltage
24
Peak Diode Recovery e
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy d
EAS (Thermally limited)
73
25
mJ
A
Avalanche Current c
IAR
Repetitive Avalanche Energy f
EAR
7.1
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Units
RθJC
–––
0.50
–––
–––
Junction-to-Case j
2.12
–––
62
RθCS
RθJA
RθJA
°C/W
Case-to-Sink, Flat Greased Surface, TO-220
Junction-to-Ambient, TO-220 ij
Junction-to-Ambient (PCB Mount) , D2Pak ij
40
www.irf.com
1
02/29/08
IRFB/S/SL3806PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
60 ––– –––
––– 0.075 ––– V/°C Reference to 25°C, ID = 5mAc
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
––– 12.6 15.8
VGS = 10V, ID = 25A f
mΩ
V
VGS(th)
2.0
–––
4.0
20
V
V
V
DS = VGS, ID = 50µA
IDSS
Drain-to-Source Leakage Current
––– –––
µA
DS = 60V, VGS = 0V
––– ––– 250
––– ––– 100
––– ––– -100
DS = 48V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA VGS = 20V
GS = -20V
V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 10V, ID = 25A
nC ID = 25A
DS = 30V
41
––– –––
S
Qg
–––
–––
–––
22
5.0
6.3
30
Qgs
Qgd
Qsync
Gate-to-Source Charge
–––
–––
V
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
VGS = 10V f
––– 28.3 –––
ID = 25A, VDS =0V, VGS = 10V
RG(int)
td(on)
–––
–––
–––
–––
–––
Ω
Internal Gate Resistance
Turn-On Delay Time
Rise Time
0.79 –––
6.3
40
49
47
–––
–––
–––
–––
ns VDD = 39V
ID = 25A
tr
td(off)
Turn-Off Delay Time
Fall Time
RG = 20Ω
VGS = 10V f
tf
Ciss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 1150 –––
––– 130 –––
V
GS = 0V
Coss
VDS = 50V
Crss
–––
67
–––
pF ƒ = 1.0MHz
Coss eff. (ER)
Coss eff. (TR)
––– 190 –––
––– 230 –––
V
GS = 0V, VDS = 0V to 60V h
Effective Output Capacitance (Energy Related)
h
VGS = 0V, VDS = 0V to 60V g
Effective Output Capacitance (Time Related)
g
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
D
S
Continuous Source Current
––– –––
A
MOSFET symbol
43
(Body Diode)
Pulsed Source Current
(Body Diode)ꢀc
showing the
integral reverse
G
ISM
––– ––– 170
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
33
V
TJ = 25°C, IS = 25A, VGS = 0V f
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 51V,
–––
–––
–––
–––
–––
22
26
17
24
1.4
ns
IF = 25A
di/dt = 100A/µs f
39
Qrr
Reverse Recovery Charge
26
nC
36
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.23mH
RG = 25Ω, IAS = 25A, VGS =10V. Part not recommended for
use above this value.
ISD ≤ 25A, di/dt ≤ 1580A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
2
www.irf.com
IRFB/S/SL3806PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 25A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
J
1
V
= 25V
DS
60µs PULSE WIDTH
≤
0.1
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
12.0
10000
1000
100
V
C
= 0V,
f = 1 MHZ
GS
I = 25A
D
= C + C , C SHORTED
iss
gs gd ds
V
V
V
= 48V
= 30V
= 12V
C
= C
DS
DS
DS
10.0
8.0
6.0
4.0
2.0
0.0
rss
gd
C
= C + C
oss
ds
C
gd
iss
C
oss
C
rss
10
0
5
10
15
20
25
1
10
, Drain-to-Source Voltage (V)
100
Q
, Total Gate Charge (nC)
V
G
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB/S/SL3806PbF
1000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100
100µsec
1msec
T
= 175°C
J
10
1
T
= 25°C
J
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
DC
V
= 0V
GS
0.1
0.1
0.0
0.5
1.0
1.5
2.0
1
10
100
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
80
75
70
65
60
45
40
35
30
25
20
15
10
5
Id = 5mA
0
-60 -40 -20
0
T
20 40 60 80 100120140160180
, Temperature ( °C )
25
50
75
100
125
150
175
T
, Case Temperature (°C)
J
C
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
0.4
300
I
D
0.3
0.3
0.2
0.2
0.1
0.1
0.0
TOP
2.8A
5.1A
250
200
150
100
50
BOTTOM 25A
0
-10
0
10 20 30 40 50 60 70
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
V
DS,
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
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IRFB/S/SL3806PbF
10
1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
0.6086 0.00026
0.1
τ
JτJ
τ
τ
Cτ
0.02
0.01
τ
1τ1
τ
2 τ2
3τ3
0.9926 0.001228
0.5203 0.00812
Ci= τi/Ri
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
0.01
pulsewidth, tav, assuming Tj = 150°C and
∆
Tstart =25°C (Single Pulse)
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
∆Τ
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
80
60
40
20
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1.0% Duty Cycle
= 25A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB/S/SL3806PbF
4.0
3.5
3.0
14
12
10
8
I = 17A
F
V
= 51V
R
T = 25°C
J
T = 125°C
J
2.5
2.0
1.5
1.0
I
I
I
I
= 50µA
= 250µA
= 1.0mA
= 1.0A
D
D
D
D
6
4
2
0
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
0
200
400
600
800
1000
T
di /dt (A/µs)
J
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
14
260
I = 25A
I = 17A
F
F
12
10
8
V
= 51V
V
= 51V
R
R
210
160
110
60
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
6
4
2
0
10
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
di /dt (A/µs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
260
I = 25A
F
V
= 51V
R
210
160
110
60
T = 25°C
J
T = 125°C
J
10
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB/S/SL3806PbF
Driver Gate Drive
P.W.
P.W.
D =
Period
D.U.T
Period
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
-
I
A
AS
V
2
GS
0.01Ω
t
p
I
AS
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
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7
IRFB/S/SL3806PbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
Note: "P" in assembly line
position indicates "Lead-Free"
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRFB/S/SL3806PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
25
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com
9
IRFB/S/SL3806PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
25
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRFB/S/SL3806PbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/08
www.irf.com
11
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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