IRFS7530-7P [INFINEON]
60V 单个 N 通道 HEXFET Power MOSFET, 采用 7引脚 D2-Pak 封装;型号: | IRFS7530-7P |
厂家: | Infineon |
描述: | 60V 单个 N 通道 HEXFET Power MOSFET, 采用 7引脚 D2-Pak 封装 |
文件: | 总12页 (文件大小:571K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
StrongIRFET™
IRFS7530-7PPbF
HEXFET® Power MOSFET
Application
Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
VDSS
RDS(on) typ.
max
60V
1.15m
1.4m
338A
ID (Silicon Limited)
ID (Package Limited)
240A
Benefits
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free, RoHS Compliant
G
D
S
Gate
Drain
Source
Base Part Number
Package Type
Standard Pack
Complete Part Number
Form
Tube
Quantity
50
IRFS7530-7PPbF
IRFS7530TRL7PP
IRFS7530-7PPbF
D2Pak-7PIN
Tape and Reel Left
800
6
5
4
3
2
1
350
300
250
200
150
100
50
I
= 100A
D
Limited By Package
T = 125°C
J
T = 25°C
J
0
4
8
12
16
20
0
25
50
75
100
125
150
175
V
, Gate-to-Source Voltage (V)
GS
T
, Case Temperature (°C)
C
Fig 2. Maximum Drain Current vs. Case Temperature
Fig 1. Typical On-Resistance vs. Gate Voltage
1
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IRFS7530-7PPbF
Absolute Maximium Rating
Symbol
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
338
239
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
A
ID @ TC = 25°C
IDM
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
Pulsed Drain Current
240
1450
375
PD @TC = 25°C
Maximum Power Dissipation
Linear Derating Factor
W
W/°C
V
2.5
VGS
TJ
Gate-to-Source Voltage
± 20
Operating Junction and
-55 to + 175
300
°C
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Avalanche Characteristics
EAS (Thermally limited)
526
Single Pulse Avalanche Energy
mJ
EAS (Thermally limited)
1029
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
IAR
EAR
A
mJ
See Fig 14, 15, 23a, 23b
Thermal Resistance
Symbol
Parameter
Typ.
Max.
Units
Junction-to-Case
–––
0.40
RJC
RJA
°C/W
Junction-to-Ambient
–––
40
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
60
––– –––
V
VGS = 0V, ID = 250µA
–––
33 ––– mV/°C Reference to 25°C, ID = 1mA
V(BR)DSS/TJ
RDS(on)
––– 1.15 1.4
VGS = 10V, ID = 100A
VGS = 6.0V, ID = 50A
VDS = VGS, ID = 250µA
VDS = 60 V, VGS = 0V
m
m
V
–––
1.4
–––
3.7
1.0
VGS(th)
IDSS
Gate Threshold Voltage
2.1 –––
––– –––
Drain-to-Source Leakage Current
µA
––– ––– 150
––– ––– 100
––– ––– -100
V
DS = 60V,VGS = 0V,TJ =125°C
VGS = 20V
GS = -20V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
nA
V
RG
–––
2.2
–––
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A.
Note that current limitations arising from heating of the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 105µH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 1575A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS
.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS
.
R is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 45A, VGS =10V.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf
2
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IRFS7530-7PPbF
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 10V, ID =100A
ID = 100A
249 ––– –––
––– 236 354
S
Qg
Qgs
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
–––
–––
62
73
–––
–––
VDS = 30V
nC
Qgd
VGS = 10V
Qsync
td(on)
tr
––– 163 –––
––– 24 –––
VDD = 30V
ID = 100A
Rise Time
––– 102 –––
––– 168 –––
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG= 2.7
VGS = 10V
–––
79
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 12960 –––
––– 1270 –––
––– 760 –––
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
pF
Coss eff.(ER) Effective Output Capacitance (Energy Related) ––– 1248 –––
VGS = 0V, VDS = 0V to 48V
VGS = 0V, VDS = 0V to 48V
Coss eff.(TR) Output Capacitance (Time Related)
––– 1590 –––
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
D
––– ––– 338
A
––– ––– 1450
G
ISM
S
VSD
Diode Forward Voltage
––– –––
1.2
V
TJ = 25°C,IS = 100A,VGS = 0V
dv/dt
Peak Diode Recovery dv/dt
–––
–––
–––
–––
–––
–––
8.5
48
50
72
83
2.5
––– V/ns TJ = 175°C,IS =100A,VDS = 60V
–––
–––
–––
–––
–––
TJ = 25°C
VDD = 51V
IF = 100A,
trr
Reverse Recovery Time
ns
TJ = 125°C
TJ = 25°C di/dt = 100A/µs
Qrr
Reverse Recovery Charge
Reverse Recovery Current
nC
A
TJ = 125°C
IRRM
TJ = 25°C
3
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IRFS7530-7PPbF
10000
1000
100
10
10000
1000
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 25°C
60µs PULSE WIDTH
Tj = 175°C
1
10
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 4. Typical Output Characteristics
Fig 3. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
10000
I
= 100A
= 10V
D
V
GS
1000
T = 175°C
J
100
T = 25°C
J
10
1
V
= 25V
DS
60µs PULSE WIDTH
0.1
2.0
4.0
6.0
8.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
V
, Gate-to-Source Voltage (V)
GS
T , Junction Temperature (°C)
J
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
1000000
100000
10000
1000
14
V
= 0V,
f = 1 MHZ
GS
I = 100A
D
V
V
V
= 48V
= 30V
12V
C
C
C
= C + C , C SHORTED
DS
DS
iss
gs
gd
ds
gd
ds
12
10
8
= C
= C
rss
oss
+ C
gd
DS=
Ciss
6
4
Coss
Crss
2
0
100
0
50
Q
100
150
200
250
300
1
10
, Drain-to-Source Voltage (V)
100
Total Gate Charge (nC)
G
V
DS
Fig 8. Typical Gate Charge vs.
Fig 7. Typical Capacitance vs.
Gate-to-Source Voltage
4
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IRFS7530-7PPbF
10000
1000
100
10
10000
1000
100
10
100µsec
1msec
T = 175°C
J
imited by
L
Package
T = 25°C
J
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
10msec
DC
1
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
1.4
GS
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.6
0.1
1
10
100
V
, Source-to-Drain Voltage (V)
SD
V
, Drain-toSource Voltage (V)
DS
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
80
2.0
Id = 1.0mA
1.5
1.0
0.5
0.0
70
60
0
10
V
20
30
40
50
60
-60 -40 -20 0 20 40 60 80 100120140160180
Drain-to-Source Voltage (V)
T , Temperature ( °C )
J
DS,
Fig 12. Typical Coss Stored Energy
Fig 11. Drain-to-Source Breakdown Voltage
2.2
V
V
V
V
V
= 5.5V
= 6.0V
= 7.0V
= 8.0V
= 10V
GS
GS
GS
GS
GS
2.0
1.8
1.6
1.4
1.2
1.0
0
50
100
150
200
I , Drain Current (A)
D
Fig 13. Typical On-Resistance vs. Drain Current
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IRFS7530-7PPbF
1
0.1
D = 0.50
0.20
0.10
0.05
0.01
0.02
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C. (Single Pulse)
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Avalanche Current vs. Pulse Width
2400
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
I
D
TOP
21A
44A
100A
2000
1600
1200
800
400
0
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
BOTTOM
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
25
50
75
100
125
150
175
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
I
av = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)· av
t
Fig 16. Maximum Avalanche Energy vs. Temperature
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IRFS7530-7PPbF
16
12
8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I
= 60A
= 51V
F
V
R
T = 25°C
J
T = 125°C
J
I
= 250µA
= 1.0mA
= 1.0A
D
I
D
I
D
4
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
400
600
800
1000
T , Temperature ( °C )
di /dt (A/µs)
J
F
Fig 17. Threshold Voltage vs. Temperature
Fig 18. Typical Recovery Current vs. dif/dt
500
400
300
200
100
0
16
I
= 60A
= 51V
I
= 100A
= 51V
F
F
V
V
R
R
T = 25°C
T = 25°C
J
12
8
J
T = 125°C
J
T = 125°C
J
4
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
di /dt (A/µs)
F
F
Fig 20. Typical Stored Charge vs. dif/dt
Fig 19. Typical Recovery Current vs. dif/dt
500
I
= 100A
= 51V
F
V
R
400
300
200
100
0
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig 21. Typical Stored Charge vs. dif/dt
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IRFS7530-7PPbF
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V
(BR)DSS
t
p
15V
DRIVER
+
L
V
DS
D.U.T
R
G
V
DD
-
I
A
AS
20V
I
0.01
t
p
AS
Fig 23a. Unclamped Inductive Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 25b. Gate Charge Waveform
Fig 25a. Gate Charge Test Circuit
8
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IRFS7530-7PPbF
D2Pak-7Pin Package Outline (Dimensions are shown in millimeters (inches))
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
9
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IRFS7530-7PPbF
D2Pak-7Pin Part Marking Information
D2Pak-7Pin Tape and Reel
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFS7530-7PPbF
Qualification Information†
Qualification Level
Industrial
(per JEDEC JESD47F) ††
MSL1
D2Pak-7Pin
Moisture Sensitivity Level
RoHS Compliant
(per JEDEC J-STD-020D††)
Yes
†
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/
†† Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comment
Updated EAS (L =1mH) = 1029mJ on page 2
03/05/2015
Updated note 9 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 45A, VGS =10V” on page 2
Updated package outline on page 9 .
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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