IRFSL4010 [INFINEON]
The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;
| 型号： | IRFSL4010 |
| 厂家： | 
Infineon |
| 描述： | The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. |
| 文件： | 总11页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 96186A
IRFS4010PbF
IRFSL4010PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
D
VDSS
RDS(on) typ.
100V
3.9m
4.7m
180A
G
max.
l Hard Switched and High Frequency Circuits
ID
S
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
D
D
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
S
S
D
G
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
G
D2Pak
IRFS4010PbF
TO-262
IRFSL4010PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Max.
180
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
127
A
720
PD @TC = 25°C
W
375
Maximum Power Dissipation
Linear Derating Factor
2.5
W/°C
V
VGS
± 20
Gate-to-Source Voltage
31
Peak Diode Recovery
dv/dt
TJ
V/ns
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
°C
300
Avalanche Characteristics
Single Pulse Avalanche Energy
EAS (Thermally limited)
318
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.40
40
Units
Rθ
Junction-to-Case
JC
°C/W
RθJA
–––
Junction-to-Ambient (PCB Mount)
www.irf.com
1
07/07/11
IRFS/SL4010PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
100 ––– –––
––– 0.10 ––– V/°C Reference to 25°C, ID = 5mA
Conditions
VGS = 0V, ID = 250μA
V
ΔV(BR)DSS/ΔTJ
RDS(on)
–––
2.0
3.9
4.7
4.0
20
VGS = 10V, ID = 106A
mΩ
V
VGS(th)
–––
VDS = VGS, ID = 250μA
IDSS
Drain-to-Source Leakage Current
––– –––
VDS = 100V, VGS = 0V
μA
––– ––– 250
––– ––– 100
––– ––– -100
VDS = 100V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
VGS = 20V
GS = -20V
nA
V
RG(int)
–––
2.0
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 25V, ID = 106A
189 ––– –––
S
––– 143 215
ID = 106A
Qgs
Gate-to-Source Charge
–––
–––
–––
–––
–––
38
50
93
21
86
–––
–––
–––
–––
–––
VDS = 50V
nC
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
VGS = 10V
Qsync
ID = 106A, VDS =0V, VGS = 10V
VDD = 65V
td(on)
Turn-On Delay Time
tr
Rise Time
ID = 106A
ns
td(off)
Turn-Off Delay Time
––– 100 –––
––– 77 –––
RG = 2.7Ω
VGS = 10V
tf
Fall Time
Ciss
Input Capacitance
––– 9575 –––
––– 660 –––
––– 270 –––
––– 757 –––
––– 1112 –––
V
GS = 0V
Coss
Output Capacitance
VDS = 50V
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
ƒ = 1.0MHz See Fig.5
pF
Coss eff. (ER)
Coss eff. (TR)
V
GS = 0V, VDS = 0V to 80V See Fig.11
GS = 0V, VDS = 0V to 80V
V
Diode Characteristics
Symbol
Parameter
Continuous Source Current
Min. Typ. Max. Units
Conditions
MOSFET symbol
IS
D
––– ––– 180
A
(Body Diode)
showing the
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
––– ––– 720
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
–––
–––
V
TJ = 25°C, IS = 106A, VGS = 0V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
–––
–––
72
81
ns
IF = 106A
di/dt = 100A/μs
Qrr
Reverse Recovery Charge
––– 210 –––
––– 268 –––
nC
A
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
5.3
–––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.057mH
RG = 25Ω, IAS = 106A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 106A, di/dt ≤ 1319A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
ꢀCoss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering echniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
RθJC value shown is at time zero
2
www.irf.com
IRFS/SL4010PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
TOP
TOP
BOTTOM
BOTTOM
1
60μs PULSE WIDTH
Tj = 25°C
≤
60μs PULSE WIDTH
Tj = 175°C
≤
4.0V
4.0V
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 106A
= 10V
D
V
GS
T = 175°C
J
T
= 25°C
= 50V
J
1
V
DS
≤60μs PULSE WIDTH
0.1
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
14.0
V
= 0V,
= C
f = 1 MHZ
GS
C
C
C
+ C , C
SHORTED
ds
iss
gs
gd
I = 106A
D
= C
12.0
rss
oss
gd
V
V
= 80V
= 50V
DS
DS
= C + C
ds
gd
10.0
8.0
6.0
4.0
2.0
0.0
C
iss
C
oss
C
rss
100
1
10
100
1000
0
25 50 75 100 125 150 175 200 225
V
, Drain-to-Source Voltage (V)
Q , Total Gate Charge (nC)
G
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS/SL4010PbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
100μsec
J
100
10
1msec
T
= 25°C
10msec
DC
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
V
= 0V
GS
0.01
1.0
0.1
1
10
100
1000
0.2
0.6
1.0
1.4
1.8
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
130
125
120
115
110
105
100
95
200
Id = 5mA
180
160
140
120
100
80
60
40
20
0
-60 -40 -20 0 20 40 60 80 100120140160180
25
50
75
100
125
150
175
T , Temperature ( °C )
J
Fig 10. Drain-to-Source Breakdown Voltage
T
, Case Temperature (°C)
C
Fig 9. Maximum Drain Current vs.
Case Temperature
4.0
1400
I
D
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1200
1000
800
600
400
200
0
TOP
12.5A
17A
BOTTOM 106A
0
20
V
40
60
80
100
120
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Drain-to-Source Voltage (V)
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
www.irf.com
IRFS/SL4010PbF
1
0.1
D = 0.50
0.20
0.10
0.05
0.02
0.01
0.01
R1
R1
R2
R2
Ri (°C/W) τi (sec)
τ
0.17537
0.000343
J τJ
τ
τ
Cτ
1 τ1
Ci= τi/Ri
τ
0.22547
0.006073
2τ2
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
350
300
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1.0% Duty Cycle
= 106A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS/SL4010PbF
4.5
4.0
3.5
3.0
35
30
25
20
15
10
5
I = 70A
F
V
= 85V
R
T = 25°C
J
T = 125°C
J
I
I
I
= 250μA
= 1.0mA
= 1.0A
D
D
D
2.5
2.0
1.5
1.0
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
400
600
800
1000
T , Temperature ( °C )
di /dt (A/μs)
J
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
1100
35
I = 70A
I = 106A
F
F
1000
900
800
700
600
500
400
300
200
100
V
= 85V
30
25
20
15
10
5
V
= 85V
R
R
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
1100
I = 106A
F
V
1000
900
800
700
600
500
400
300
200
= 85V
R
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/μs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
www.irf.com
IRFS/SL4010PbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2μF
12V
.3μF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFS/SL4010PbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 7 = 1997
WEEK 19
ASSEMBLY
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DE S IGNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
ASSEMBLY
LOT CODE
WEEK 19
A = AS S E MBLY S IT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
www.irf.com
IRFS/SL4010PbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
THIS IS AN IRF530S WITH
PART NUMBER
LOT CODE 8024
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
DAT E CODE
YEAR 0 = 2000
WE EK 02
AS S E MBL Y
LOT CODE
LINE L
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
F530S
DATE CODE
P = DESIGNATES LEAD - FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
AS S E MB L Y
LOT CODE
WEEK 02
A = AS S E MB L Y S IT E CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com
9
IRFS/SL4010PbF
D2Pak (TO-263AB) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 101N.Sepulveda blvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2011
www.irf.com
10
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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Power Field-Effect Transistor, 41A I(D), 150V, 0.045ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, TO-262, 3 PIN
INFINEON
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