IRFSL4410ZTRRPBF [INFINEON]
Power Field-Effect Transistor, 75A I(D), 100V, 0.009ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, LEAD FREE, PLASTIC, TO-262, 3 PIN;
| 型号： | IRFSL4410ZTRRPBF |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 75A I(D), 100V, 0.009ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, LEAD FREE, PLASTIC, TO-262, 3 PIN |
| 文件： | 总11页 (文件大小：839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97278B
IRFB4410ZPbF
IRFS4410ZPbF
IRFSL4410ZPbF
HEXFET® Power MOSFET
D
S
Applications
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
ID (Package Limited)
100V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
7.2m
9.0m
:
:
G
97
c
75A
Benefits
D
D
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
l Fully Characterized Capacitance and Avalanche
S
D
S
S
SOA
D
D
G
G
G
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
D2Pak
IRFS4410ZPbF
TO-262
TO-220AB
IRFSL4410ZPbF
IRFB4410ZPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
Parameter
Max.
97c
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current d
69c
A
75
390
PD @TC = 25°C
230
W
Maximum Power Dissipation
1.5
Linear Derating Factor
W/°C
V
VGS
± 20
Gate-to-Source Voltage
16
Peak Diode Recovery f
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
242
mJ
A
Avalanche Currentꢀc
IAR
See Fig. 14, 15, 22a, 22b,
Repetitive Avalanche Energy g
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.65
–––
62
Units
RθJC
Junction-to-Case k
RθCS
RθJA
RθJA
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220 k
2
–––
40
Junction-to-Ambient (PCB Mount) , D Pak
jk
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1
06/01/07
IRF/B/S/SL4410ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
100 ––– –––
––– 0.12 ––– V/°C Reference to 25°C, ID = 5mAd
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
7.2
9.0
4.0
20
VGS = 10V, ID = 58A g
mΩ
V
VGS(th)
–––
VDS = VGS, ID = 150µA
IDSS
Drain-to-Source Leakage Current
––– –––
µA
VDS = 100V, VGS = 0V
––– ––– 250
––– ––– 100
––– ––– -100
––– 0.70 –––
V
DS = 80V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA VGS = 20V
GS = -20V
V
RG
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Min. Typ. Max. Units
140 ––– –––
Conditions
VDS = 10V, ID = 58A
S
Qg
Total Gate Charge
–––
–––
–––
–––
–––
–––
–––
–––
83
19
27
56
16
52
43
57
120
–––
nC ID = 58A
VDS =50V
VGS = 10V g
ID = 58A, VDS =0V, VGS = 10V g
ns VDD = 65V
Qgs
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Qgd
Qsync
–––
–––
–––
–––
–––
td(on)
tr
ID = 58A
td(off)
Turn-Off Delay Time
Fall Time
RG =2.7Ω
VGS = 10V g
tf
Ciss
Input Capacitance
––– 4820 –––
––– 340 –––
––– 170 –––
––– 420 –––
––– 690 –––
pF VGS = 0V
DS = 50V
ƒ = 1.0MHz, See Fig.5
Coss
Output Capacitance
Reverse Transfer Capacitance
V
Crss
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 80V i, See Fig.11
GS = 0V, VDS = 0V to 80V hꢀ
Effective Output Capacitance (Energy Related)
iꢀ
V
Effective Output Capacitance (Time Related)
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
––– –––
A
MOSFET symbol
97
c
(Body Diode)
Pulsed Source Current
(Body Diode)ꢀd
showing the
integral reverse
G
ISM
––– ––– 390
A
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
––– –––
1.3
57
V
TJ = 25°C, IS = 58A, VGS = 0V g
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
–––
–––
–––
–––
–––
38
46
53
82
2.5
ns
IF = 58A
di/dt = 100A/µs g
69
Qrr
Reverse Recovery Charge
80
nC
120
–––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.143mH
RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use
above this value.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
ISD ≤ 58A, di/dt ≤ 610A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢁ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF/B/S/SL4410ZPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
4.5V
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 175°C
≤
60µs PULSE WIDTH
Tj = 25°C
≤
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 58A
V
= 50V
D
DS
V
= 10V
≤
60µs PULSE WIDTH
GS
T
= 25°C
J
T
= 175°C
J
1
0.1
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
12.0
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I
= 58A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
V
V
V
= 80V
= 40V
= 20V
DS
DS
DS
= C
10.0
8.0
6.0
4.0
2.0
0.0
rss
oss
gd
= C + C
ds
gd
C
iss
C
C
oss
rss
100
0
20
40
60
80
100
1
10
100
Q , Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRF/B/S/SL4410ZPbF
1000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100µsec
1msec
100
10
1
T
= 175°C
J
10msec
DC
T
= 25°C
J
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.1
1
0.0
0.5
1.0
1.5
2.0
2.5
0
1
10
100
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
100
80
60
40
20
0
125
120
115
110
105
100
95
Id = 5mA
Limited By Package
90
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, Case Temperature (°C)
T
, Temperature ( °C )
C
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1000
I
D
900
800
700
600
500
400
300
200
100
0
TOP
6.4A
9.4A
BOTTOM 58A
-10
0
10 20 30 40 50 60 70 80 90 100
Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
V
J
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRF/B/S/SL4410ZPbF
1
D = 0.50
0.20
0.1
0.10
0.05
R1
R2
R2
R1
Ri (°C/W) τi (sec)
τ
J τJ
τ
0.237
0.000178
τ
Cτ
1τ1
Ci= τi/Ri
τ
2τ2
0.02
0.01
0.413
0.003772
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
∆
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
∆Τ
pulsewidth, tav, assuming
Tstart = 150°C.
j = 25°C and
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
TOP
BOTTOM 1.0% Duty Cycle
= 58A
Single Pulse
I
D
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRF/B/S/SL4410ZPbF
20
15
10
5
4.5
4.0
3.5
3.0
2.5
I
= 39A
= 85V
F
V
T
R
= 25°C _____
= 125°C ----------
J
T
J
I
I
I
I
= 150µA
= 250µA
= 1.0mA
= 1.0A
D
D
D
D
2.0
1.5
1.0
0
100
200
300
400
500
600
700
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
di /dt (A/µs)
f
T
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
400
350
300
250
200
150
100
50
20
15
10
5
I
= 39A
= 85V
I
= 58A
= 85V
F
F
V
T
V
T
R
R
= 25°C _____
= 125°C ----------
= 25°C _____
= 125°C ----------
J
J
T
T
J
J
0
0
100
200
300
400
500
600
700
100
200
300
400
500
600
700
di /dt (A/µs)
f
di /dt (A/µs)
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
450
I
= 58A
= 85V
F
V
T
400
350
300
250
200
150
100
50
R
= 25°C _____
= 125°C
J
T
J
----------
0
100
200
300
400
500
600
700
di /dt (A/µs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRF/B/S/SL4410ZPbF
Driver Gate Drive
P.W.
P.W.
D =
Period
D.U.T
Period
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
t
15V
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
20V
0.01
Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
LD
VDS
VGS
90%
+
-
VDD
D.U.T
10%
VDS
VGS
Second Pulse Width < 1µs
Duty Factor < 0.1%
td(off)
td(on)
tf
tr
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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IRF/B/S/SL4410ZPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
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TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
8
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IRF/B/S/SL4410ZPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
25
TO-262 packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
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9
IRF/B/S/SL4410ZPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
25
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
10
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IRF/B/S/SL4410ZPbF
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/07
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11
相关型号：
IRFSL4610TRL
Power Field-Effect Transistor, 73A I(D), 100V, 0.014ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, TO-262, 3 PIN
INFINEON
IRFSL4610TRR
Power Field-Effect Transistor, 73A I(D), 100V, 0.014ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, TO-262, 3 PIN
INFINEON
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