IRISMPS1 [INFINEON]

REFERENCE DESIGN; 参考设计


型号：	IRISMPS1
厂家：	Infineon
描述：	REFERENCE DESIGN 参考设计
文件：	总12页 (文件大小：187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRISMPS1

REFERENCE DESIGN

International Rectifier · 233 Kansas Street El Segundo CA 90245 USA

Technical Specifications

1. DC Input: V=36-72V, I= 1.0A max

2. Inrush Current: 4A max

3. Efficiency: Typical 75% when measured at maximum load high line (73% at low line)

4. Output Characteristics

Load Range

Regulation

Nominal Ouput Voltage

(V)

Min

Max

4.75V ~ 5.25V

5. Turn On Delay: 300msec @ 36V full load

6. Hold-Up Time: 3msec (48Vin Full load) / 2ms (36Vin Full load)

7. Short Circuit Protection:Yes

8: Output Rise Time: 8ms max (10-90%)

9: Over Voltage Protection:Yes

10: Switching Frequency: 85 -425kHz

Relevant Technical Documents

AN1018a - Using the IR40xx Series SMPS ICs

AN1024a - Flyback transformer design for the IR40xx series

IRIS4007(K) - Datasheet

www.irf.com

IRISMPS1

Circuit Description

The IRISMPS2 refererence design is a complete tested power supply circuit. It is designed for a 36-72V

DC line input and will provide a 5V, 5A full load DC output.

The design uses a flyback converter topology, with an IRIS4007K as the main switch and control device.

The initial startup current for the IRIS4007K is provided by a dropper resistor from the DC bus. Once the circuit

is started the Vcc power for the IRIS4007K comes from the bias winding of the main transformer. The primary

current control circuit consists of a current sensing resistor which feeds a voltage proportional to the trans-

former primary current into the feedback (FB) pin of the IRIS4007K. The secondary voltage control loop uses

a zener diode as the reference and an optocoupler to feedback the information across the transformer

isolation boundary back to the control circuit of the IRIS4007K.

Test Circuit Set-up

The circuit is designed for a 36-72V DC line input. To effectively test and evaluate this circuit it ios

recommended that a DC power supply with a 100V range is used that is capable of supplying 5A. The DC

input power is applied to the pins at P1(+) and P4(gnd) marked on the board.

For the output the best load to use is an electronic load which will allow easy changes in the output load,

e.g. something like a Chroma 63102. Another simple alternative is to use a High power resistor for the load.

Circuit Operation

The front end of the circuit consists of an EMI Filter. At power up the DC voltage is applied to the top of the

transformer, and the top of resistor R3. R3 allows about 450uA of quiescent current to flow which charges the

Vcc capacitor C9. When the voltage at the Vcc pin of the IRIS4007K reaches the positive undervoltage lockout

threshold (V_CCUV+) , the IRIS4007K starts to operate and will turn on the internal FET. Now the DC bus voltage

is applied across the transformer primary winding, the FET and the current sense resistor R10. The current

through the transformer primary, the FET and the current sense resistors will start to ramp up. the rate of the

ramp is dependent on the DC bus voltage . The current ramps until the voltage across R10 reaches the Vth1

of the IRIS4007K (0.73V typ). During this time there is no current flowing in either the bias winding or the

output winding, because this is blocked by the diodes D1 and D4 respectively.

At the point when the voltage across R10 reaches Vth1this activates a comparator in the IRIS4007K and

the internal FET is switched off. Now the energy stored in the transformer causes the voltage at the Drain

connected end of the transformer to rise, and as a result the voltage at the bias winding and the output winding

changes from negative to positive. The output rectifiers now conduct and the energy is transferred to the

output and the bias winding. If there is a fixed full current load on the output it will take a number of cycles for

the output voltage to rise to the required level, and also it will take a few cycles for the bias winding to begin

supplying power to the Vcc pin of the IRIS4007K. Until this happens, C9 holds the voltage above the

undervoltage lockout level (Vccuv-) to make sure the circuit does not drop out. During this time the circuit

cannot create enough voltage signal through the delay circuit to activate the quasi-resonant operation, so the

circuit operates with a fixed off time of 50us (this is the pulse raio control mode or PRC mode).

Once the the output capacitors C5/C6/C13 and the Vcc capacitor C6 are fully charged, the complete

quasi-resonant signal is passed through the delay circuit D5/R7/D6 to the feedback (FB) pin. This will give a

voltage above the Vth2 threshold of the IRIS4007K, and this activates the quasi-resonant operation, holding

the internal FET off until all the energy is transferred from the primary side of the transformer to the secondary

and bias outputs. When all the energy is transferred, the quasi-resonant signal at the FB pin will start to fall

until it can no longer supply the 1.35mA required by the IRIS4007K internal latch, and the FET is turned back

www.irf.com

IRISMPS1

on. This is also the lowest point of the resonant voltage at the drain pin of the IRIS4007K, so results in reduced

switching losses.

If the DC input voltage changes but the load stays constant, the primary current ramp will now be steeper

resulting in a shorter ON time, but still the same off time as it still takes the same amount of time to transfer the

same energy to the output. The reduced ON time leads to a higher operating frequency.

If the DC input voltage remains constant, but the load is reduced, the secondary side voltage monitoring

circuit (ISO1A/R5/D3) will see an increase in the voltage, as the circuit is still passing the same energy to the

secondary side, but less current is being drawn. This causes the zener diode D3 to conduct, which leads to a

current flow in the optocoupler ISO1A, which gets passed across the transformer boundary to the phototransistor

part of the optocoupler ISO1B. This in turn creates a voltage drop across R9, generating an offset voltage at the

FB pin which reduces the current required through the current sense resistor R10 needed to reach a voltage

of 0.73typ (Vth1 threshold) at the FB pin, and hence less energy is put into the transformer, reducing both the

ON time and the OFF time.

Circuit Waveforms

The following plots show waveforms taken from the circuit under various stated conditions

Fig 1) Drain (D) voltage of IRIS4007K (CH1) andVcc voltage (CH2) at start-up

Fig 1) shows the drain voltage of the IRIS4007K and the Vcc voltage during start-up with full load output

with a 48VDC input. Note the small dip in the Vcc voltage as the circuit starts to operate, and also the

reflected voltage at the drain due from the output, raising the drain voltage above the DC bus.

www.irf.com

IRISMPS1

Fig 2)Drain (D) voltage of IRIS4007K (CH1) and the FB pin voltage (CH2) at 36VDC in/Full load output

Fig 2) shows the drain voltage and the feedback pin (FB) voltage. In this case the quasi-resonant signal

swings all the way to near zero volts at the drain before the FET is turned on, and hence underthese

conditions the circuit turns the FET on with near zero voltage switching, due to the quasi-resonant switch-

ing. The FB pin signal shows the current ramp when the FET is on(when the drain voltage is low), and the

resonant signal being passed back during the FET off time.

Fig 3) Drain (D) voltage of IRIS4007K (CH1) and the FB pin voltage (CH2) at 72VDC in/Full load output

www.irf.com

IRISMPS1

Fig 3) shows the same waveforms as in fig 2) again with a full load output, but this time with a 72VDC input.

Note that the operating frequency has now increased, and the effect of the quasi-resonant switching is now

more pronounced.This is evident by the quarter sine wave nature of the falling edge of the drain waveform, at

the bottom of which the FET is turned on, ensuring that it is turned on at the minimum possible voltage to

reduce the switching losses. Note also the steeper ramp in the FB pin voltage when the FET is on which results

in a shorter on time.

Fig 4) Drain (D) voltage of IRIS4007K (CH1) and the source(S) pin voltage (CH2) at 48VDC in/Full load

output

Fig 4) shows the waveforms for a 48V input and full load output, but this time it show the Source (S) pin

voltage with the drain voltage showing the effect of the primary current ramp, which is seen as a voltage

generated across the current sense resistor R10. Note that this waveform shows some noise on the source

pin voltage which is smothed out by the RC filter comprising R9 and C12. The intial voltage spike at the

start of the ramp is a result of discharging the quasi-resonant capacitor C5 and the primary winding

capacitance of the transformer.

www.irf.com

IRISMPS1

Fig 5) Drain (D) voltage of IRIS4007K(CH1) and the FB pin voltage(CH2) at 36VDC in/0.1A load output

Fig 5) again shows the drain and FB pin voltages, but this time with a 36VDC and a light load condition

of 0.1A (0.5W output power). Again the quasi-resonant effect can be seen by the quarter wave signal on

the drain pin and also at the FB pin. Note the very short on time, and the fact that the current ramp voltage

at the FB pin does not start from zero, this is due to the offset voltage generated from the voltage feedback

loop across R8.

Fig 6)Drain (D) voltage of IRIS4011 (CH1) and the FB pin voltage (CH2) at 230VAC in/0.1A load output

www.irf.com

IRISMPS1

Fig 6) showsthe same details as in fig 5), but at 72VDC input, in this case you can see the on time is very

short as it takes very little time to get the energy required into the transformer.

Efficiency

Efficiency vs DC Input Voltage

Output Current = 5A

Output Current =0.5A

DC Input Voltage

Efficiency vs Output Power

Vin=36V

Vin=48V

Vin=72V

0.5

2.5

Output Power

www.irf.com

IRISMPS1

IRISMPS1 48/5V 25W Converter B.O.M.

Description

R10

C10

C11

C12

C13

16k 5% 1206 1/8W

75R 5% 0805 1/10W

18k 5% 1206 1/8W

75R 5% 0805 1/10W

0R 5% 0805 1/8W

100R 5% 0805 1/10W

2.0K 5% 0805 1/10W

5.1K 5% 0805 1/10W

680R 5% 0805 1/10W

0.15R 5%1206 1/8W

22uF 100V Electrolytic Capacitor

470pF 0805 50V cermaic capacitor

1nF 200V 0805 ceramic capacitor

0.1uF 100V ceramic capacitor

1000uF 25V Electrolytic Capacitor

330uF 6.3V Electrolytic Capacitor

2200pF 500V ceramic capacitor

10uF 35V Electrolytic Capacitor

0.1uF 50V 0805 ceramic capacitor

0805 capacitor

470pF 0805 50V cermaic capacitor

1000uF 25V Electrolytic Capacitor

30A 30V Schottky Diode

Ultrafast recovery 1A 200V Diode UF1003

3.9V Zener diode 500mW

SM 1N4148 Diode

HS1, HS2 Plug-in heatsinks for TO-200

ISO1

Optocoupler

IR4007K 200V ISMPS IC

Custom - Precision Inc

1.5uH Inductor

www.irf.com

DC Bus

DC in

5Vout

C13

C10

ISO1B

ISO1A

Vcc

gnd out

IRIS4007K

C11

R10

C12

Gnd in

International Rectifier

233 Kansas Street

El Segundo

CA 90245

Size Title

Rev

1.1

IRISMPS1 Reference Design

Filename

Date:

Wednesday, June 06, 2001

Sheet

IRISMPS1

Board Layout - Component Side

www.irf.com

IRISMPS1

Board Layout - Track Side

www.irf.com

IRISMPS1

WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105

http://www.irf.com/ Data and specifications subject to change without notice. 2/13/2001

www.irf.com

IRISMPS1 [INFINEON]

相关型号：

IRISMPS3

IRISMPS5

IRJ01AH250X250X0.5

IRJ04-100ND300X200

IRJ04-250ND300X200

IRK

IRK-71

IRK-91

IRK.105

IRK.136

IRK.142

IRK.162