IRL540NL [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRL540NL |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总10页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-91535
IRL540NS/L
HEXFET® Power MOSFET
l Advanced Process Technology
l Surface Mount (IRL540NS)
l Low-profile through-hole (IRL540NL)
l 175°C Operating Temperature
l Fast Switching
D
VDSS = 100V
RDS(on) = 0.044Ω
G
l Fully Avalanche Rated
Description
ID = 36A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedizeddevicedesignthatHEXFETPowerMOSFETs
arewellknownfor,providesthedesignerwithanextremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
itslowinternalconnectionresistanceandcandissipateup
to 2.0W in a typical surface mount application.
The through-hole version (IRF540NL) is available for low-
profile applications.
2
T O -262
D
Pak
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10Vꢀ
Continuous Drain Current, VGS @ 10Vꢀ
Pulsed Drain Current ꢀ
36
26
A
120
PD @TA = 25°C
PD @TC = 25°C
Power Dissipation
3.8
W
W
Power Dissipation
140
Linear Derating Factor
0.91
± 16
310
W/°C
V
VGS
EAS
IAR
Gate-to-Source Voltage
Single Pulse Avalanche Energyꢀ
Avalanche Current
mJ
A
18
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ꢀ
Operating Junction and
14
mJ
V/ns
5.0
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
–––
Max.
1.1
40
Units
RθJC
RθJA
°C/W
–––
5/13/98
IRL540NS/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
100 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C Reference to 25°C, ID = 1mAꢀ
––– ––– 0.044
––– ––– 0.053
––– ––– 0.063
VGS = 10V, ID = 18A
VGS = 5.0V, ID = 18A
VGS = 4.0V, ID = 15A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 18Aꢀ
VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 150°C
VGS = 16V
RDS(on)
Static Drain-to-Source On-Resistance
Ω
VGS(th)
gfs
Gate Threshold Voltage
1.0
14
––– 2.0
––– –––
V
S
Forward Transconductance
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
––– ––– 74
––– ––– 9.4
––– ––– 38
A
IDSS
IGSS
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA
VGS = -16V
Qg
ID = 18A
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 80V
VGS = 5.0V, See Fig. 6 and 13 ꢀ
–––
–––
–––
–––
11 –––
81 –––
39 –––
62 –––
VDD = 50V
ID = 18A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 5.0Ω, VGS = 5.0V
RD = 2.7Ω, See Fig. 10 ꢀ
Between lead,
LS
Internal Source Inductance
7.5
–––
–––
nH
pF
and center of die contact
VGS = 0V
Ciss
Coss
Crss
Input Capacitance
––– 1800 –––
––– 350 –––
––– 170 –––
Output Capacitance
VDS = 25V
Reverse Transfer Capacitance
ƒ = 1.0MHz, See Fig. 5ꢀ
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
IS
36
––– –––
A
G
ISM
Pulsed Source Current
(Body Diode) ꢀ
integral reverse
––– ––– 120
S
p-n junction diode.
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 190 290
––– 1.1 1.7
V
TJ = 25°C, IS = 18A, VGS = 0V ꢀ
ns
TJ = 25°C, IF = 18A
Qrr
ton
µC di/dt = 100A/µs ꢀ
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
ꢀ Uses IRL540N data and test conditions
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 1.9mH
RG = 25Ω, IAS = 18A. (See Figure 12)
ISD ≤ 18A, di/dt ≤ 180A/µs, VDD ≤ V(BR)DSS
,
TJ ≤ 175°C
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended soldering techniques refer to application note #AN-994.
IRL540NS/L
1000
100
10
1000
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
8.0V
6.0V
4.0V
3.0V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
2.5V
20µs PULSE WIDTH
20µs PULSE WIDTH
T
= 175°C
TJ = 25°C
J
1
1
A
100
A
0.1
1
10
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
D S
D S
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
= 30A
D
100
10
1
TJ = 25°C
TJ = 175°C
VD S = 50V
20µs PULSE WIDTH
V
= 10V
GS
A
A
-60 -40 -20
0
20
40
60
80 100 120 140 160 180
2
4
6
8 10
T
J
, Junction Temperature (°C)
VG S , Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance
Fig 3. Typical Transfer Characteristics
Vs. Temperature
IRL540NS/L
3000
15
12
9
V
C
C
C
= 0V,
= C
= C
f = 1MHz
I
= 18A
D
GS
iss
rss
oss
+ C
gs
gd
+ C
,
C
SHORTED
ds
gd
V
V
V
= 80V
= 50V
= 20V
D S
D S
D S
= C
ds
gd
C
iss
2000
1000
0
6
C
C
oss
rss
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
1
10
100
0
20
Q
40
60
80
100
V
, Drain-to-Source Voltage (V)
, Total Gate Charge (nC)
D S
G
Fig 5. Typical Capacitance Vs.
Fig 6. Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
1000
1000
100
10
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
100
10
1
10µs
T
= 175°C
J
100µs
T
= 25°C
J
1ms
T
T
= 25°C
= 175°C
C
J
10ms
V
= 0V
Single Pulse
GS
1.6
A
1
A
1000
0.4
0.6
0.8
1.0
1.2
1.4
1.8
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
S D
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
IRL540NS/L
RD
40
30
20
10
0
VDS
VGS
D.U.T.
RG
+VDD
-
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
T , Case Temperature ( C)
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
1
D = 0.50
0.20
P
DM
0.10
0.05
0.1
t
1
0.02
0.01
t
2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D =
t / t
1 2
2. Peak T = P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRL540NS/L
800
600
400
200
0
I
D
TOP
7.3A
13A
18A
15V
BOTTOM
DRIVER
L
V
D S
D.U .T
R
G
+
V
DD
-
I
A
AS
10V
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
A
25
50
75
100
125
150
175
V
(BR)DSS
Starting T , Junction Temperature (°C)
J
t
p
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Fig 12b. Unclamped Inductive Waveforms
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
Q
G
+
5.0 V
V
DS
D.U.T.
-
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
IRL540NS/L
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
IRL540NS/L
D2Pak Package Outline
10.54 (.415)
10.29 (.405)
10.16 (.400)
REF.
- B -
1.32 (.052)
4.69 (.185)
4.20 (.165)
1.40 (.055)
- A -
M AX.
1.22 (.048)
2
6.47 (.255)
6.18 (.243)
1.78 (.070)
1.27 (.050)
15.49 (.610)
14.73 (.580)
2.79 (.110)
2.29 (.090)
1
3
2.61 (.103)
2.32 (.091)
5.28 (.208)
4.78 (.188)
8.89 (.350)
REF.
1.40 (.055)
1.14 (.045)
1.39 (.055)
1.14 (.045)
3X
0.55 (.022)
0.46 (.018)
0.93 (.037)
0.69 (.027)
3X
5.08 (.200)
0.25 (.010)
M
B A M
MINIMUM RECOM MENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
LEAD ASSIGNMENTS
1 - GATE
NO TES:
1
2
3
4
DIM ENSIONS AFTER SO LDER DIP.
17.78 (.700)
2 - DRAIN
3 - SOURCE
DIM ENSIONING & TOLERANCING PER ANSI Y14.5M , 1982.
CONTROLLING DIM ENSION : INCH.
HEATSINK & LEAD DIM ENSIONS DO NOT INCLUDE BURRS.
3.81 (.150)
2.54 (.100)
2.08 (.082)
2X
2X
Part Marking Information
D2Pak
A
INTERNATIONAL
RECTIFIER
LOGO
PART NUM BER
F530S
9246
1M
DATE CODE
(YYW W )
9B
ASSEM BLY
YY
=
YEAR
= W EEK
LOT CODE
W W
IRL540NS/L
Package Outline
TO-262 Outline
Part Marking Information
TO-262
IRL540NS/L
Tape & Reel Information
D2Pak
TRR
1 .6 0 (.063 )
1 .5 0 (.059 )
1.60 (.06 3)
1.50 (.05 9)
4.10 (.16 1)
3.90 (.15 3)
0.3 68 (.0145)
0.3 42 (.0135)
FEED DIRECTION
1.85 (.07 3)
11.60 (.457)
11.40 (.449)
1.65 (.06 5)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.42 9)
10.70 (.42 1)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
M A X.
60.00 (2.362)
MIN .
30.40 (1.197)
M AX.
NO TES :
1. CO M FO RM S TO EIA-418.
2. CO N TR O LLIN G D IM ENSIO N : M ILLIM ET ER .
3. DIM ENSIO N MEASUR ED
26.40 (1.039)
24.40 (.961)
4
@ HU B.
3
4. INC LUD ES FLAN G E D ISTO R TIO N
@
O UTER EDG E.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
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IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/
Data and specifications subject to change without notice.
5/98
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