IRLU120N [INFINEON]
Power MOSFET(Vdss=100V, Rds(on)=0.185ohm, Id=10A); 功率MOSFET （ VDSS = 100V ， RDS（ON） = 0.185ohm ，ID = 10A）
| 型号： | IRLU120N |
| 厂家： | 
Infineon |
| 描述： | Power MOSFET(Vdss=100V, Rds(on)=0.185ohm, Id=10A) |
| 文件： | 总10页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 91541B
IRLR/U120N
HEXFET® Power MOSFET
Surface Mount (IRLR120N)
Straight Lead (IRLU120N)
Advanced Process Technology
Fast Switching
D
VDSS = 100V
RDS(on) = 0.185Ω
Fully Avalanche Rated
G
ID = 10A
Description
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
D -PAK
TO -252AA
I-PAK
TO -251AA
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
10
7.0
35
A
PD @TC = 25°C
Power Dissipation
48
W
W/°C
V
Linear Derating Factor
0.32
± 16
85
VGS
EAS
IAR
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
mJ
A
6.0
4.8
5.0
EAR
dv/dt
TJ
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
mJ
V/ns
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
–––
–––
Max.
3.1
50
Units
°C/W
1
RθJC
RθJA
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
RθJA
110
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5/11/98
IRLR/U120N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
100 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.12 ––– V/°C Reference to 25°C, ID = 1mA
––– ––– 0.185
––– ––– 0.225
––– ––– 0.265
VGS = 10V, ID = 6.0A
RDS(on)
Static Drain-to-Source On-Resistance
W
VGS = 5.0V, ID = 6.0A
VGS = 4.0V, ID = 5.0A
VDS = VGS, ID = 250µA
VDS = 25V, ID = 6.0A
VGS(th)
gfs
Gate Threshold Voltage
1.0
3.1
––– 2.0
––– –––
V
S
Forward Transconductance
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
––– ––– 20
––– ––– 4.6
––– ––– 10
VDS = 100V, VGS = 0V
VDS = 80V, VGS = 0V, TJ = 150°C
IDSS
IGSS
Drain-to-Source Leakage Current
µA
nA
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
VGS = 16V
VGS = -16V
ID = 6.0A
Qg
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 80V
VGS = 5.0V, See Fig. 6 and 13
–––
–––
–––
–––
4.0 –––
35 –––
23 –––
22 –––
VDD = 50V
ID = 6.0A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
RG = 11Ω, VGS = 5.0V
RD = 8.2Ω, See Fig. 10
Between lead,
D
LD
LS
Internal Drain Inductance
Internal Source Inductance
–––
4.5
–––
nH
6mm (0.25in.)
G
from package
––– 7.5 –––
––– 440 –––
and center of die contact
VGS = 0V
S
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
–––
–––
97 –––
50 –––
pF
VDS = 25V
Reverse Transfer Capacitance
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
Parameter
Continuous Source Current
(Body Diode)
Min. Typ. Max. Units
Conditions
MOSFET symbol
showing the
D
IS
10
35
––– –––
––– –––
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
S
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 110 160
––– 410 620
V
TJ = 25°C, IS = 6.0A, VGS = 0V
TJ = 25°C, IF =6.0A
ns
Qrr
ton
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 4.7mH
RG = 25Ω, IAS = 6.0A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
This is applied for I-PAK, LS of D-PAK is measured between lead and
center of die contact
ISD ≤ 6.0A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS
,
Uses IRL520N data and test conditions.
TJ ≤ 175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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IRLR/U120N
100
10
1
100
10
1
VGS
15V
VGS
15V
TOP
TOP
12V
12V
10V
10V
8.0V
6.0V
4.0V
3.0V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
BOTTOM 2.5V
2.5V
2.5V
20µs PULSE W IDTH
20µs PULSE W IDTH
T
= 25°C
J
T
= 175°C
J
0.1
0.1
A
100
A
0.1
1
10
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
D S
D S
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
I
= 10A
D
TJ = 25°C
TJ = 175°C
10
1
VDS = 50V
20µs PU LSE W ID TH
V
= 10V
GS
0.1
A
A
-60 -40 -20
0
20
40
60
80 100 120 140 160 180
2
4
6
8
10
and
T
J
, Junction Tem perature (°C)
VG S , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRLR/U120N
800
15
12
9
V
= 0V,
f = 1M Hz
I
= 6.0A
D
GS
C
C
C
= C
= C
= C
+ C
+ C
,
C
SHORTED
iss
gs
gd
ds
gd
ds
V
V
V
= 80V
= 50V
= 20V
DS
DS
DS
rss
oss
gd
600
400
200
0
C
iss
C
C
oss
rss
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
A
1
10
100
0
5
10
15
20
25
V
, Drain-to-Source Voltage (V)
Q
, Total Gate Charge (nC)
DS
G
Fig 5. Typical Capacitance Vs.
Fig 6. Typical Gate Charge Vs.
Drain-to-Source Voltage
Gate-to-Source Voltage
100
10
1
100
10
1
OPERATION IN THIS AREA LIM ITED
BY R
DS(on)
10µs
T
= 175°C
J
100µs
T
= 25°C
J
1m s
10m s
T
T
= 25°C
= 175°C
C
J
Single Pulse
V
= 0V
G S
A
0.1
0.1
A
0.4
0.6
0.8
1.0
1.2
1.4
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
4
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IRLR/U120N
10
8
RD
VDS
VGS
D.U.T.
RG
+VDD
-
6
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
4
Fig 10a. Switching Time Test Circuit
2
V
DS
90%
A
175
0
25
50
75
100
125
150
T
, Case Tem perature (°C)
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
t
t
r
t
t
f
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
10
D = 0.50
0.20
1
0.10
0.05
P
0.02
0.01
DM
SINGLE PULSE
(THERMAL RESPONSE)
0.1
t
1
t
2
Notes:
1. Duty factor D = t / t
1
2
2. Peak T = P
x Z
+ T
thJC C
J
DM
0.01
0.00001
0.0001
0.001
0.01
0.1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U120N
200
160
120
80
I
D
TOP
2.4A
4.2A
6.0A
15V
BOTTOM
DRIVER
L
V
D S
D.U .T
R
G
+
V
D D
-
I
A
AS
10V
0.01
Ω
t
p
40
Fig 12a. Unclamped Inductive Test Circuit
0
A
175
25
50
75
100
125
150
Starting T , Junction Tem perature (°C)
V
(BR )D SS
J
t
p
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I
AS
Current Regulator
Fig 12b. Unclamped Inductive Waveforms
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
Q
G
+
5.0 V
V
DS
D.U.T.
-
Q
Q
GD
GS
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRLR/U120N
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
D.U.T
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRLR/U120N
Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
- A -
1.27 (.050)
5.46 (.215)
0.58 (.023)
0.46 (.018)
0.88 (.035)
5.21 (.205)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
10.42 (.410)
9.40 (.370)
1.02 (.040)
1.64 (.025)
LEAD ASSIG NM ENTS
1 - GATE
1
2
3
0.51 (.020)
MIN.
2 - DRA IN
- B -
3 - SOURCE
4 - DRA IN
1.52 (.060)
1.15 (.045)
0.89 (.035)
0.64 (.025)
3X
0.58 (.023)
0.46 (.018)
1.14 (.045)
0.76 (.030)
2X
0.25 (.010)
M
A M B
NOTES:
2.28 (.090)
1
2
3
4
DIMENSIONING & TOLERANCING PER ANSI Y 14.5M, 1982.
CONTROLLING DIMENSION : INCH.
4.57 (.180)
CONFORMS TO JEDE C OUTLINE TO-252AA.
DIMENSIONS SHOW N ARE BEFORE SOLDER DIP,
SOLDER DIP M AX. +0.16 (.006).
Part Marking Information
TO-252AA (D-PARK)
EXAMPLE : THIS IS AN IRFR120
W ITH ASSEM BLY
A
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE 9U1P
FIRST PORTION
OF PART NUMBER
IRFR
120
1P
9U
ASSEMBLY
SECOND PORTION
OF PART NUM BER
LOT CODE
8
www.irf.com
IRLR/U120N
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
- A -
0.58 (.023)
0.46 (.018)
1.27 (.050)
5.46 (.215)
0.88 (.035)
5.21 (.205)
LEAD ASSIGNM ENTS
4
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
- B -
NOTES:
1
2
3
4
DIM ENS IONING & TOLERANCING PER ANSI Y14.5M , 1982.
CONTROLLING DIMENSION : INCH.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
CONFORMS TO JEDEC OUTLINE TO-252AA.
DIM ENS IONS SHOW N ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
1.14 (.045)
0.76 (.030)
1.14 (.045)
0.89 (.035)
3X
0.89 (.035)
0.64 (.025)
3X
0.25 (.010)
M
A M B
0.58 (.023)
0.46 (.018)
2.28 (.090)
2X
Part Marking Information
TO-251AA (I-PARK)
EXAM PLE : TH IS IS AN IR FU 120
W ITH ASSEM BLY
INTE RN ATION AL
R EC TIFIER
LO GO
LO T C OD E 9U 1P
FIR ST PO RTION
OF PAR T N U M BER
IR FU
120
1P
9U
SEC O N D PO R TIO N
O F PAR T N U M B ER
AS SEM BLY
LOT
C O D E
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9
IRLR/U120N
Tape & Reel Information
TO-252AA
TR
TR L
TRR
16.3 ( .641 )
15.7 ( .619 )
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIR ECTIO N
FEED DIR ECTIO N
N O TES :
1. C O NTRO LLING D IM EN SIO N : M ILLIM ETER.
2. ALL D IM EN SIO N S ARE SH O W N IN M ILLIM ETERS ( INC HES ).
3. O U TLINE C O N FO RM S TO EIA-481 & EIA-541.
13 INC H
16 m m
NO TES :
1. O U TLINE CO N FO RM S TO EIA-481.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-chome, Toshima-ku, Tokyo Japan Tel: 81 33 983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 16907 Tel: 65 221 8371
Data and specifications subject to change without notice.
5/98
10
www.irf.com
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