IRLU8721_技术文档

PD - 96119

IRLR8721PbF

IRLU8721PbF

HEXFET^®Power MOSFET

Applications

V_DSSR_DS(on)max

Qg

l High Frequency Synchronous Buck

Converters for Computer Processor Power

l High Frequency Isolated DC-DC

Converters with Synchronous Rectification

for Telecom and Industrial Use

l Lead-Free

8.4m

30V

8.5nC

D

S

D

G

Benefits

l Very Low RDS(on) at 4.5V V_GS

l Ultra-Low Gate Impedance

l Fully Characterized Avalanche Voltage

and Current

D-Pak

IRLR8721PbF

I-Pak

IRLU8721PbF

G

D

S

Gate

Drain

Source

Absolute Maximum Ratings

Parameter

Max.

30

Units

V

V_DS

Drain-to-Source Voltage

V

Gate-to-Source Voltage

± 20

65

GS

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

I

@ T_C= 25°C

@ T_C= 100°C

D

46

A

260

65

DM

P

@T_C= 25°C

@T_C= 100°C

Maximum Power Dissipation

D

W

33

Linear Derating Factor

Operating Junction and

0.43

-55 to + 175

W/°C

°C

T

J

T

Storage Temperature Range

STG

Thermal Resistance

Parameter

Junction-to-Case

Typ.

Max.

2.3

Units

R_θJC

R_θJA

–––

Junction-to-Ambient (PCB Mount)

50

°C/W

Junction-to-Ambient

110

Notes through ꢀ are on page 11

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1

08/10/07

IRLR/U8721PbF

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Drain-to-Source Breakdown Voltage

Min. Typ. Max. Units

Conditions

V_GS= 0V, I_D= 250µA

BV_DSS

30

–––

V

∆ΒV_DSS/∆T_J

R_DS(on)

Breakdown Voltage Temp. Coefficient –––

21

––– mV/°C Reference to 25°C, I_D= 1mA

Ω

m

Static Drain-to-Source On-Resistance

–––

1.35

–––

46

6.3

8.4

V_GS= 10V, I_D= 25A

10.1 11.8

2.35

––– mV/°C

V

_GS= 4.5V, I_D= 20A

_DS= V_GS, I_D= 25µA

V_GS(th)

∆V_GS(th)

I_DSS

Gate Threshold Voltage

1.9

-6.8

–––

8.5

1.9

1.2

3.4

2.0

4.6

7.9

2.3

8.8

30

V

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

1.0

150

100

-100

–––

13

µA

V

_DS= 24V, V_GS= 0V

V_DS= 24V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

nA V_GS= 20V

V_GS= -20V

gfs

Q_g

S

V_DS= 15V, I_D= 20A

–––

Q_gs1

Q_gs2

Q_gd

Q_godr

Q_sw

Q_oss

R_G

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

–––

3.8

V

_DS= 15V

_GS= 4.5V

nC

V

I_D= 20A

Gate Charge Overdrive

Switch Charge (Q_gs2+ Q_gd)

See Fig. 16

Output Charge

nC

V_DS= 16V, V_GS= 0V

Ω

Gate Resistance

Turn-On Delay Time

Rise Time

t_d(on)

t_r

t_d(off)

t_f

–––

V

_DD= 15V, V_GS= 4.5V

I_D= 20A

Turn-Off Delay Time

Fall Time

9.4

6.5

ns

R_G= 1.8Ω

See Fig. 14

V_GS= 0V

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 1030 –––

–––

350

110

–––

pF V_DS= 15V

ƒ = 1.0MHz

Avalanche Characteristics

Parameter

Typ.

–––

Max.

Units

mJ

A

Single Pulse Avalanche Energy

E_AS

I_AR

93

20

Avalanche Current

Repetitive Avalanche Energy

E_AR

6.5

mJ

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

65

I_S

Continuous Source Current

–––

A

D

S

(Body Diode)

Pulsed Source Current

showing the

integral reverse

I_SM

G

–––

260

(Body Diode)

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

–––

17

1.0

26

36

V

T = 25°C, I = 20A, V = 0V

J S GS

Reverse Recovery Time

Reverse Recovery Charge

Forward Turn-On Time

ns T = 25°C, I = 20A, V_DD= 15V

J F

Q_rr

t_on

di/dt = 300A/µs

24

nC

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

2

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IRLR/U8721PbF

1000

100

10

1000

100

10

VGS

10V

VGS

10V

TOP

8.0V

5.0V

4.5V

4.0V

3.5V

3.0V

2.7V

8.0V

5.0V

4.5V

4.0V

3.5V

3.0V

BOTTOM

2.7V

1

2.7V

60µs PULSE WIDTH

Tj = 175°C

≤

60µs PULSE WIDTH

Tj = 25°C

≤

0.1

1

0.1

1

10

100

0.1

1

10

100

V

, Drain-to-Source Voltage (V)

V

, Drain-to-Source Voltage (V)

DS

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

2.0

I

= 25A

D

V

= 10V

GS

100

10

1

T

= 175°C

J

1.5

1.0

0.5

T

= 25°C

V

J

= 15V

DS

≤60µs PULSE WIDTH

0.1

0

2

4

6

8

10

-60 -40 -20 0 20 40 60 80 100120140160180

, Junction Temperature (°C)

T

J

V

, Gate-to-Source Voltage (V)

GS

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

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3

IRLR/U8721PbF

10000

5.0

4.0

3.0

2.0

1.0

0.0

V

= 0V,

= C

f = 1 MHZ

GS

I

= 20A

V

= 24V

= 15V

= 6.0V

D

C

+ C , C

SHORTED

DS

iss

gs

gd

ds

= C

rss

oss

gd

= C + C

ds

gd

C

1000

100

10

iss

C

oss

C

rss

1

10

, Drain-to-Source Voltage (V)

100

0

2

4

6

8

10

V

Q , Total Gate Charge (nC)

DS

G

Fig 6. Typical Gate Charge vs.

Fig 5. Typical Capacitance vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000

100

10

1000

100

10

OPERATION IN THIS AREA

LIMITED BY R

(on)

DS

100µsec

1msec

T

= 175°C

J

T

= 25°C

J

10msec

1

Tc = 25°C

Tj = 175°C

Single Pulse

V

= 0V

GS

0.1

0.0

0.5

1.0

1.5

2.0

0

1

10

100

V

, Source-to-Drain Voltage (V)

V

, Drain-to-Source Voltage (V)

SD

DS

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

4

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IRLR/U8721PbF

70

60

50

40

30

20

10

0

2.5

2.0

1.5

1.0

0.5

Limited By Package

I

= 25µA

D

25

50

75

100

125

150

175

-75 -50 -25

0

25 50 75 100 125 150175 200

T

, Case Temperature (°C)

T , Temperature ( °C )

C

J

Fig 9. Maximum Drain Current vs.

Fig 10. Threshold Voltage vs. Temperature

Case Temperature

10

D = 0.50

1

0.20

0.10

0.05

R₁

R₂

R₃

Ri (°C/W) τi (sec)

0.3501 0.000072

0.1

0.01

τ

0.02

0.01

^Jτ_J

τ

^Cτ

τ

¹τ₁

τ

²τ₂

³τ₃

1.1877 0.001239

0.7635 0.010527

Ci= τi/Ri

/

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

SINGLE PULSE

( THERMAL RESPONSE )

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

t

, Rectangular Pulse Duration (sec)

1

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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5

IRLR/U8721PbF

400

350

300

250

200

150

100

50

15V

I

D

TOP

1.1A

1.4A

BOTTOM 20A

DRIVER

L

V

DS

D.U.T

R

G

+

-

V

DD

I

A

AS

20V

t

0.01

Ω

p

Fig 12a. Unclamped Inductive Test Circuit

V

(BR)DSS

t

p

0

25

50

75

100

125

150

175

Starting T , Junction Temperature (°C)

J

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

I

AS

R_D

V_DS

Fig 12b. Unclamped Inductive Waveforms

V_GS

D.U.T.

R_G

⁺V_DD

Current Regulator

Same Type as D.U.T.

-

V_GS

PulseWidth ≤ 1 µs

Duty Factor ≤ 0.1 %

50KΩ

.2µF

12V

.3µF

Fig 14a. Switching Time Test Circuit

+

V

DS

D.U.T.

-

90%

V

GS

3mA

10%

V

GS

I

D

G

t

r

t

f

d(on)

d(off)

Current Sampling Resistors

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

6

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IRLR/U8721PbF

Driver Gate Drive

P.W.

Period

D.U.T

Period

D =

P.W.

+

*

=10V

V

GS

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

-

D.U.T. I Waveform

SD

+

-

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

-

+

D.U.T. V Waveform

DS

Diode Recovery

dv/dt

V

DD

V_DD

Re-Applied

Voltage

• dv/dt controlled by R_G

R_G

+

-

Body Diode

Forward Drop

• Driver same type as D.U.T.

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

I

SD

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

Id

Vds

Vgs

Vgs(th)

Qgs1

Qgs2

Qgodr

Qgd

Fig 16. Gate Charge Waveform

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7

IRLR/U8721PbF

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

loss

conduction

drive

output

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

g

⎛

⎜

Q_oss

⎞

⎠

P_loss= P_conduction+ P_switching+ P_drive+ P_output

+

×V × f + Q × V × f

(

)

in

rr

in

⎝ 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

P

= I ²× R_{ds(on )}

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

⎛

Q_gd

i_g

⎞

Q_gs2

i_g

⎞

⎟

⎜

⎟

⎜

+ I ×

× V × f + I ×

× V × f

in

⎝

⎠

⎝

⎠

+ Q × V × f

(

)

g

⎛ Q_oss

⎞

⎠

+

×V × f

in

⎝

2

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFETdata sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

8

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IRLR/U8721PbF

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com

9

IRLR/U8721PbF

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

10

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IRLR/U8721PbF

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

TR

TRL

TRR

16.3 ( .641 )

15.7 ( .619 )

16.3 ( .641 )

15.7 ( .619 )

12.1 ( .476 )

11.9 ( .469 )

8.1 ( .318 )

7.9 ( .312 )

FEED DIRECTION

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).

3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Notes:

Calculated continuous current based on maximum allowable

Repetitive rating; pulse width limited by

max. junction temperature.

junction temperature. Package limitation current is 50A.

Starting T_J= 25°C, L = 0.47mH

R_G= 25Ω, I_AS= 20A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to

application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.08/2007

www.irf.com

11


型号：	IRLU8721
厂家：	Infineon
描述：	Power Field-Effect Transistor, 65A I(D), 30V, 0.0084ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-251AA, PLASTIC, IPAK-3 开关脉冲晶体管
文件：	总11页 (文件大小：364K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRLU8721 [INFINEON]

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