IRS21303DPBF [INFINEON]
3-PHASE BRIDGE DRIVER; 3相桥式驱动器
| 型号： | IRS21303DPBF |
| 厂家： | 
Infineon |
| 描述： | 3-PHASE BRIDGE DRIVER |
| 文件： | 总23页 (文件大小：537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Data Sheet No. PD60256 revA
IRS2130D/IRS21303D/IRS2132D
3-PHASE BRIDGE DRIVER
Product Summary
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
Fully operational to +600 V
VOFFSET
600 V max.
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for all channels
Over-current shutdown turns off all six drivers
Three Independent half-bridge drivers
Matched propagation delay for all channels
2.5 V logic compatible
Outputs out of phase with inputs
Cross-conduction prevention logic
All parts are LEAD-FREE
IO+/- (min.)
VOUT
200 mA / 420 mA
10 V – 20 V (IRS213(0,2)D)
13 V – 20 V (IRS21303D)
500 ns
ton/off (typ.)
Deadtime (typ.)
2.0 µs (IRS2130D)
0.7 µs (IRS213(2,03)D)
Applications:
*Motor Control
*Air Conditioners/ Washing Machines
*General Purpose Inverters
Integrated bootstrap diode function
*Micro/Mini Inverter Drives
Description
Packages
The IRS213(0, 03, 2)D are high voltage, high speed
power MOSFET and IGBT drivers with three independent
high and low side referenced output channels. Proprietary
HVIC technology enables ruggedized monolithic
construction. Logic inputs are compatible with CMOS or
LSTTL outputs, down to 2.5 V logic. A ground-referenced
operational amplifier provides analog feedback of bridge
current via an external current sense resistor. A current trip
function which terminates all six outputs is also derived from
this resistor. An open drain FAULT signal indicates if an
over-current or undervoltage shutdown has occurred. The
output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. Propagation
delays are matched to simplify use at high frequencies. The
floating channels can be used to drive N-channel power
28-Lead SOIC
28-Lead PDIP
44-Lead PLCC w/o 12 Leads
MOSFETs or IGBTs in the high side configuration which operates up to 600 V.
Typical Connection
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions. Zener clamps are included between VCC & VSO (25 V), VCC
VSS (20V), and VBx & VSx (20 V).
&
Symbol
Definition
Min.
Max.
Units
VB1,2,3
High side floating supply voltage
-0.3
625
VS1,2,3
VHO1,2,3
VCC
High side floating offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Logic ground
VB1,2,3 - 20
VS1,2,3 - 0.3
-0.3
VB1,2,3 + 0.3
VB1,2,3 + 0.3
25
VSS
VCC - 20
-0.3
VCC + 0.3
VCC + 0.3
VLO1,2,3
Low side output voltage
V
(VSS + 15) or
(VCC + 0.3),
whichever is
lower
Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP)
VIN
VSS -0.3
VFLT
VCAO
VCA-
FAULT output voltage
VSS -0.3
VCC +0.3
VCC +0.3
VCC +0.3
50
Operational amplifier output voltage
Operational amplifier inverting input voltage
Allowable offset supply voltage transient
VSS -0.3
VSS -0.3
—
dVS/dt
V/ns
W
(28 lead PDIP)
—
1.5
PD
Package power dissipation @ TA ≤ +25 °C
(28 lead SOIC)
(44 lead PLCC)
(28 lead PDIP)
(28 lead SOIC)
(44 lead PLCC)
—
1.6
—
2.0
—
83
Rth,JA
Thermal resistance, junction to ambient
°C/W
°C
—
78
—
63
TJ
TS
TL
Junction temperature
—
150
Storage temperature
-55
150
Lead temperature (soldering, 10 seconds)
—
300
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the
recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested
with all supplies biased at a 15 V differential.
Symbol
Definition
Min.
Max.
Units
IRS213(0,2)D
IRS21303D
VS1,2,3 +10
VB1,2,3
High side floating supply voltage
VS1,2,3 +20
V
S1,2,3 +13
Note 1
VS1,2,3
High side floating offset voltage
High side floating output voltage
600
VHO1,2,3
VS1,2,3
10
13
VB1,2,3
IRS213(0,2)D
IRS21303D
VCC
Low side and logic fixed supply voltage
20
V
VSS
VLO1,2,3
VIN
Logic ground
-5
5
Low side output voltage
0
VCC
Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP)
VSS
VSS
VSS
VSS
-40
VSS + 5
VCC
FAULT output voltage
VFLT
VCAO
VCA-
TA
Operational amplifier output voltage
Operational amplifier inverting input voltage
Ambient temperature
VSS + 5
VSS + 5
125
°C
Note 1: Logic operational for VS of (VSO - 8 V) to (VSO + 600 V). Logic state held for VS of (VSO - 8 V) to (VSO – VBS .
)
(Please refer to the Design Tip DT97-3 for more details).
Note 2: The CAO pin and all input pins (except CA-) are internally clamped with a 5.2 V zener diode.
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3
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are
referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
VIH
VIL
Logic “0” input voltage (OUT = LO)
Logic “1” input voltage (OUT = HI)
ITRIP input positive going threshold
2.2
—
—
—
—
V
0.8
VIT,TH+
400 490 580
mV
V
VOH
VOL
ILK
High level output voltage, VBIAS - VO
Low level output voltage, VO
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
—
—
—
—
—
—
—
—
30
4
1
400
50
70
6
VIN = 0 V, Io= 20 mA
mV VIN = 5 V, Io= 20 mA
VB = VS = 600 V
µA
IQBS
IQCC
IIN+
IIN-
IITRIP+
IITRIP-
VIN = 0 V
mA
µA
nA
Logic “1” input bias current (OUT = HI)
Logic “0” input bias current (OUT = LO)
“High” ITRIP bias current
—
—
—
—
300 400
220 300
5
VIN = 5 V
ITRIP = 5 V
ITRIP = 0 V
100
10
“Low” ITRIP bias current
—
VBS supply undervoltage
positive going threshold
IRS213(0,2)D 7.5 8.35 9.2
IRS21303D 11 13
IRS213(0,2)D 7.1 7.95 8.8
VBSUV+
VBSUV-
VCCUV+
VCCUV-
VCCUVH
—
VBS supply undervoltage
negative going threshold
IRS21303D
IRS213(0,2)D 8.3
9
—
9
11
9.7
13
9.4
11
—
VCC supply undervoltage
positive going threshold
IRS21303D
IRS213(0,2)D
IRS21303D
IRS213(0,2)D
IRS21303D
IRS213(0,2)D
IRS21303D
11
8
9
—
—
—
—
8.7
—
0.3
2
V
VCC supply undervoltage
negative going threshold
Hysteresis
—
—
0.4
2
VBSUVH
Ron, FLT
IO+
Hysteresis
FAULT low on-resistance
—
55
75
—
Ω
VO = 0 V, VIN = 0 V
PW ≤ 10 µs
VO = 15 V, VIN = 5 V
PW ≤ 10 µs
Output high short circuit pulsed current
Output low short circuit pulsed current
200 250
420 500
mA
IO-
—
RBS
VOS
ICA-
Integrated bootstrap diode resistance
Operational amplifier input offset voltage
CA- input bias current
—
—
—
200
—
—
—
10
50
Ω
mV
nA
VSO = VCA- = 0.2 V
VCA- = 2.5 V
Operational amplifier common mode
rejection ratio
Operational amplifier power supply
rejection ratio
VSO = VCA- = 0.1 V &
1.1 V
VSO = VCA- = 0.2 V
VCC = 10 V & 20 V
CMRR
PSRR
TBD 80
TBD 75
—
—
dB
Operational amplifier high level output
voltage
Operational amplifier low level output
voltage
VOH,AMP
VOL,AMP
4.9
—
5.2
—
5.4
30
V
VCA- = 0 V, VSO =1 V
VCA- = 1 V, VSO =0 V
mV
Note: Please refer to Feature Description section for integrated bootstrap functionality information.
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Static Electrical Characteristics - (Continued)
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are
referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
VCA- = 0 V, VSO =1 V
ISRC,AMP
Operational amplifier output source current
4
1
7
2.1
10
4
—
—
—
—
VCAO = 4 V
VCA- = 1 V, VSO =0 V
VCAO = 2 V
VCA- = 0 V, VSO =5 V
VCAO = 0 V
ISNK,AMP
IO+,AMP
IO-,AMP
Operational amplifier output sink current
mA
Operational amplifier output high short circuit
current
Operational amplifier output low short circuit
current
—
—
VCA- = 5 V, VSO =0 V
VCAO = 5 V
Dynamic Electrical Characteristics
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
ton
toff
t r
Turn-on propagation delay
400 500 700
400 500 700
Turn-off propagation delay
Turn-on rise time
—
—
80
35
125
55
VS1,2,3 = 0 V to 600 V
tf
Turn-off fall time
titrip
tbl
ITRIP to output shutdown propagation delay
ITRIP blanking time
400 660 920
400
350 550 870
325
—
—
ns
ITRIP to FAULT indication delay
tflt
tflt, in
Input filter time (all six inputs)
—
—
LIN1,2,3 to FAULT clear time IRS213(0,2)D
LIN1,2,3 & HIN1,2,3 to FAULT clear time
IRS21303D
tfltclr
DT
5300 8500 13700
1300 2000 3100
IRS2130D
Deadtime
IRS213(2,03)D 500 700 1100
SR+
SR-
Operational amplifier slew rate (+)
Operational amplifier slew rate (-)
5
10
—
—
V/µs
1 V input step
2.4
3.2
NOTE: For high side PWM, HIN pulse width must be > 1.5 µs.
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Fig. 1. Input/Output Timing Diagram
Fig. 2. Detime Waveform Definitions
Fig. 3. Input/OutSwitching Time Waveform nitions
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Fig. 4. Overcurrent Shutdown Switching Time Waveform Definitions
Fig. 5. Input Filter Function
Fig. 6. Diagnoic Feedback Operational Amplifier Circuit
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Lead Definitions
Symbol
Description
HIN1,2,3
LIN1,2,3
FAULT
Logic input for high side gate driver outputs (HO1,2,3), out of phase
Logic input for low side gate driver output (LO1,2,3), out of phase
Indicates over-current or undervoltage lockout (low side) has occurred, negative logic
Low side and logic fixed supply
VCC
ITRIP
CAO
Input for over-current shutdown
Output of current amplifier
CA-
Negative input of current amplifier
VSS
Logic ground
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
VSO
High side floating supply
High side gate drive output
High side floating supply return
Low side gate drive output
Low side return and positive input of current amplifier
Lead Assignments
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Functional Block Diagram
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Functional Block Diagram
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10
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
-
at a very high PWM duty cycle due to the
1 Features Description
bootstrap FET equivalent resistance (RBS
see page 4).
,
1.1 Integrated Bootstrap Functionality
In these cases, better performances can be achieved
by using the IRS213(0,03,2) non D version with an
external bootstrap network.
The IRS213(0,03,2)D family embeds an integrated
bootstrap FET that allows an alternative drive of the
bootstrap supply for a wide range of applications.
2 PCB Layout Tips
There is one bootstrap FET for each channel and it is
connected between each of the floating supply (VB1,
VB2, VB3) and VCC (see Fig. 7).
2.1 Distance from H to L Voltage
The IRS213(0,03,2)J package lacks some pins (see
page 8) in order to maximizing the distance between
the high voltage and low voltage pins. It’s strongly
recommended to place the components tied to the
floating voltage in the respective high voltage portions
of the device (VB1,2,3, VS1,2,3) side.
The bootstrap FET of each channel follows the state
of the respective low side output stage (i.e., bootFet
is ON when LO is high, it is OFF when LO is low),
unless the VB voltage is higher than approximately
1.1(VCC). In that case the bootstrap FET stays off
until the VB voltage returns below that threshold (see
Fig. 8).
2.2 Ground Plane
To minimize noise coupling ground plane must not be
placed under or near the high voltage floating side.
2.3 Gate Drive Loops
Current loops behave like an antenna able to receive
and transmit EM noise (see Fig. 9). In order to reduce
EM coupling and improve the power switch turn on/off
performances, gate drive loops must be reduced as
much as possible. Moreover, current can be injected
inside the gate drive loop via the IGBT collector-to-
gate parasitic capacitance. The parasitic auto-
inductance of the gate loop contributes to develop a
voltage across the gate-emitter increasing the
possibility of self turn-on effect.
IGC
VBX (VCC)
Fig. 7. Simplified BootFet Connection
gate
resistance
CGC
HOX (LOX )
Vth~17V
Vcc=15V
Gate Drive
Loop
Phase voltage
LO
VGE
( Vs0 )
VSX
BootFet
OFF
Bootstrap FET
state
BootFet
ON
BootFet
ON
Fig. 9. Antenna Loops
Fig. 8. State Diagram
2.4 Supply Capacitors
Bootstrap FET is suitable for most PWM modulation
schemes and can be used either in parallel with the
external bootstrap network (diode + resistor) or as a
replacement of it. The use of the integrated bootstrap
as a replacement of the external bootstrap network
may have some limitations in the following situations:
Supply capacitors must be placed as close as
possible to the device pins (VCC and VSS for the
ground tied supply, VB and VS for the floating supply)
in order to minimize parasitic inductance/resistance.
-
when used in non-complementary PWM
schemes (typically 6-step modulations)
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11
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
In order to avoid such undervoltage it is highly
recommended to minimize high side emitter to low
side collector distance and low side emitter to
negative bus rail stray inductance. See DT04-4 at
www.irf.com for more detailed information.
2.5 Routing and Placement
Power stage PCB parasitic may generate dangerous
voltage transients for the gate driver and the control
logic. In particular it’s recommended to limit phase
voltage negative transients.
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12
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Figures 10-40 provide information on the experimental performance of the IRS2132DS HVIC. The line plotted in
each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were
tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line
labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been
connected together to illustrate the understood trend. The individual data points on the curve were determined by
calculating the averaged experimental value of the parameter (for a given temperature).
1000
800
600
400
200
0
1500
1200
900
600
300
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 11. Turn-Off Propagation Delay vs. Temperature
Fig. 10. Turn-On Propagation Delay vs. Temperature
125
100
75
250
200
150
50
100
Exp.
Exp.
50
0
25
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 12. Turn-On Rise Time vs. Temperature
Fig. 13. Turn-Off Fall Time vs. Temperature
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
1500
1200
1500
1200
900
600
300
0
Exp.
900
Exp.
600
300
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 15. TITRIP Propagation Delay vs. Temperature
Fig. 14. DT Propagation Delay vs. Temperature
1500
250
200
150
100
1200
900
600
300
0
Exp.
50
Exp.
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 16. ITRIP to FAULT Propagation Delay vs.
Temperature
Fig.17. FAULT Low On Resistance vs. Temperature
10
100
8
6
4
2
0
80
60
40
20
0
Exp.
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 18. VCC Quiescent Current vs. Temperature
Fig. 19. VBS Quiescent Current vs. Temperature
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
11
10
9
11
10
Exp.
9
Exp.
8
8
7
6
7
6
-50
-25
0
25
50
75
100
125
125
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 20. VCCUV+ Threshold vs. Temperature
Fig. 21. VCCUV- Threshold vs. Temperature
11
10
9
11
10
9
Exp.
Exp.
8
8
7
7
6
6
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 22. VBSUV+ Threshold vs. Temperature
Fig. 23. VBSUV- Threshold vs. Temperature
750
500
250
0
750
500
250
0
EXP.
Exp.
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 24. ITRIP Positive Going Threshold vs. Temperature
Fig. 25. ITRIP Negative Going Threshold vs.
Temperature
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
750
500
400
300
200
100
0
600
Exp.
450
300
150
0
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 27. Output Low Short Circuit Current vs.
Temperature
Fig. 26. Output High Short Circuit Pulsed Current vs.
Temperature
25
20
15
10
25
20
15
10
5
Exp.
5
Exp.
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 29. "Low" ITRIP Bias Current vs. Temperature
Fig. 28. "High" ITRIP Bias Current vs. Temperature
8
25
20
15
10
5
Exp.
6
Exp.
4
2
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 30. VOH,AMP vs. Temperature
Fig. 31. VOL,AMP vs. Temperature
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
20
15
10
5
5
4
Exp.
3
Exp.
2
1
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 32. SR+,AMP vs. Temperature
Fig. 33. SR-,AMP vs. Temperature
12
5
4
3
2
1
0
10
8
Exp.
Exp.
6
4
2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 34. ISNK,AMP vs. Temperature
Fig. 35. ISRC,AMP vs. Temperature
15
20
16
12
8
12
9
Exp.
6
Exp.
3
4
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 37. IO+,AMP vs. Temperature
Fig. 36. IO-,AMP vs. Temperature
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IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
90
70
50
30
10
-10
125
100
Exp.
75
50
25
0
Exp.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Fig. 39. PSRR vs. Temperature
Fig. 38. VOS,AMP vs. Temperature
150
125
100
75
Exp.
50
25
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 40. CMRR vs. Temperature
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18
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Case Outlines
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19
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
Case Outlines
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20
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 28SOICW
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
11.90
3.90
23.70
11.40
10.80
18.20
1.50
Max
12.10
4.10
24.30
11.60
11.00
18.40
n/a
Min
Max
0.476
0.161
0.956
0.456
0.433
0.724
n/a
0.468
0.153
0.933
0.448
0.425
0.716
0.059
0.059
1.50
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 28SOICW
Metric
Imperial
Min
Code
A
B
C
D
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
102.00
30.40
29.10
26.40
Max
13.001
0.844
0.519
0.096
4.015
1.196
1.145
1.039
12.976
0.824
0.503
0.767
3.858
n/a
E
F
98.00
n/a
G
H
26.50
24.40
1.04
0.96
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21
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 44PLCC
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
23.90
3.90
31.70
14.10
17.90
17.90
2.00
Max
24.10
4.10
32.30
14.30
18.10
18.10
n/a
Min
0.94
Max
0.948
0.161
1.271
0.562
0.712
0.712
n/a
0.153
1.248
0.555
0.704
0.704
0.078
0.059
1.50
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 44PLCC
Metric
Imperial
Max
Code
A
B
C
D
Min
329.60
20.95
12.80
1.95
Max
330.25
21.45
13.20
2.45
Min
12.976
0.824
0.503
0.767
3.858
n/a
13.001
0.844
0.519
0.096
4.015
1.511
1.409
1.303
E
F
98.00
n/a
102.00
38.4
G
34.7
35.8
1.366
1.283
H
32.6
33.1
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22
IRS2130D/IRS21303D/IRS2132D (J&S)PbF
PRELIMINARY
ORDER INFORMATION
28-Lead PDIP IRS2130DPbF
28-Lead PDIP IRS21303DPbF
28-Lead PDIP IRS2132DPbF
28-Lead SOIC IRS2130DSPbF
28-Lead SOIC IRS21303DSPbF
28-Lead SOIC IRS2132DSPbF
44-Lead PLCC IRS2132DJPbF
44-Lead PLCC IRS21303DJPbF
44-Lead PLCC IRS2132DJPbF
28-Lead SOIC Tape & Reel IRS2130DSTRPbF
28-Lead SOIC Tape & Reel IRS21303DSTRPbF
28-Lead SOIC Tape & Reel IRS2132DSTRPbF
44-Lead PLCC Tape & Reel IRS2130DJTRPbF
44-Lead PLCC Tape & Reel IRS21303DJTRPbF
44-Lead PLCC Tape & Reel IRS2132DJTRPbF
WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105
This part has been qualified per industrial level
http://www.irf.com Data and specifications subject to change without notice.5/19/2006
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23
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