IRS21531DS [INFINEON]
EiceDRIVER™ 600 V half-bridge gate driver IC with typical 0.18 A source and 0.26 A sink currents in 8 Lead SOIC package for IGBTs and MOSFETs. Also available in 8 Lead PDIP.;
| 型号： | IRS21531DS |
| 厂家： | 
Infineon |
| 描述： | EiceDRIVER™ 600 V half-bridge gate driver IC with typical 0.18 A source and 0.26 A sink currents in 8 Lead SOIC package for IGBTs and MOSFETs. Also available in 8 Lead PDIP. 驱动 双极性晶体管 光电二极管 |
| 文件： | 总14页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60238 revE
IRS2153(1)D(S)PbF
SELF-OSCILLATING HALF-BRIDGE DRIVER IC
Features
Product Summary
Integrated 600 V half-bridge gate driver
VOFFSET
600 V Max
50%
CT, RT programmable oscillator
15.4 V Zener clamp on VCC
Micropower startup
Duty cycle
Non-latched shutdown on CT pin (1/6th VCC
)
Driver source/sink
current
Internal bootstrap FET
180 mA/260 mA typ.
15.4 V typ.
Excellent latch immunity on all inputs and outputs
+/- 50 V/ns dV/dt immunity
Vclamp
ESD protection on all pins
8-lead SOIC or PDIP package
Internal deadtime
1.1 µs typ. (IRS2153D)
0.6 µs typ. (IRS21531D)
Deadtime
Description
Package
The IRS2153(1)D is based on the popular IR2153 self-
oscillating half-bridge gate driver IC using a more
advanced silicon platform, and incorporates a high
voltage half-bridge gate driver with a front end oscillator
similar to the industry standard CMOS 555 timer. HVIC
and latch immune CMOS technologies enable rugged
monolithic construction. The output driver features a high
pulse current buffer stage designed for minimum driver
cross-conduction. Noise immunity is achieved with low
di/dt peak of the gate drivers.
PDIP8
IRS2153(1)DPbF
SO8
IRS2153(1)DSPbF
Typical Connection Diagram
+ AC Rectified Line
RVCC
VCC
VB
1
8
7
6
5
CBOOT
MHS
RT
HO
VS
LO
2
RT
L
CT
3
CVCC
CT
RL
MLS
COM
4
- AC Rectified Line
1
IRS2153(1)D
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead.
The thermal resistance and power dissipation ratings are measured under board mounted and still air
conditions.
Parameter
Symbol
VB
Definition
Min.
-0.3
Max.
625
Units
High side floating supply voltage
VS
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
RT pin current
VB - 25
VS – 0.3
-0.3
VB + 0.3
VB + 0.3
V
VHO
VLO
VCC + 0.3
IRT
-5
5
mA
V
VRT
VCT
ICC
RT pin voltage
-0.3
VCC + 0.3
VCC + 0.3
20
CT pin voltage
-0.3
Supply current (Note 1)
---
mA
V/ns
W
Maximum allowable current at LO and HO due to external
power transistor Miller effect.
IOMAX
-500
500
Allowable offset voltage slew rate
-50
---
50
1.0
dVS/dt
PD
Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin DIP
Maximum power dissipation @ TA ≤ +25 ºC, 8-Pin SOIC
Thermal resistance, junction to ambient, 8-Pin DIP
Thermal resistance, junction to ambient, 8-Pin SOIC
Junction temperature
PD
---
0.625
85
RthJA
RthJA
TJ
---
ºC/W
ºC
---
128
150
150
300
-55
-55
---
TS
Storage temperature
TL
Lead temperature (soldering, 10 seconds)
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal
breakdown voltage of 15.4 V. Please note that this supply pin should not be driven by a DC, low
impedance power source greater than the VCLAMP specified in the Electrical Characteristics section.
Note 1:
2
IRS2153(1)D
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Parameter
Symbol
VBS
Definition
High side floating supply voltage
Steady state side floating supply offset voltage
Supply voltage
Min.
VCC - 0.7
-3.0 (Note 2)
VCCUV+ +0.1 V
(Note 3)
Max.
VCLAMP
600
Units
V
VS
VCC
ICC
VCC CLAMP
5
Supply current
mA
ºC
TJ
Junction temperature
-40
125
It is recommended to avoid output switching conditions where the negative-going spikes at the VS
node would decrease VS below ground by more than -5 V.
Note 2:
Note 3:
Enough current should be supplied to the
clamping the voltage at this pin.
pin of the IC to keep the internal 15.6 V zener diode
VCC
Recommended Component Values
Parameter
Symbol
RT
Component
Min.
1
Max.
---
Units
kΩ
Timing resistor value
CT pin capacitor value
CT
330
---
pF
VBIAS (VCC, VBS) = 14 V, VS=0 V and TA = 25 °C, CLO = CHO = 1 nF.
Frequency vs. RT
1,000,000
CT Values
100,000
10,000
1,000
100
330pf
470pF
1nF
2.2nF
4.7nF
10nF
10
1,000
10,000
100,000
1,000,000
RT (Ohm)
For further information, see Fig. 12.
3
IRS2153(1)D
Electrical Characteristics
VBIAS (VCC, VBS) = 14 V, CT = 1 nF, VS=0 V and TA = 25 °C unless otherwise specified. The output voltage and current (VO and IO) parameters are
referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Test Conditions
Symbol
Definition
Min Typ Max Units
Low Voltage Supply Characteristics
VCCUV
+
Rising VCC undervoltage lockout threshold
Falling VCC undervoltage lockout threshold
10.0
8.0
1.6
---
11.0
9.0
12.0
10.0
2.4
V
VCCUV
-
VCCUVHYS VCC undervoltage lockout hysteresis
2.0
IQCCUV
IQCC
ICC
Micropower startup VCC supply current
Quiescent supply current
130
800
1.8
170
1000
---
VCC ≤ VCCUV-
µA
---
VCC
supply current
---
mA
V
RT = 36.9 kΩ
VCC
VCC zener clamp voltage
Floating Supply Characteristics
VCC
14.4
15.4
16.8
ICC = 5 mA
CLAMP
IQBS
Quiescent VBS supply current
BS supply undervoltage positive going
threshold
BS supply undervoltage negative going
---
60
80
µA
V
V
VBSUV+
8.0
9.0
9.5
V
VBSUV-
ILK
7.0
---
8.0
---
9.0
50
threshold
Offset supply leakage current
VB = VS = 600 V
µA
Oscillator I/O Characteristics
18.4
88
---
19.0
93
19.6
100
---
RT = 36.5 kΩ
RT = 7.15 kΩ
fo < 100 kHz
fOSC
Oscillator frequency
kHz
%
d
RT pin duty cycle
50
0.02
0.30
9.32
4.66
2.3
10
ICT
CT pin current
---
1.0
0.6
---
µA
ICTUV
VCT+
VCT-
VCTSD
UV-mode CT pin pulldown current
Upper CT ramp voltage threshold
Lower CT ramp voltage threshold
CT voltage shutdown threshold
0.20
---
mA
VCC = 7 V
V
---
---
2.2
---
2.4
50
IRT = -100 µA
IRT = -1 mA
IRT = 100 µA
IRT = 1 mA
VRT+
High-level RT output voltage, VCC - VRT
---
100
10
300
50
---
VRT-
Low-level RT output voltage
UV-mode RT output voltage
---
100
0
300
100
VRTUV
---
VCC ≤ VCCUV-
mV
IRT = -100 µA,
---
---
10
50
VCT = 0 V
VRTSD
SD-mode RT output voltage, VCC - VRT
IRT = -1 mA,
VCT = 0 V
100
300
4
IRS2153(1)D
Electrical Characteristics
V
(V , V ) = 14 V, C = 1 nF, V =0 V and T = 25 °C unless otherwise specified. The output voltage and current (VO and IO)
BIAS CC BS
T
S
A
parameters are referenced to COM and are applicable to the respective output leads: HO or LO. CLO = CHO = 1 nF.
Test Conditions
Symbol
Definition
Min
Typ
Max Units
Gate Driver Output Characteristics
VOH
VOL
VCC
High-level output voltage
Low-level output voltage
---
---
---
IO = 0 A
COM
---
V
IO = 0 A
VCC ≤ VCCUV-
,
VOL_UV
UV-mode output voltage
---
COM
---
Output rise time
---
---
120
50
220
tr
tf
ns
Output fall time
80
---
Shutdown propagation delay
Output deadtime (HO or LO) (IRS2153D)
---
350
1.1
tsd
td
0.65
1.75
µs
µs
Output deadtime (HO or LO) (IRS21531D)
Output source current
0.35
---
0.6
180
260
0.85
---
td
IO+
IO-
mA
Output sink current
---
---
Bootstrap FET Characteristics
VB_ON
IB_CAP
IB_10V
VB when the bootstrap FET is on
VB source current when FET is on
VB source current when FET is on
---
40
10
13.7
55
---
---
---
V
CBS=0.1 uF
VB=10 V
mA
12
5
IRS2153(1)D
Lead Definitions
VCC
RT
VB
HO
VS
LO
1
2
3
4
8
7
6
5
CT
COM
Lead
Description
Symbol
VCC
RT
Logic and internal gate drive supply voltage
Oscillator timing resistor input
CT
Oscillator timing capacitor input
COM IC power and signal ground
LO
VS
Low-side gate driver output
High voltage floating supply return
High-side gate driver output
HO
VB
High side gate driver floating supply
6
IRS2153(1)D
Functional Block Diagram
2
RT
8
7
VB
R
R
Q
HV
LEVEL
SHIFT
+
-
R
S
HO
PULSE
FILTER
DEAD
TIME
R
S
Q
Q
PULSE
GEN
6
1
VS
+
-
BOOTSTRAP
DRIVE
VCC
DEAD
TIME
15.4V
R/2
R/2
Q
S
5
4
LO
DELAY
+
-
R1
R2
3
CT
COM
M1
UV
DETECT
7
IRS2153(1)D
Timing Diagram
Operating Mode
VCCUV+
VCC
Fault Mode:
CT <1/6*VCC
2/3 VCC
VCT
1/3 VCC
1/6 VCC
VCC
LO
DT
VCC
HO
DT
VCC
VRT
IRT
Switching Time Waveform
Deadtime Waveform
90%
LO
HO
10%
tr
tf
DTLO
DTHO
90%
10%
90%
HO
LO
10%
8
IRS2153(1)D
Bootstrap MOSFET
Functional Description
The internal bootstrap FET and supply capacitor (CBOOT) comprise
the supply voltage for the high side driver circuitry. The internal
boostrap FET only turns on when LO is high. To guarantee that
the high-side supply is charged up before the first pulse on pin
HO, the first pulse from the output drivers comes from the LO pin.
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the state
the IC is in when VCC is below the turn-on threshold of the IC. The
IRS2153(1)D under voltage lock-out is designed to maintain an
ultra low supply current of less than 170 µA, and to guarantee the
IC is fully functional before the high and low side output drivers
are activated. During under voltage lock-out mode, the high and
low-side driver outputs HO and LO are both low.
Normal operating mode
Once the VCCUV+ threshold is passed, the MOSFET M1 opens, RT
increases to approximately VCC (VCC-VRT+) and the external CT
capacitor starts charging. Once the CT voltage reaches VCT
-
Supply voltage
(about 1/3 of VCC), established by an internal resistor ladder, LO
turns on with a delay equivalent to the deadtime (td). Once the CT
voltage reaches VCT+ (approximately 2/3 of VCC), LO goes low, RT
goes down to approximately ground (VRT-), the CT capacitor
discharges and the deadtime circuit is activated. At the end of the
deadtime, HO goes high. Once the CT voltage reaches VCT-, HO
goes low, RT goes high again, the deadtime is activated. At the
end of the deadtime, LO goes high and the cycle starts over
again.
+ AC Rectified Line
RVCC
VCC
RT
VB
HO
VS
LO
1
2
3
4
8
7
6
5
CBOOT
MHS
RT
CT
L
The following equation provides the oscillator frequency:
CVCC
CT
COM
RL
MLS
1
f ~
1.453× RT ×CT
- AC Rectified Line
Fig. 1 Typical Connection Diagram
This equation can vary slightly from actual measurements due to
internal comparator over- and under-shoot delays. For a more
accurate determination of the output frequency, the frequency
characteristic curves should be used (RT vs. Frequency, page 3).
Fig. 1 shows an example of supply voltage. The start-up capacitor
(CVCC) is charged by current through supply resistor (RVCC) minus
the start-up current drawn by the IC. This resistor is chosen to
provide sufficient current to supply the IRS2153(1)D from the DC
bus. CVCC should be large enough to hold the voltage at Vcc
above the UVLO threshold for one half cycle of the line voltage as
it will only be charged at the peak, typically 0.1 uF. It will be
necessary for RVCC to dissipate around 1 W.
Shut-down
If CT is pulled down below
(approximately 1/6 of VCC) by
V
CTSD
an external circuit, CT doesn’t charge up and oscillation stops.
LO is held low and the bootstrap FET is off. Oscillation will
resume once CT is able to charge up again to VCT-
.
The use of a two diode charge pump made of DC1, DC2 and
CVS (Fig. 2) from the half bridge (VS) is also possible however
the above approach is simplest and the dissipation in RVCC should
not be unacceptably high.
+ AC Rectified Line
RVCC
VCC
RT
VB
HO
VS
LO
1
2
3
4
8
7
6
5
CBOOT
MHS
DC2
RT
CT
L
CVCC
CVS
CT
COM
RL
MLS
DC1
- AC Rectified Line
Fig. 2 Charge pump circuit
The supply resistor (RVCC) must be selected such that enough
supply current is available over all operating conditions.
Once the capacitor voltage on VCC reaches the start-up threshold
VCCUV+, the IC turns on and HO and LO begin to oscillate.
9
IRS2153(1)D
100
98
96
94
92
90
19
18.8
18.6
18.4
18.2
18
-25
0
25
50
75
100
125
11
12
13
14
15
16
Temperature(C)
VCC(V)
FREQ vs VCC
FREQ vs TEMP
Fig. 3
Fig. 4
1.25
1.4
1.3
1.2
1.1
1
1.15
1.05
0.95
0.85
0.75
0.9
-25
0
25
50
75
100
125
11
12
13
14
15
16
Temperature(C)
VCC(V)
DT vs TEMP
Fig. 6 (IRS2153D)
DT vs VCC
Fig. 5 (IRS2153D)
17
16
15
90
80
70
60
50
40
30
20
10
0
-25
0
25
50
75
100
125
20
70
120
Temperature (°C)
Frequency(kHz)
VCC CLAMP vs TEMP
Tj vs. Frequency (SOIC)
Fig. 7
Fig. 8
10
IRS2153(1)D
300
250
200
150
100
50
300
250
200
150
100
50
IsinkLO
IsinkHO
IsourceHO
IsourceLO
0
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature(C)
Temperature(C)
IsourceHO,IsinkHO vs Temp
IsourceLO,IsinkLO vs Temp
Fig. 10
Fig. 9
80
70
60
50
40
30
20
10
0
VOH_HO vs. Frequency
IB_CAP
With External BS diode
No external BS diode
16
14
12
10
8
IBS_10V
6
4
-25
0
25
50
75
100
125
2
Temperature(C)
0
0
50
100
150
200
250
300
350
400
IBCAP, IBS10V vs TEMP
Frequency (kHz)
T=25°C, VS=0V, CHO = 1nF
Fig. 11
Fig. 12
VOH_HO vs. Frequency vs. Temp
VCC=14V, CHO=1nF, VS=0V
14
12
10
8
6
4
2
0
K
20
K
50
K
75
hz
0K
10
5K
12
0K
15
0K
0
2
46K
.
1
Frequency (kHz)
T=25c T=75c
Fig. 13
T=-25c
T=125c
11
IRS2153(1)D
IRS2153(1)DPbF
IRS2153(1)DSPbF
12
IRS2153(1)D
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric
Imperial
Min
0.311
0.153
0.46
Code
A
B
C
D
E
F
G
H
Min
7.90
3.90
11.70
5.45
6.30
5.10
1.50
1.50
Max
8.10
4.10
12.30
5.55
6.50
5.30
n/a
Max
0.318
0.161
0.484
0.218
0.255
0.208
n/a
0.214
0.248
0.200
0.059
0.059
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
329.60
20.95
12.80
1.95
98.00
n/a
14.50
12.40
Max
330.25
21.45
13.20
2.45
102.00
18.40
17.10
14.40
Min
12.976
0.824
0.503
0.767
3.858
n/a
Max
13.001
0.844
0.519
0.096
4.015
0.724
0.673
0.566
0.570
0.488
13
IRS2153(1)D
PART MARKING INFORMATION
ORDER INFORMATION
8-Lead PDIP IRS2153DPbF
8-Lead PDIP IRS21531DPbF
8-Lead SOIC IRS2153DSPbF
8-Lead SOIC IRS21531DSPbF
8-Lead SOIC Tape & Reel IRS2153DSTRPbF
8-Lead SOIC Tape & Reel IRS21531DSTRPbF
The SOIC-8 is MSL2 qualified.
This product has been designed and qualified for the industrial level.
Qualification standards can be found at www.irf.com <http://www.irf.com>
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
Data and specifications subject to change without notice. 6/27/2006
14
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