IRS23365DMPBF_技术文档

IRS23365DM

Product Summary

Topology

Features

•

Drives up to six IGBT/MOSFET power devices

3 Phase

≤ 600 V

Gate drive supplies up to 20 V per channel

Integrated bootstrap functionality

Overꢀcurrent protection

Overꢀtemperature shutdown input

Advanced input filter

Integrated deadtime protection

Shootꢀthrough (crossꢀconduction) protection

Undervoltage lockout for V_CC& V_BS

Enable/disable input and fault reporting

Adjustable fault clear timing

V_OFFSET

V_OUT

10 V – 20 V

180 mA & 380 mA

530 ns & 530 ns

275 ns

I_o+& I _oꢀ(typical)

t_ON& t_OFF(typical)

Deadtime (typical)

Package Options

Separate logic and power grounds

3.3 V input logic compatible

Tolerant to negative transient voltage

Designed for use with bootstrap power supplies

Matched propagation delays for all channels

ꢀ40°C to 125°C operating range

RoHS compliant

LeadꢀFree

48ꢀLead MLPQ7X7

(without 14 leads)

Typical Applications

•

Appliance motor drives

Servo drives

Micro inverter drives

General purpose three phase inverters

Typical Connection Diagram

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IRS23365DM

Description

The IRS23365DM is a high voltage, high speed, power MOSFET and IGBT gate drivers with three highꢀside and three lowꢀ

side referenced output channels for 3ꢀphase applications. This IC is designed to be used with lowꢀcost bootstrap power

supplies; the bootstrap diode functionality has been integrated into this device to reduce the component count and the PCB

size. Proprietary HVIC and latch immune CMOS technologies have been implemented in a rugged monolithic structure. The

floating logic input is compatible with standard CMOS or LSTTL outputs (down to 3.3 V logic). A current trip function which

terminates all six outputs can be derived from an external current sense resistor. Enable functionality is available to terminate

all six outputs simultaneously. An openꢀdrain FAULT signal is provided to indicate that a fault (e.g., overꢀcurrent, overꢀ

temperature, or undervoltage shutdown event) has occurred. Fault conditions are cleared automatically after a delay

programmed externally via an RC network connected to the RCIN input. The output drivers feature a highꢀpulse current

buffer stage designed for minimum driver crossꢀconduction. Shootꢀthrough protection circuitry and a minimum deadtime

circuitry have been integrated into this IC. Propagation delays are matched to simplify the HVIC’s use in high frequency

applications. The floating channels can be used to drive Nꢀchannel power MOSFETs or IGBTs in the highꢀside configuration,

which operate up to 600 V.

Simplified Block Diagram

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IRS23365DM

Typical Application Diagram

DC Bus ≤ 600 V

+

To

Load

Input

Voltage

ꢀ

IRS2336xD

V_CC

Control Inputs,

EN, & FAULT

Qualification Information^†

Industrial^††

Qualification Level

Comments: This family of ICs has passed JEDEC’s Industrial

qualification. IR’s Consumer qualification level is granted by

extension of the higher Industrial level.

MSL3^†††, 260°C

MLPQ7X7

Moisture Sensitivity Level

(per IPC/JEDEC JꢀSTDꢀ020)

Class 1B

Human Body Model

Machine Model

(per JEDEC standard JESD22ꢀA114)

Class B

ESD

(per EIA/JEDEC standard EIA/JESD22ꢀA115)

Class IV

(per JEDEC standard JESD22ꢀC101)

Class I, Level A

Charged Device Model ^††††

IC LatchꢀUp Test

RoHS Compliant

(per JESD78)

Yes

†

††

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information.

†††

Higher MSL ratings may be available for the specific package types listed here. Please contact your International

Rectifier sales representative for further information.

††††

Charged Device Model classification is based on SOIC28W package.

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IRS23365DM

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters

are absolute voltages referenced to V_SSunless otherwise stated in the table. The thermal resistance and power dissipation

ratings are measured under board mounted and still air conditions. Voltage clamps are included between V_CC& COM (25 V),

V_CC& V_SS(25 V), and V_B& V_S(25 V).

Definition

Min

Max

Units

Symbol

V_CC

25^†

Low side supply voltage

ꢀ0.3

V_IN

Logic input voltage (HIN, LIN, ITRIP, EN)

V_SSꢀ0.3

V_SS+5.2

V_RCIN

V_B

V_S

V_HO

V_LO

V_FLT

COM

dV_S/dt

PW_HIN

RCIN input voltage

V_SSꢀ0.3

ꢀ0.3

V_CC+0.3

625^†

Highꢀside floating well supply voltage

Highꢀside floating well supply return voltage

Floating gate drive output voltage

Lowꢀside output voltage

Fault output voltage

Power ground

V

V_Bꢀ25^†

V_Sꢀ0.3

COMꢀ0.3

V_SSꢀ0.3

V_CCꢀ25

—

V_B+0.3

V_CC+0.3

50

Allowable V_Soffset supply transient relative to V_SS

Highꢀside input pulse width

V/ns

ns

500

—

P_D

2.0

W

Package power dissipation @ T_A≤+25ºC

—

Rth_JA

Thermal resistance, junction to ambient

63

ºC/W

T_J

T_S

T_L

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

—

ꢀ55

—

150

300

ºC

†

All supplies are tested at 25 V. An internal 25 V clamp exists for each supply.

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IRS23365DM

Recommended Operating Conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute

voltages referenced to V_SSunless otherwise stated in the table. The offset rating is tested with supplies of (V_CCꢀCOM) = (V_Bꢀ

V_S) = 15 V.

Definition

Min

Max

Units

Symbol

V_CC

V_IN

V_B

Lowꢀside supply voltage

10

V_SS

20

HIN, LIN, & EN input voltage

V_SS+5

V_S+20

Highꢀside floating well supply voltage

V_S+10

Highꢀside floating well supply offset voltage^†

Transient highꢀside floating supply voltage^††

Floating gate drive output voltage

Lowꢀside output voltage

V_S

V_S(t)

V_HO

COMꢀ8

ꢀ50

V_s

COM

ꢀ5

V_SS

ꢀ40

600

V_B

V_CC

5

V_CC

V_SS+5

125

V

V_LO

COM

V_FLT

V_RCIN

V_ITRIP

T_A

Power ground

FAULT output voltage

RCIN input voltage

ITRIP input voltage

Ambient temperature

ºC

†

V_S

of –8 V to 600 V. Logic state held for of –8 V to –V_BS. Please refer to Design Tip DT97ꢀ3 for

Logic operation for

more details.

†† Operational for transient negative V_Sof V_SSꢀ 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the

Application Information section of this datasheet for more details.

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IRS23365DM

Static Electrical Characteristics

(V_CCꢀCOM) = (V_BꢀV_S) = 15 V. T_A= 25^oC unless otherwise specified. The V_INand I_INparameters are referenced to V_SSand are

applicable to all six channels. The V_Oand I_Oparameters are referenced to respective V_Sand COM and are applicable to the

respective output leads HO or LO. The

parameters are referenced to V_SS. The

parameters are referenced to V_S.

V_CCUV

V_BSUV

Symbol

Definition

V_CCsupply undervoltage positive going threshold

V_CCsupply undervoltage negative going

threshold

Min

8

Typ

8.9

Max

9.8

Units

Test Conditions

V_CCUV

+

V_CCUV

7.4

8.2

9

ꢀ

—

V_CCUVHY

V_BSUV+

V

_CCsupply undervoltage hysteresis

0.3

8

0.7

8.9

V

NA

V_BSsupply undervoltage positive going threshold

9.8

V_BSsupply undervoltage negative going

threshold

V_BSUVꢀ

7.4

8.2

9

—

V_BSUVHY

I_LK

I_QBS

V

_BSsupply undervoltage hysteresis

0.3

—

0.7

—

70

2

Highꢀside floating well offset supply leakage

Quiescent V_BSsupply current

50

120

4

V_B= V_S= 600 V

ꢁA

All inputs are in the off

state

I_QCC

Quiescent V_CCsupply current

mA

V_OH

V_OL

High level output voltage drop, V_BIASꢀV_O

Low level output voltage drop, V_O

—

0.90

0.40

1.4

0.6

V

I_O= 20 mA

V_O=0 V,V_IN=0 V,

PW ≤ 10 ꢁs

V_O=15 V,V_IN=5 V,

PW ≤ 10 ꢁs

I_o+

I_oꢀ

Output high short circuit pulsed current

Output low short circuit pulsed current

120

250

180

380

—

mA

V_IH

V_IL

Logic “1” input voltage

Logic “0” input voltage

Input voltage clamp

(HIN, LIN, ITRIP and EN)

Input bias current (HO = High)

2.5

—

NA

0.8

V

V_IN,CLAMP

I_HIN+

4.8

—

5.2

5.65

220

I_IN= 100 ꢁA

V_IN= 0 V

165

I_HINꢀ

I_LIN+

I_LINꢀ

Input bias current (HO = Low)

Input bias current (LO = High)

Input bias current (LO = Low)

—

120

165

120

165

220

165

V_IN= 4 V

V_IN= 0 V

V_IN= 4 V

ꢁA

V

V_RCIN,TH

V_RCIN,HY

I_RCIN

R_ON,RCIN

VIT,TH+

VIT,THꢀ

VIT,HYS

IITRIP+

IITRIPꢀ

RCIN positive going threshold

RCIN hysteresis

—

0.37

—

0.8

—

8

3

—

50

0.46

0.4

0.07

5

—

5

—

1

100

0.55

—

20

1

2.5

—

20

1

NA

RCIN input bias current

RCIN low on resistance

ITRIP positive going threshold

ITRIP negative going threshold

ITRIP hysteresis

ꢁA

ꢂ

V

V_RCIN= 0 V or 15 V

I = 1.5 mA

NA

“High” ITRIP input bias current

“Low” ITRIP input bias current

ꢁA

V

VIN = 4 V

VIN = 0 V

NA

VEN,TH+ Enable positive going threshold

VEN,THꢀ

IEN+

Enable negative going threshold

“High” enable input bias current

“Low” enable input bias current

ꢁA

ꢂ

VIN = 4 V

VIN = 0 V

I = 1.5 mA

NA

IENꢀ

—

50

200

RON,FLT FAULT low on resistance

RBS Internal BS diode Ron

100

—

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IRS23365DM

Dynamic Electrical Characteristics

V_CC= V_B= 15 V, V_S= V_SS= COM, T_A= 25^oC, and C_L= 1000 pF unless otherwise specified.

Symbol

Definition

Turnꢀon propagation delay

Turnꢀoff propagation delay

Turnꢀon rise time

Min

400

—

Typ

530

125

50

Max

750

190

75

Units

Test Conditions

t_ON

t_OFF

t_R

V_IN= 0 V & 5 V

t_F

Turnꢀoff fall time

—

Input filter time^†

(HIN, LIN, ITRIP)

t_FIL,IN

t_EN

t_FILTER,EN

200

350

510

ns

Enable low to output shutdown

propagation delay

350

460

650

V_IN,V_EN= 0 V or 5 V

Enable input filter time

100

1.3

200

—

2

NA

V_IN= 0 V or 5 V

FAULT clear time

RCIN: R = 2 Mꢂ, C = 1 nF

t_FLTCLR

1.65

ms

V_ITRIP= 0 V

ITRIP to output shutdown

propagation delay

t_ITRIP

t_BL

500

—

750

400

600

1200

—

V_ITRIP= 5 V

ITRIP blanking time

ITRIP to FAULT propagation delay

Deadtime

V_IN= 0 V or 5 V

t_FLT

DT

400

950

420

V_ITRIP= 5 V

190

—

275

—

V_IN= 0 V & 5 V without

external deadtime

DT matching^††

MDT

60

ns

V_IN= 0 V & 5 V with

external deadtime larger

than DT

††

MT

PM

—

50

75

Delay matching time (t_ON, t_OFF

Pulse width distortion^†††

)

PW input=10 ꢁs

†

The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the input

filter is exceeded.

††

This parameter applies to all of the channels. Please see the application section for more details.

†††

PM is defined as PW_INꢀ PW_OUT.

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IRS23365DM

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IRS23365DM

Functional Block Diagram: IRS23365D

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IRS23365DM

Input/Output Pin Equivalent Circuit Diagrams: IRS23365D

V_B

ESD

Diode

20V

Clamp

HO

ESD

Diode

V_CC

ESD

Diode

V_S

R_PU

600V

20V

Clamp

HIN

or LIN

V_CC

VIN

Clamp

ESD

Diode

ESD

Diode

V_SS

25 V

Clamp

LO

ESD

Diode

COM

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IRS23365DM

Lead Definitions: IRS23365DM

Symbol

Description

VCC

VSS

Lowꢀside supply voltage

Logic ground

VB1

Highꢀside gate drive floating supply (phase 1)

Highꢀside gate drive floating supply (phase 2)

Highꢀside gate drive floating supply (phase 3)

High voltage floating supply return (phase 1)

High voltage floating supply return (phase 2)

High voltage floating supply return (phase 3)

VB2

VB3

VS1

VS2

VS3

HIN1/N

HIN2/N

HIN3/N

LIN1/N

LIN2/N

LIN3/N

HO1

Logic inputs for highꢀside gate driver outputs (phase 1); input is outꢀofꢀphase with output

Logic inputs for highꢀside gate driver outputs (phase 2); input is outꢀofꢀphase with output

Logic inputs for highꢀside gate driver outputs (phase 3); input is outꢀofꢀpha se with output

Logic inputs for lowꢀside gate driver outputs (phase 1); input is outꢀofꢀphase with output

Logic inputs for lowꢀside gate driver outputs (phase 2); input is outꢀofꢀphase with output

Logic inputs for lowꢀside gate driver outputs (phase 3); input is outꢀofꢀphase with output

Highꢀside driver outputs (phase 1)

HO2

Highꢀside driver outputs (phase 2)

HO3

Highꢀside driver outputs (phase 3)

LO1

Lowꢀside driver outputs (phase 1)

LO2

Lowꢀside driver outputs (phase 2)

LO3

Lowꢀside driver outputs (phase 3)

COM

Lowꢀside gate drive return

Indicates overꢀcurrent, overꢀtemperature (ITRIP), or lowꢀside undervoltage lockout has occurred. This pin

has negative logic and an openꢀdrain output. The use of overꢀcurrent and overꢀtemperature protection

requires the use of external components.

Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No effect on

FAULT and not latched.

FAULT/N

EN

Analog input for overꢀcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT and

RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time t_FLTCLR, then

automatically becomes inactive (openꢀdrain high impedance).

An external RC network input used to define the FAULT CLEAR delay (t_FLTCLR) approximately equal to R*C.

When RCIN > 8 V, the FAULT pin goes back into an openꢀdrain highꢀimpedance state.

ITRIP

RCIN

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IRS23365DM

Lead Assignments

The central exposed pad (35) has to be connected to COM for better electrical performance.

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IRS23365DM

Application Information and Additional Details

Information regarding the following topics are included as subsections within this section of the datasheet.

•

IGBT/MOSFET Gate Drive

Switching and Timing Relationships

Deadtime

Matched Propagation Delays

Input Logic Compatibility

Undervoltage Lockout Protection

ShootꢀThrough Protection

Enable Input

Fault Reporting and Programmable Fault Clear Timer

OverꢀCurrent Protection

OverꢀTemperature Shutdown Protection

Truth Table: Undervoltage lockout, ITRIP, and ENABLE

Advanced Input Filter

ShortꢀPulse / Noise Rejection

Integrated Bootstrap Functionality

Bootstrap Power Supply Design

Separate Logic and Power Grounds

Tolerant to Negative V_STransients

PCB Layout Tips

Integrated Bootstrap FET limitation

Additional Documentation

IGBT/MOSFET Gate Drive

The IRS23365D HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several

parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the

power switch, is defined as I_O. The voltage that drives the gate of the external power switch is defined as V_HOfor the highꢀside

power switch and V_LOfor the lowꢀside power switch; this parameter is sometimes generically called V_OUTand in this case does not

differentiate between the highꢀside or lowꢀside output voltage.

V_B

(or V_CC

)

(or V_CC)

I_O+

HO

(or LO)

+

I_Oꢀ

V_HO(or V_LO)

ꢀ

V_S

(or COM)

Figure 1: HVIC sourcing current

Figure 2: HVIC sinking current

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IRS23365DM

Switching and Timing Relationships

The relationship between the input and output signals of the IRS23365D are illustrated below in Figures 3 . From these

figures, we can see the definitions of several timing parameters (i.e., PW_IN, PW_OUT, t_ON, t_OFF, t_R, and t_F) associated with this

device.

LINx

(or HINx)

50%

PW_IN

t_OFFt_F

t_ONt_R

PW_OUT

90%

10%

90%

10%

LOx

(or HOx)

Figure 3: Switching time waveforms

The following two figures illustrate the timing relationships of some of the functionality of the IRS23365D; this functionality is

described in further detail later in this document.

During interval A of Figure 4, the HVIC has received the command to turnꢀon both the highꢀ and lowꢀside switches at the same

time; as a result, the shootꢀthrough protection of the HVIC has prevented this condition and both the highꢀ and lowꢀside output

are held in the off state.

Interval B of Figures 4 and 5 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of

the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low), the voltage

on the RCIN pin has been pulled to 0 V, and a fault is reported by the FAULT output transitioning to the low state. Once the

ITRIP input has returned to the low state, the output will remain disabled and the fault condition reported until the voltage on

the RCIN pin charges up to V_RCIN,TH(see interval C in Figure 6); the charging characteristics are dictated by the RC network

attached to the RCIN pin.

During intervals D and E of Figure 4, we can see that the enable (EN) pin has been pulled low (as is the case when the driver IC

has received a command from the control IC to shutdown); this results in the outputs (HOx and LOx) being held in the low state

until the enable pin is pulled high.

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IRS23365DM

Figure 4: Input/output timing diagram

Interval B

Interval C

V_IT,THꢀ

V_IT,TH+

ITRIP

FAULT

50%

t_FLT

RCIN

HOx

V_RCIN,TH

t_FLTCLR

90%

t_ITRIP

Figure 5: Detailed view of B & C intervals

Deadtime

This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within

IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a

minimum deadtime) in which both the highꢀ and lowꢀside power switches are held off; this is done to ensure that the power

switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is

automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified

by the gate driver. Figure 6 illustrates the deadtime period and the relationship between the output gate signals.

The deadtime circuitry of the IRS23365D is matched with respect to the highꢀ and lowꢀside outputs of a given channel;

additionally, the deadtimes of each of the three channels are matched. Figure 6 defines the two deadtime parameters (i.e.,

DT₁and DT₂) of a specific channel; the deadtime matching parameter (MDT) associated with the IRS23365D specifies the

maximum difference between DT₁and DT₂. The MDT parameter also applies when comparing the DT of one channel of the

IRS23365D to that of another.

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IRS23365DM

Figure 6: Illustration of deadtime

Matched Propagation Delays

The IRS23365D is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a

signal at the input requires approximately the same time duration (i.e., t_ON, t_OFF) for both the lowꢀside channels and the highꢀ

side channels; the maximum difference is specified by the delay matching parameter (MT). Additionally, the propagation delay

for each lowꢀside channel is matched when compared to the other lowꢀside channels and the propagation delays of the highꢀ

side channels are matched with each other; the MT specification applies as well. The propagation turnꢀon delay (t_ON) of the

IRS23365D is matched to the propagation turnꢀon delay (t_OFF).

Input Logic Compatibility

The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS23365D has been designed to be

compatible with 3.3 V and 5 V logicꢀlevel signals. Figure 7 illustrates an input signal to the IRS23365D, its input threshold

values, and the logic state of the IC as a result of the input signal.

Figure 7: HIN & LIN input thresholds

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IRS23365DM

Undervoltage Lockout Protection

This family of ICs provides undervoltage lockout protection on both the V_CC(logic and lowꢀside circuitry) power supply and the

V_BS(highꢀside circuitry) power supply. Figure 8 is used to illustrate this concept; V_CC(or V_BS) is plotted over time and as the

waveform crosses the UVLO threshold (V_CCUV+/ꢀor V_BSUV+/ꢀ) the undervoltage protection is enabled or disabled.

Upon powerꢀup, should the V_CCvoltage fail to reach the V_CCUV+threshold, the IC will not turnꢀon. Additionally, if the V_CC

voltage decreases below the V_CCUVꢀthreshold during operation, the undervoltage lockout circuitry will recognize a fault

condition and shutdown the highꢀ and lowꢀside gate drive outputs, and the FAULT pin will transition to the low state to inform

the controller of the fault condition.

Upon powerꢀup, should the V_BSvoltage fail to reach the V_BSUVthreshold, the IC will not turnꢀon. Additionally, if the V_BSvoltage

decreases below the V_BSUVthreshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and

shutdown the highꢀside gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to

fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low

voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high

conduction losses within the power device and could lead to power device failure.

Figure 8: UVLO protection

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IRS23365DM

ShootꢀThrough Protection

The IRS23365D is equipped with shootꢀthrough protection circuitry (also known as crossꢀconduction prevention circuitry).

Figure 9 shows how this protection circuitry prevents both the highꢀ and lowꢀside switches from conducting at the same time.

Table 1 illustrates the input/output relationship of the devices in the form of a truth table.

Figure 9: Illustration of shootꢀthrough protection circuitry

IRS23365D

HIN

0

LIN

0

HO

0

LO

0

1

0

1

0

1

0

Table 1: Input/output truth table for IRS23365D

Enable Input

The IRS23365D is equipped with an enable input pin that is used to shutdown or enable the HVIC. When the EN pin is in the

high state the HVIC is able to operate normally (assuming no other fault conditions). When a condition occurs that should

shutdown the HVIC, the EN pin should see a low logic state. The enable circuitry of the IRS23365D features an input filter; the

minimum input duration is specified by t_FILTER,EN. Please refer to the EN pin parameters V_EN,TH+, V_EN,THꢀ, and I_ENfor the details

of its use. Table 2 gives a summary of this pin’s functionality and Figure 10 illustrates the outputs’ response to a shutdown

command.

EN

V_EN,THꢀ

Enable Input

t_EN

Enable input high

Enable input low

Outputs enabled^*

Outputs disabled

90%

HOx

(or LOx)

Table 2: Enable functionality truth table

(*assumes no other fault condition)

Figure 10: Output enable timing waveform

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IRS23365DM

Fault Reporting and Programmable Fault Clear Timer

The IRS23365D provides an integrated fault reporting output and an adjustable fault clear timer. There are two situations that

would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of V_CCand the second is if the

ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally pulled to V_SSand the fault clear timer

is activated. The fault output stays in the low state until the fault condition has been removed and the fault clear timer expires;

once the fault clear timer expires, the voltage on the FAULT pin will return to V_CC

.

The length of the fault clear time period (t_FLTCLR) is determined by exponential charging characteristics of the capacitor where

the time constant is set by R_RCINand C_RCIN. In Figure 11 where we see that a fault condition has occurred (UVLO or ITRIP),

RCIN and FAULT are pulled to V_SS, and once the fault has been removed, the fault clear timer begins. Figure 12 shows that

R_RCINis connected between the V_CCand the RCIN pin, while C_RCINis placed between the RCIN and V_SSpins.

Figure 11: RCIN and FAULT pin waveforms

Figure 12: Programming the fault clear timer

The design guidelines for this network are shown in Table 3.

≤1 nF

Ceramic

C_RCIN

0.5 Mꢂ to 2 Mꢂ

>> R_ON,RCIN

R_RCIN

Table 3: Design guidelines

The length of the fault clear time period can be determined by using the formula below.

v_C(t) = V_f(1ꢀe^ꢀt/RC

)

t_FLTCLR= ꢀ(R_RCINC_RCIN)ln(1ꢀV_RCIN,TH/V_CC

)

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IRS23365DM

OverꢀCurrent Protection

The IRS23365D HVICs are equipped with an ITRIP input pin. This functionality can be used to detect overꢀcurrent events in

the DCꢀ bus. Once the HVIC detects an overꢀcurrent event through the ITRIP pin, the outputs are shutdown, a fault is

reported through the FAULT pin, and RCIN is pulled to V_SS

.

The level of current at which the overꢀcurrent protection is initiated is determined by the resistor network (i.e., R₀, R₁, and R₂)

connected to ITRIP as shown in Figure 13, and the ITRIP threshold (V_IT,TH+). The circuit designer will need to determine the

maximum allowable level of current in the DCꢀ bus and select R₀, R₁, and R₂such that the voltage at node V_Xreaches the

overꢀcurrent threshold (V_IT,TH+) at that current level.

V_IT,TH+= R₀I_DCꢀ(R₁/(R₁+R₂))

Figure 13: Programming the overꢀcurrent protection

For example, a typical value for resistor R₀could be 50 mꢂ. The voltage of the ITRIP pin should not be allowed to exceed 5

V; if necessary, an external voltage clamp may be used.

OverꢀTemperature Shutdown Protection

The ITRIP input of the IRS23365D can also be used to detect overꢀtemperature events in the system and initiate a shutdown

of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the

resistor network as shown in Figure 14 and select the maximum allowable temperature.

This network consists of a thermistor and two standard resistors R₃and R₄. As the temperature changes, the resistance of the

thermistor will change; this will result in a change of voltage at node V_X. The resistor values should be selected such the

voltage V_Xshould reach the threshold voltage (V_IT,TH+) of the ITRIP functionality by the time that the maximum allowable

temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.

When using both the overꢀcurrent protection and overꢀtemperature protection with the ITRIP input, ORꢀing diodes (e.g.,

DL4148) can be used. This network is shown in Figure 15; the ORꢀing diodes have been labeled D₁and D₂.

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IRS23365DM

Figure 14: Programming overꢀtemperature

protection

Figure 15: Using overꢀcurrent protection and overꢀ

temperature protection

Truth Table: Undervoltage lockout, ITRIP, and ENABLE

Table 4 provides the truth table for the IRS23365D. The first line shows that the UVLO for V_CChas been tripped; the FAULT

output has gone low and the gate drive outputs have been disabled. is not latched in this case and when V_CCis greater

V_CCUV

than

, the FAULT output returns to the high impedance state.

V_CCUV

The second case shows that the UVLO for V_BShas been tripped and that the highꢀside gate drive outputs have been disabled.

After V_BSexceeds the , HO will stay low until the HVIC input receives a new rising transition of HIN. The third

V_BSUVthreshold

case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and

that the gate drive outputs have been disabled and a fault has been reported through the fault pin. In the last case, the HVIC

has received a command through the EN input to shutdown; as a result, the gate drive outputs have been disabled.

VCC

VBS

—

ITRIP

—

EN

—

RCIN

High

Low

FAULT

0

High impedance

0

LO

0

LIN

0

HO

0

HIN

0

<

UVLO V_CC

UVLO V_BS

Normal operation

ITRIP fault

V_CCUV

15 V

<

0 V

>V_ITRIP

0 V

5 V

0 V

V_BSUV

15 V

EN command

High

High impedance

0

Table 4: IRS23365D UVLO, ITRIP, EN, RCIN, & FAULT truth table

Advanced Input Filter

The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise

spikes and short pulses. This input filter has been applied to the HIN, LIN, and EN inputs. The working principle of the new

filter is shown in Figures 16 and 17.

Figure 16 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1)

show an input signal with a duration much longer then t_FIL,IN; the resulting output is approximately the difference between the

input signal and t_FIL,IN

.

The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then

t_FIL,IN; the resulting output is approximately the difference between the input signal and t_FIL,IN

.

Figure 17 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms

(Example 1) show an input signal with a duration much longer then t_FIL,IN; the resulting output is approximately the same

duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer

then t_FIL,IN; the resulting output is approximately the same duration as the input signal.

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3 December, 2012

IRS23365DM

Figure 16: Typical input filter

Figure 17: Advanced input filter

ShortꢀPulse / Noise Rejection

This device’s input filter provides protection against shortꢀpulses (e.g., noise) on the input lines. If the duration of the input

signal is less than t_FIL,IN, the output will not change states. Example 1 of Figure 18 shows the input and output in the low state

with positive noise spikes of durations less than t_FIL,IN; the output does not change states. Example 2 of Figure 18 shows the

input and output in the high state with negative noise spikes of durations less than t_FIL,IN; the output does not change states.

Figure 18: Noise rejecting input filters

Figures 19 and 20 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses.

The input filter characteristic is shown in Figure 19; the left side illustrates the narrow pulse ON (short positive pulse)

characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The xꢀaxis of Figure 19 shows

the duration of PW_IN, while the yꢀaxis shows the resulting PW_OUTduration. It can be seen that for a PW_INduration less than

t_FIL,IN, that the resulting PW_OUTduration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PW_IN

duration exceed t_FIL,IN, that the PW_OUTdurations mimic the PW_INdurations very well over this interval with the symmetry

improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for the

highꢀside inputs be ≥ 500 ns.

The difference between the PW_OUTand PW_INsignals of both the narrow ON and narrow OFF cases is shown in Figure 20; the

careful reader will note the scale of the yꢀaxis. The xꢀaxis of Figure 20 shows the duration of PW_IN, while the yꢀaxis shows the

resulting PW_OUT–PW_INduration. This data illustrates the performance and near symmetry of this input filter.

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3 December, 2012

IRS23365DM

Figure 19: IRS23365D input filter characteristic

Figure 20: Difference between the input pulse and the output pulse

Integrated Bootstrap Functionality

The new IRS23365D family features integrated highꢀvoltage bootstrap MOSFETs that eliminate the need of the external

bootstrap diodes and resistors in many applications.

There is one bootstrap MOSFET for each highꢀside output channel and it is connected between the V_CCsupply and its

respective floating supply (i.e., V_B1, V_B2, V_B3); see Figure 21 for an illustration of this internal connection.

The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and it has a limited source current due

to R_BS. The V_BSvoltage will be charged each cycle depending on the onꢀtime of LO and the value of the C_BScapacitor, the

drainꢀsource (collectorꢀemitter) drop of the external IGBT (or MOSFET), and the lowꢀside freeꢀwheeling diode drop.

The bootstrap MOSFET of each channel follows the state of the respective lowꢀside output stage (i.e., the bootstrap MOSFET

is ON when LO is high, it is OFF when LO is low), unless the V_Bvoltage is higher than approximately 110% of V_CC. In that

case, the bootstrap MOSFET is designed to remain off until V_Breturns below that threshold; this concept is illustrated in Figure

22.

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3 December, 2012

IRS23365DM

V_B1

V_CC

V_B2

V_B3

Figure 21: Internal bootstrap MOSFET connection

Figure 22: Bootstrap MOSFET state diagram

A bootstrap MOSFET is suitable for most of the PWM modulation schemes and can be used either in parallel with the external

bootstrap network (i.e., diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of

the external bootstrap network may have some limitations. An example of this limitation may arise when this functionality is

used in nonꢀcomplementary PWM schemes (typically 6ꢀstep modulations) and at very high PWM duty cycle. In these cases,

superior performances can be achieved by using an external bootstrap diode in parallel with the internal bootstrap network.

Bootstrap Power Supply Design

For information related to the design of the bootstrap power supply while using the integrated bootstrap functionality of the

IRS23365D, please refer to Application Note 1123 (ANꢀ1123) entitled “Bootstrap Network Analysis: Focusing on the Integrated

Bootstrap Functionality.” This application note is available at www.irf.com.

For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode) please refer

to Design Tip 04ꢀ4 (DT04ꢀ4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is available at www.irf.com.

Separate Logic and Power Grounds

The IRS23365D has separate logic and power ground pin (V_SSand COM respectively) to eliminate some of the noise

problems that can occur in power conversion applications. Current sensing shunts are commonly used in many applications

for power inverter protection (i.e., overꢀcurrent protection), and in the case of motor drive applications, for motor current

measurements. In these situations, it is often beneficial to separate the logic and power grounds.

Figure 23 shows a HVIC with separate V_SSand COM pins and how these two grounds are used in the system. The V_SSis

used as the reference point for the logic and overꢀcurrent circuitry; V_Xin the figure is the voltage between the ITRIP pin and

the V_SSpin. Alternatively, the COM pin is the reference point for the lowꢀside gate drive circuitry. The output voltage used to

drive the lowꢀside gate is V_LOꢀCOM; the gateꢀemitter voltage (V_GE) of the lowꢀside switch is the output voltage of the driver

minus the drop across R_G,LO

.

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3 December, 2012

IRS23365DM

DC+ BUS

D_BS

V_B

(x3)

V_CC

C_BS

HO

R_G,HO

(x3)

V_S

(x3)

V_S1

V_S2

V_S3

LO

(x3)

R_G,LO

ITRIP

+

V_GE1

V_GE2

V_GE3

ꢀ

V_SS

COM

R₂

R₀

+

R₁

V_X

ꢀ

DCꢀ BUS

Figure 23: Separate V_SSand COM pins

Tolerant to Negative V_STransients

A common problem in today’s highꢀpower switching converters is the transient response of the switch node’s voltage as the

power switches transition on and off quickly while carrying a large current. A typical 3ꢀphase inverter circuit is shown in Figure

24; here we define the power switches and diodes of the inverter.

If the highꢀside switch (e.g., the IGBT Q1 in Figures 25 and 26) switches off, while the U phase current is flowing to an

inductive load, a current commutation occurs from highꢀside switch (Q1) to the diode (D2) in parallel with the lowꢀside switch of

the same inverter leg. At the same instance, the voltage node V_S1, swings from the positive DC bus voltage to the negative

DC bus voltage.

Figure 24: Three phase inverter

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IRS23365DM

DC+ BUS

Q1

ON

I_U

V_S1

D2

Q2

OFF

DCꢀ BUS

Figure 25: Q1 conducting

Figure 26: D2 conducting

Also when the V phase current flows from the inductive load back to the inverter (see Figures 27 and 28), and Q4

IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2,

swings from the positive DC bus voltage to the negative DC bus voltage.

Figure 27: D3 conducting

Figure 28: Q4 conducting

However, in a real inverter circuit, the V_Svoltage swing does not stop at the level of the negative DC bus, rather it swings

below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”.

The circuit shown in Figure 29 depicts one leg of the three phase inverter; Figures 30 and 31 show a simplified illustration of

the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the

PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the highꢀside switch is on, V_S1is below the DC+ voltage by

the voltage drops associated with the power switch and the parasitic elements of the circuit. When the highꢀside power switch

turns off, the load current momentarily flows in the lowꢀside freewheeling diode due to the inductive load connected to V_S1(the

load is not shown in these figures). This current flows from the DCꢀ bus (which is connected to the COM pin of the HVIC) to

the load and a negative voltage between V_S1and the DCꢀ Bus is induced (i.e., the COM pin of the HVIC is at a higher potential

than the V_Spin).

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3 December, 2012

IRS23365DM

Figure 29: Parasitic Elements

Figure 30: V_Spositive

Figure 31: V_Snegative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3ꢀ5 V/ns. The negative V_Stransient voltage can

exceed this range during some events such as short circuit and overꢀcurrent shutdown, when di/dt is greater than in normal

operation.

International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications.

The IRS23365D has been seen to withstand large negative V_Stransient conditions on the order of ꢀ50 V for a period of 50 ns.

An illustration of the IRS23365D’s performance can be seen in Figure 32. This experiment was conducted using various loads

to create this condition; the curve shown in this figure illustrates the successful operation of the IRS2336D under these

stressful conditions. In case of ꢀV_Stransients greater then ꢀ20 V for a period of time greater than 100 ns; the HVIC is designed

to hold the highꢀside outputs in the off state for 4.5 ꢃs in order to ensure that the highꢀ and lowꢀside power switches are not on

at the same time.

Figure 32: Negative V_Stransient results for an International Rectifier HVIC

Even though the IRS23365D has been shown able to handle these large negative V_Stransient conditions, it is highly

recommended that the circuit designer always limit the negative V_Stransients as much as possible by careful PCB layout and

component use.

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3 December, 2012

IRS23365DM

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating

voltage pins (V_Band V_S) near the respective high voltage portions of the device.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage

floating side. The central exposed pad has to be connected to COM for better electrical performance.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 33). In order

to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as

much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collectorꢀtoꢀgate parasitic

capacitance. The parasitic autoꢀinductance of the gate loop contributes to developing a voltage across the gateꢀemitter, thus

increasing the possibility of a self turnꢀon effect.

Figure 33: Antenna Loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the V_CCand V_SSpins. This connection is

shown in Figure 34. A ceramic 1 ꢃF ceramic capacitor is suitable for most applications. This component should be placed as

close as possible to the pins in order to reduce parasitic elements

.

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3 December, 2012

IRS23365DM

Figure 34: Supply capacitor

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch

node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended

to 1) minimize the highꢀside emitter to lowꢀside collector distance, and 2) minimize the lowꢀside emitter to negative bus rail

stray inductance. However, where negative V_Sspikes remain excessive, further steps may be taken to reduce the spike. This

includes placing a resistor (5 ꢂ or less) between the V_Spin and the switch node (see Figure 35), and in some cases using a

clamping diode between V_SSand V_S(see Figure 36). See DT04ꢀ4 at www.irf.com for more detailed information.

Figure 36: V_Sresistor

Figure 37: V_Sclamping diode

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the

document number to quickly locate them. Below is a short list of some of these documents.

DT97ꢀ3: Managing Transients in Control IC Driven Power Stages

ANꢀ1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04ꢀ4: Using Monolithic High Voltage Gate Drivers

ANꢀ978: HV Floating MOSꢀGate Driver ICs

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3 December, 2012

IRS23365DM

Parameter Temperature Trends

Figures 38ꢀ59 provide information on the experimental performance of the IRS23365D HVIC. The line plotted in each figure

is generated from actual lab data. A small number of individual samples were tested at three temperatures (ꢀ40 ºC, 25 ºC,

and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data

point at each of the tested temperatures) that have been connected together to illustrate the understood temperature trend.

The individual data points on the curve were determined by calculating the averaged experimental value of the parameter

(for a given temperature).

1000

800

600

400

200

0

1000

800

600

400

200

0

Exp.

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 38: t_ONvs. temperature

Figure 39: t_OFFvs. temperature

600

450

300

150

0

1500

1200

900

600

300

0

Exp.

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 40: DT vs. temperature

Figure 41: t_ITRIPvs. temperature

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3 December, 2012

IRS23365DM

1200

1000

800

600

400

200

0

1000

800

600

400

200

0

Exp.

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 42: t_FLTvs. temperature

Figure 43: t_ENvs. temperature

60

40

20

0

60

40

20

0

Exp.

ꢀ50

ꢀ25

0

25

50

75

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 44: MT vs. temperature

Figure 45: MDT vs. temperature

60

40

20

0

16

12

8

Exp.

4

0

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

Temperature (^oC)

Figure 46: PM vs. temperature

Figure 47: I_ITRIP+vs. temperature

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3 December, 2012

IRS23365DM

5

4

3

2

1

0

120

100

80

60

40

20

0

Exp.

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 48: I_QCCvs. temperature

Figure 49: I_QBSvs. temperature

0.60

0.40

0.20

0.00

0.60

Exp.

0.40

0.20

0.00

Exp.

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

Temperature (^oC)

Figure 50: I_O+vs. temperature

Figure 51: I_Oꢀvs. temperature

12

10

8

12

10

8

Exp.

6

4

2

0

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

Temperature (^oC)

Figure 52: V_CCUV+vs. temperature

Figure 53: V_CCUVꢀvs. temperature

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3 December, 2012

IRS23365DM

10

9

10

9

Exp.

8

7

6

5

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 54: V_BSUV+vs. temperature

Figure 55: V_BSUVꢀvs. temperature

800

600

400

200

800

600

400

200

0

Exp.

EXP.

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 56: V_IT,TH+vs. temperature

Figure 57: V_IT,THꢀvs. temperature

100

80

60

40

20

0

100

80

60

40

20

0

Exp.

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 58: R_ON,RCINvs. temperature

Figure 59: R_ON,FLTvs. temperature

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IRS23365DM

Case outline drawing for: MLPQ7X7

34 www.irf.com

3 December, 2012

IRS23365DM

Tape and Reel Details: MLPQ7X7

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 48MLPQ7X7

Metric

Min

Imperial

Min

Code

A

B

C

D

E

F

G

H

Max

12.10

4.10

16.30

7.60

7.35

n/a

Max

0.476

0.161

0.641

0.299

0.289

n/a

11.90

3.90

15.70

7.40

7.15

1.50

0.474

0.153

0.618

0.291

0.281

0.059

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 48MLPQ7X7

Metric

Min

329.60

20.95

12.80

1.95

98.00

n/a

18.5

Imperial

Min

Code

A

B

C

D

E

F

G

H

Max

330.25

21.45

13.20

2.45

102.00

22.4

21.1

Max

13.001

0.844

0.519

0.096

4.015

0.881

0.83

12.976

0.824

0.503

0.767

3.858

n/a

0.728

0.645

16.4

18.4

0.724

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3 December, 2012

IRS23365DM

Part Marking Information

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3 December, 2012

IRS23365DM

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Form

Quantity

52

Tube/Bulk

IRS23365DMPbF

IRS23365D

MLPQ7x7 48L

Tape and Reel

3000

IRS23365DMTRPbF

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no

responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of

patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise

under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without

notice. This document supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technicalꢀinfo/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252ꢀ7105

Revision History

Date

Comment

09/28/11

10/11/11

Original document.

Iin+ and Iinꢀ updated

03/27/2012 New datasheet format

04/27/2012 Add explanation about exposed pad

37 www.irf.com

3 December, 2012


型号：	IRS23365DMPBF
厂家：	Infineon
描述：	Drives up to six IGBT/MOSFET power devices 双极性晶体管
文件：	总37页 (文件大小：594K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRS23365DMPBF [INFINEON]

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