IRS25401STRPBF_技术文档

September 8, 2010

Datasheet No – PD97524

IRS254(01,11)

LED BUCK REGULATOR CONTROL IC

Product Summary

Features

Topology

V_OFFSET

V_OUT

Buck

200V,600V

VCC

• 200 V (IRS25401) and 600 V (IRS25411) half

bridge driver

• Micropower startup (<500 μA)

• ±2% voltage reference

• 140 ns deadtime

I_o+& I _o-(typical)

0.5A/0.7A

50/30nS

140nS

• 15.6 V zener clamp on V_CC

• Frequency up to 500 kHz

• Auto restart, non-latched shutdown

• PWM dimmable

t_ON& t_OFF(typical)

Deadtime (typical)

• Small 8-Lead DIP/8-Lead SOIC packages

Packages

Typical Applications

LED drivers for lamp replacement

LED driver back end current regulator

8-Lead PDIP

8-LeadSOIC

IRS254(01,11)PbF

IRS254(01,11)SPbF

Typical Connection Diagram

VBUS

L2

VOUT+

RS1

RS2

DBOOT

IC1

VCC

VB

HO

VS

LO

CVCC1

1

2

3

4

8

7

6

5

ROV1

ROV2

COM

RG1

M1

M2

DCLAMP

DOV

CVCC2

CBUS2

CBOOT

L1

IFB

CBUS1

ENN

RG2

COUT

VOUT-

CEN

RF

RCS

ROUT

CF

COM

EN

DEN1

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IRS254(01,11)(S)

Page

3

Table of Contents

Description

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

lectrical Characteristics

Functional Block Diagram

Input/Output Pin Equivalent Circuit Diagram

Lead Definitions

5

6

7

8

9

10

12

17

18

19

20

Lead Assignments

Application Information and Additional Details

Package Details

Tape and Reel Details

Part Marking Information

Ordering Information

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2

IRS254(01,11)(S)

Description

The IRS254(01,11) are high voltage, high frequency buck control ICs for constant LED current regulation. They

incorporate a continuous mode time-delayed hysteretic buck regulator to directly control the average load current,

using an accurate on-chip bandgap voltage reference. These parts directly replace the IRS2540 and IRS2541

with improved latch up immunity.

The application is inherently protected against short circuit conditions, with the ability to easily add open-circuit

protection. An external high-side bootstrap circuit drives the buck switching element at high frequencies. A low-

side driver is also provided for synchronous rectifier designs. All functions are realized within a simple 8 pin DIP

or SOIC package.

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3

IRS254(01,11)(S)

Alternate application circuit using a single MOSFET

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4

IRS254(01,11)(S)

Qualification Information^†

Industrial^††

Comments: This family of ICs has passed JEDEC’s Industrial

qualification. IR’s Consumer qualification level is granted by

extension of the higher Industrial level.

Qualification Level

MSL2^†††260°C

SOIC8

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

Not applicable

(non-surface mount package style))

PDIP8

Class B

Machine Model

Human Body Model

(per JEDEC standard JESD22-A115)

ESD

Class 1C

(per EIA/JEDEC standard EIA/JESD22-A114)

Class I, Level A

(per JESD78)

Yes

IC Latch-Up Test

RoHS Compliant

†

††

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

Higher qualification ratings may be available should the user have such requirements. Please

contact your International Rectifier sales representative for further information.

Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

†††

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5

IRS254(01,11)(S)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The

thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol

Definition

Min

-0.3

V_B+ 0.3

V_S– 0.3

-0.3

-20

Max

225

625

Units

IRS25401

IRS25411

V_B

High-side floating well supply voltage

V_S

V_HO

V_LO

V_IFB

V_ENN

I_CC

High-side floating well supply return voltage

Floating gate drive output voltage

Low-side output voltage

V_B+ 0.3

V_CC+ 0.3

20

V

Feedback voltage

Enable voltage

†

Supply current ( )

mA

dV/dt

Allowable offset voltage slew rate

-50

50

V/ns

(8-Pin DIP)

(8-Pin SOIC)

(8-Pin DIP)

(8-Pin SOIC)

---

-55

---

1

Package power dissipation @ T_A≤+25 ºC

P_D

W

0.625

T_JMAX-T_A)/R_THJA

P_D= (

125

200

150

300

R_ΘJA

Thermal resistance, junction to ambient

ºC/W

T_J

T_S

T_L

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

ºC

†

: This IC contains a zener clamp structure between the chip V_CCand COM, with a nominal breakdown voltage

of 15.6 V. Please note that this supply pin should not be driven by a low impedance DC power source greater

than V_CLAMPspecified in the electrical characteristics section.

Recommended Operating Conditions

For proper operation the device should be used within recommended conditions.

Symbol

V_BS

Definition

High-side floating supply voltage

Steady state high-side floating supply offset

voltage

Min

V_CC-0.7

-1

Max

V_CLAMPHS

200

Units

IRS25401

IRS25411

V_S

V

-1

600

V_CC

I_CC

T_J

Supply voltage

Supply current

Junction temperature

V_CCUV+

-Note 2

-25

V_CLAMP

10

125

††

: Sufficient current should be supplied to

to keep the internal 15.6 V zener regulating at V_CLAMP.

V_CC

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6

IRS254(01,11)(S)

Electrical Characteristics

V_CC= V_BS= V_BIAS= 14 V +/- 0.25 V, C_LO=C_HO=1000 pF, C_VCC=C_VBS=0.1 μF, T_A=25 °C unless otherwise

specified.

Symbol

Definition

Min

Typ

Max Units

Test Conditions

Supply Characteristics

V

_CCsupply undervoltage positive going

threshold

_CCsupply undervoltage negative going

V_CCUV+

V_CCUV-

V_UVHYS

8.0

6.5

1.0

9.0

7.5

1.2

10.0

8.5

V

_CCrising from 0 V

V

V_CCfalling from 14 V

threshold

V_CCsupply undervoltage lockout

hysteresis

2.0

I_QCCUV

I_QCCENN

I_QCC

UVLO mode quiescent current

Diesabled mode quiescent current

Quiescent V_CCsupply current

---

50

1.0

150

2.0

µA V_CC=6 V

EN>V_ENTH+

I_FB= 1 V

Duty Cycle = 50%

mA

I_CC50k

V_CCsupply current, f = 50 kHz

V_CCzener clamp voltage

---

2.0

3.0

f = 50 kHz

V_CLAMP

14.6

15.6 16.6

V

I_CC= 10 mA

Floating Supply Characteristics

I_QBS0Quiescent V_BSsupply current

I_QBS1Quiescent V_BSsupply current

_BSsupply undervoltage positive going

threshold

_BSsupply undervoltage negative going

---

0.05

1.0

2.0

V_HO= V_S

I_FB= 0 V

mA

V

V_BSUV+

V_BSUV-

I_LK

6.5

6.0

7.5

7.0

1

8.5

8.0

50

V

threshold

IRS25401:V_B=V_S=200 V

IRS25411:V_B=V_S=600 V

I_CC= 10 mA

Offset supply leakage current

---

µA

V

V_CLAMPHSV_BShigh side zener clamp voltage

24.4

26.0 27.6

Current Control Operation

V_ENNTH+

V_ENNTH-

V_0.5

V_IFBTH

f

ENN pin positive threshold

ENN pin negative threshold

0.5 V voltage reference (die level test)

IFB pin threshold

2.5

1.7

490

455

---

2.7

2.0

500

3.0

2.3

510

540

---

V

mV

kHz

Maximum frequency

Gate Driver Output Characteristics

V_OL

V_OH

t_r

Low level output voltage (HO or LO)

High level output voltage (HO or LO)

Turn-on rise time

Turn-off fall time

---

COM

V_CC

50

---

120

50

V

ns

t_f

30

Output source/sink short circuit pulsed

current

I_O+/-

---

0.5/0.7 ---

A

DT

t_LO,ON

t_LO,OFF

Deadtime

---

140

320

180

---

I_FB= 50 kHz square

wave, 200 mV pk-pk

DC offset = 400 mV

Duty Cycle = 50%

Delay between V_IFB>V_IFBTHand LO turn-on

Delay between V_IFB<V_IFBTHand LO turn-off

Delay between V_IFB<V_IFBTHand HO turn-

on

Delay between V_IFB>V_IFBTHand HO turn-

off

ns

t_HO,ON

---

320

180

---

t_HO,OFF

Watchdog timer

t_WD

P_WWD

Watchdog timer period

LO pulse width

---

20

1.0

---

μs

I_FB=1 V

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7

IRS254(01,11)(S)

Functional Block Diagram

8

7

6

VB

HO

VS

PULSE

FILTER &

LATCH

DELAY

LEVEL

SHIFT

3

IFB

1

5

VCC

LO

UVN

DELAY

UVLO

15.6 V

4

ENN

2 V

BANDGAP

REFERENCE

100 K

Watchdog

20 ?S

1 ?S Pulse

Generator

0. 5 V

Timer

2

COM

Values in block diagram are typical values

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8

IRS254(01,11)(S)

Input/Output Pin Equivalent Circuit Diagrams: IRS25401/IRS25411

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9

IRS254(01,11)(S)

Lead Definitions

PIN #

Symbol

Description

1

2

3

4

5

6

7

8

VCC

COM

IFB

ENN

LO

VS

HO

VB

Supply voltage

IC power & signal ground

Current feedback

Disable outputs (LO=High, HO=Low)

Low–side gate driver output

High–side floating return

High–side gate driver output

High–side gate driver floating supply

Lead Assignments

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IRS254(01,11)(S)

State Diagram

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11

IRS254(0,1)(S)PbF

determined as follows. When the inductance value

is large enough to maintain a low ripple on I_FB, I_out,avg

can be calculated:

Application Information and Additional

Details

Operating Mode

VIFBTH

The IRS254(01,11) operates as a time-delayed

hysteritic buck controller. During normal operating

conditions the output current is regulated via the IFB

pin voltage (nominal value of 500 mV). This feedback

is compared to an internal high precision bandgap

voltage reference. An on-board dV/dt filter has also

been used to ignore erroneous transitioning.

Iout(avg) =

RCS

Once the supply to the IC reaches V_CCUV+, the LO

output is held high and the HO output low for a

predetermined period of time. This initiates charging of

the bootstrap capacitor, establishing the V_BSfloating

supply for the high-side output. The IC then begins

toggling HO and LO outputs as needed to regulate the

current.

(A)

(B)

Fig.2 (A) Storing Energy in Inductor

(B) Releasing Inductor Stored Energy

50%

HO

50%

t_HO_off

t_HO_on

DT2

Iout

HO

LO

DT1

50%

LO

t_LO_off

t_LO_on

IFB

IFBTH

Fig.1 IRS254(01,11) Control Signals, Iavg=1.2 A

Fig.3 IRS254(0,1) Time Delayed Hysterisis

As long as V_IFBis below V_IFBTH, HO is on, modulated by

the watchdog timer described below, which maintains

charge for the floating high side on the bootstrap

The control method is hysteretic with a free running

frequency, which enables average current regulation

in constrast to a fixed frequency scheme providing

peak current regulation only. This reduces the part

count since there is no need for frequency setting

components and also provides an inherently stable

system, which acts as a dynamic current source.

capacitor. The load is receiving current from V_BUS

,

which simultaneously stores energy in the inductor, as

V_IFBincreases, unless the load is open circuit. Once

V_IFBcrosses V_IFBTH, the control loop switches HO off

after the delay t_HO,OFF. When HO switches off, LO will

turn on after the deadtime (DT), the inductor then

releases its stored energy into the load and V_IFBstarts

decreasing. When V_IFBdrops below V_IFBTHagain, the

control loop switches HO on after the delay t_HO,ONand

LO off after the delay t_HO,ON+ DT. The switching

continues to regulate the current at an average value

A deadtime of approximately 140 ns between the two

gate drive signals is incoporated to prevent shoot-

through. The deadtime has been adjusted to maintain

precise current regulation, while still preventing

shoot-through.

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12

IRS254(0,1)(S)PbF

Watchdog Timer

Disable (ENN) Pin

During an open circuit condition, without the watchdog

timer, the HO output would remain high at all times and

the charge stored in the bootstrap capacitor C_BOOT

would gradually discharge the floating power supply for

the high-side driver, which would then be unable to fully

switch on the upper MOSFET causing high losses. To

maintain sufficient charge on the bootstrap capacitor, a

The disable pin can be used for PWM dimming and

open-circuit protection. When the ENN pin is held

low, the chip remains in a fully functional state with no

alterations to the operating environment. To disable

the control feedback and regulation, a voltage greater

than V_ENTH(approximately 2.5 V) needs to be applied

to the ENN pin. With the chip in a disabled state, HO

output will remain low, whereas the LO output will

remain high to prevent V_Sfrom floating, in addition to

maintaining charge on the bootstrap capacitor. The

threshold for disabling the IRS254(01,11) has been

set to 2.5 V to enhance noise immunity. This 2.5 V

threshold also provides compatibility for a drive signal

from a microcontroller.

watchdog timer has been implemented.

In the

condition where V_IFBremains below V_IFBTH, the HO

output is driven low after 20 μs and the LO output

forced high. This toggling of the outputs will last for

approximately 1 μs to maintain and replenish sufficient

charge on C_BOOT

.

Dimming Mode

To achieve dimming, a signal with constant frequency

and adjustable duty cycle can be fed into the ENN

pin. There is a direct linear relationship between the

average load current and duty cycle. If the ratio is

50%, 50% of the maximum set light output will be

realized. Likewise if the ratio is 30%, 70% of the

maximum set light output will be realized. A

sufficiently high frequency of the dimming signal must

be chosen to avoid noticeable flashing or “strobe

light” effect. A signal above 120Hz up to 5kHz is

sufficient.

HO

LO

The ENN pin logic is inverted to provide enable low

so that the default state is with the IC running.

The minimum amount of dimming achievable (light

output approaches 0%) will be determined by the “on”

time of the HO output, when in a fully functional

regulating state. To maintain reliable dimming, it is

recommended to keep the “off” time of the enable

signal at least 10 times that of the HO “on” time. For

example, if the application is running at 75 kHz with

an input voltage of 100 V and an output voltage of 20

V, the HO “on” time will be approximately 2.7 µs

according to standard buck topology theory. This will

set the minimum “off” time of the enable signal to 27

µs.

Fig.4 Illustration of Watchdog Timer

Bootstrap Capacitor and Diode

The bootstrap capacitor value needs to be selected so

that it maintains sufficient charge for at least the

approximately 20 μs interval until the watchdog timer

allows the capacitor to recharge. If the capacitor value

is too small, it will discharge in less than 20 μs. The

typical bootstrap capacitor is approximately 100 nF.

The bootstrap diode must be a fast recovery or ultrafast

recovery component to maintain good efficiency. Since

the cathode of the bootstrap diode will be switching

between zero and to the high voltage bus, the reverse

recovery time of this diode is critical. For additional

information concerning the bootstrap components, refer

to the Design Tip (DT 98-2), “Bootstrap Component

Selection For Control ICs” at www.irf.com under Design

Support

V_out

V_in

20V

Duty Cycle =

∗100 =

*100 = 20%

100V

1

HO_{on time}= 20%*

≈ 2.7μs

75kHz

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13

IRS254(0,1)(S)PbF

to form the voltage clamp. The repetition of the

spikes can be reduced by simply increasing the

capacitor size.

Enable Duty Cycle Relationship to Light Output

100

90

80

70

60

50

40

30

20

10

0

The two resistors form a voltage divider for the

output, which is then fed into the cathode of the zener

diode. The diode will only conduct, flooding the

enable pin, when its nominal voltage is exceeded.

The chip will enter a disabled state once the divider

network produces a voltage at least 2.5 V greater

than the zener rating. The capacitor serves only to

filter and slow the transients/switching at the positive

output terminal. The clamped output voltage can be

determined by the following analysis. The choice of

capacitor is at the designer’s discretion.

0

10

20

30

40

50

60

70

80

90

100

Percentage of Light Output

Fig.5 Light Output vs Enable Pin Duty Cycle

This scheme will not be adequate in all applications.

An improved method is described in IRPLLED1 Rev

D reference design documentation.

EN

(

2.5V + DZ)(R₁+ R₂

)

V_out

=

R₂

DZ = Zener Diode Nominal Rated Voltage

HO

LO

Fig.6 IRS254(01,11) Dimming Signals

Open Circuit Protection Mode

There are several

methods of providing

over voltage protection

at the output if needed.

Vout

R1

IFB

EN

The

simple method uses a

voltage divider,

capacitor, and zener

diode, the output

following

very

3

4

R2

Fig.8 Open Circuit Fault Signals, with Clamp

Fig.7 Open Circuit

Protection Scheme

voltage can be clamped

at any desired value. In open-

circuit condition without any

Under-voltage Lock-out Mode

The under-voltage lock-out mode (UVLO) is defined

output clamp, the positive output terminal may reach a

high DC voltage. Switching will still occur between the

HO and LO outputs, whether due to the output voltage

clamp or the watchdog timer. Transients and switching

will be observed at the positive output terminal as seen

in Fig. 8. The difference in signal shape, between the

output voltage and the I_FB, is due to the capacitor used

as the state IRS254(01,11) is in when _CCis below

V

the turn-on threshold of the IC. During startup

conditions, if the IC supply remains below _CCUV+, the

V

IRS254(01,11) will enter the UVLO mode. This state

is very similar to when the IC has been disabled via

control signals, except that LO is also held low.

When the supply is increased to V_CCUV+, the IC enters

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14

IRS254(0,1)(S)PbF

the normal operation mode. If already in normal

operation, the IC does not enter UVLO unless the

has a significant effect on the operating frequency or

current regulation, as can be seen in Figs. 13 and 14.

supply voltage falls below V_CCUV-

.

-

Inductance Selection

400

390

To maintain tight hysteretic current regulation the

inductor and output capacitor C_OUT(in parallel with the

LEDs) need to be large enough to maintain the supply to

the load during t_HO,ONand avoid significant

undershooting of the load current, which in turn causes

the average current to fall below the desired value.

380

470uH

370

680uH

1mH

1.5mH

360

350

340

330

First, consider the effect of the inductor when there is no

output capacitor to clearly demonstrate the impact of the

inductor. In this case, the load current is identical to the

inductor current. Fig. 9 shows how the inductor value

impacts the frequency over a range of input voltages. As

can be seen, the input voltage has a great impact on the

frequency and the inductor value has the greatest impact

at reducing the frequency for smaller input voltages.

30

80

130

180

Vin (V)

Fig.10 Current Regulation for Chosen Inductances

I_out= 350 mA, V_out= 16.8 V

400

380

360

340

425

375

470uH

320

300

280

260

240

220

200

680uH

1mH

470uH

325

1.5mH

680uH

1mH

275

1.5mH

225

175

13

18

23

28

33

Vout (V)

30

80

130

180

Fig.11 Frequency Response for Chosen Inductances

I_out= 350 mA, V_in= 50 V

Vin (V)

Fig.9 Frequency Response for Chosen Inductances

I_out= 350 mA, V_out= 16.8 V

345

343

341

339

Fig. 10 shows how the variation in load current increases

over a span of input voltages, as the inductance is

decreased. Fig. 11 shows the variation of frequency over

different output voltages and different inductance values.

Finally Fig. 12 shows how the load current variation

increases with lower inductance over a range of output

voltages.

470uH

337

335

333

331

329

327

325

680uH

1mH

1.5mH

13

18

23

28

33

The output capacitor can be used simultaneously to

achieve the target frequency and current control

accuracy. Fig. 11 shows how the capacitance reduces

the frequency over a range of input voltage. A small

capacitance of 4.7 μF has a large effect on reducing the

frequency. Fig. 12 shows how the current regulation is

also improved with the output capacitance. There is a

point at which continuing to add capacitance no longer

Vout (V)

Fig.12 Current Regulation for Chosen Inductances

_out= 350 mA, V_in= 50 V

I

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15

IRS254(0,1)(S)PbF

0uF

1000

100

10

4.7uF

10uF

22uF

33uF

47uF

30

50

70

90

110

130

150

170

Vin (V)

Fig. 13 I_out= 350 mA, V_out= 16.8 V, L = 470 μH

Fig. 15 I_out= 350 mA, V_in= 100 V, V_out= 16.85 V, L = 470 μH,

C _out= 33 μF

400

350

300

250

200

150

100

50

The resistance between V_BUSand V_CCsupply should

be large enough to minimize the current sourced

directly from the input voltage line; value should be on

the order of hundreds of kΩ. Through the supply

40V

100V

160V

resistor, a current will flow to charge the

V

CC

capacitor. Once the capacitor is charged up to the

threshold, the IRS254(01,11) enters the micro

V

CCUV+

0

10

20

30

40

50

start-up regime and begins to operate, activating the

LO and HO outputs. After the first few cycles of

switching, the resistor connected between the output

Capacitance (uF)

Fig. 14 I _out= 350 mA, V_out= 16.8 V, L = 470 μH

and

will take over and source all necessary

V_CC

current for the IC. The resistor connecting the output

to the supply should be carefully designed according

to its power rating.

The addition of the C_OUTincreases the amount of

energy that can be stored in the output stage, which

also means it can supply current for an increased

period of time. Therefore by slowing down the di/dt

transients in the load, the frequency is effectively

decreased.

V_out−15.6V

RS2 =

10mA

P_{RS2_ Rated}

P_RS2= (10mA)²RS2 ≤

2

With the C_OUTcapacitor, the inductor current is no

longer identical to that seen in the load. The inductor

current will still have a perfectly triangular shape, where

as the load will see the same basic trend in the current,

but all sharp corners will be rounded with all peaks

significantly reduced, as can be seen in Fig. 15

Icc ≈ 10mA

Supply

V

CC

Since the IRS254(01,11) is rated for 200 V (or 600 V),

V_BUScan reach values of this magnitude. If a supply

resistor to V_BUSis used, it can experience high power

losses. For higher voltage applications if the output

voltage is above VCCUV+ plus one diode drop an

alternate V_CCsupply scheme utilizing the micro-power

start-up and a resistor feed-back from the output can to

be implemented, as seen in Fig. 16.

Fig. 16 Alternate Supply Diagram

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16

IRS254(0,1)(S)PbF

Package Details

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17

IRS254(0,1)(S)PbF

Tape and Reel Details

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 8SOICN

Metric

Imperial

Min

0.311

0.153

0.46

Code

A

B

C

D

E

F

G

H

Min

7.90

3.90

11.70

5.45

6.30

5.10

1.50

Max

8.10

4.10

12.30

5.55

6.50

5.30

n/a

Max

0.318

0.161

0.484

0.218

0.255

0.208

n/a

0.214

0.248

0.200

0.059

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 8SOICN

Metric

Imperial

Code

A

B

C

D

E

F

G

H

Min

329.60

20.95

12.80

1.95

98.00

n/a

14.50

12.40

Max

330.25

21.45

13.20

2.45

102.00

18.40

17.10

14.40

Min

12.976

0.824

0.503

0.767

3.858

n/a

Max

13.001

0.844

0.519

0.096

4.015

0.724

0.673

0.566

0.570

0.488

www.irf.com

18

IRS254(0,1)(S)PbF

Part Marking Information

SOIC

PDIP

www.irf.com

19

IRS254(0,1)(S)PbF

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Form

Quantity

PDIP8

SOIC8

Tube/Bulk

50

IRS25401PBF

IRS25401SPBF

IRS25401STRPBF

IRS25411PBF

IRS25401

IRS25411

Tube/Bulk

95

Tape and Reel

2500

PDIP8

SOIC8

Tube/Bulk

50

Tube/Bulk

95

IRS25411SPBF

IRS25411STRPBF

Tape and Reel

2500

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility

for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of

other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any

patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This

document supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

www.irf.com

20


型号：	IRS25401STRPBF
厂家：	Infineon
描述：	LED BUCK REGULATOR CONTROL IC LED降压稳压器控制IC 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件：	总20页 (文件大小：519K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRS25401STRPBF [INFINEON]

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