IRS26072DSPBF_11_技术文档

Data Sheet No. PD 97408B

May 30, 2011

IRS26072DSPbF

HIGH AND LOW SIDE DRIVER

Product Summary

Features

•

Floating channel designed for bootstrap operation

Topology

high and low side driver

≤ 600 V

Integrated bootstrap diode suitable for Complimentary

PWM switching schemes only

V_OFFSET

•

IRS26072DSPBF is suitable for sinusoidal motor control

applications

IRS26072DSPBF is NOT recommended for

Trapezoidal motor control applications

Fully operational to 600 V

Tolerant to negative transient voltage, dV/dt immune

Gate drive supply range from 10 V to 20 V

UnderꢀVoltage lockout for both channels

3.3 V, 5 V, and 15 V input logic compatible

Matched propagation delay for both channels

Lower di/dt gate driver for better noise immunity

Outputs in phase with inputs

V_OUT

10 V – 20 V

I_o+& I _oꢀ(typical)

t_ON& t_OFF(typical)

200 mA & 350 mA

200 ns

•

Package Options

RoHS compliant

8ꢀLead SOIC

Typical Applications

•

Motor Control

Air Conditioners/ Washing Machines

General Purpose Inverters

Micro/Mini Inverter Drivers

Typical Connection Diagram

Up to600 V

Vcc

HIN

Vcc

VB

HO

HIN

LIN

TO

LOAD

VS

LO

LIN

COM

IRS26072D

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IRS26072DSPbF

Table of Contents

Page

3

Description

Simplified Block Diagram

Typical Application Diagram

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

Static Electrical Characteristics

Dynamic Electrical Characteristics

Functional Block Diagram

Input/Output Pin Equivalent Circuit Diagram

Lead Definitions

3

4

5

6

7

8

9

10

11

21

26

27

28

29

Lead Assignments

Application Information and Additional Details

Parameter Temperature Trends

Package Details

Tape and Reel Details

Part Marking Information

Ordering Information

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IRS26072DSPbF

Description

The IRS26072D is a high voltage, high speed power MOSFET and IGBT driver with independent high and low

side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized

monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V. The output

drivers feature a highꢀpulse current buffer stage designed for minimum driver crossꢀconduction. The floating

channel can be used to drive Nꢀchannel power MOSFETs or IGBTs in the high side configuration up to 600 V.

Simplified Block Diagram

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IRS26072DSPbF

Typical Application Diagram

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IRS26072DSPbF

Qualification Information^†

Qualification Level

Industrial^††

Comments: This IC has passed JEDEC industrial

qualification. IR consumer qualification level is granted by

extension of the higher Industrial level.

MSL2 , 260°C

(per IPC/JEDEC JꢀSTDꢀ020)

Moisture Sensitivity Level

Class 2

(per JEDEC standard JESD22ꢀA114)

Class B

Human Body Model

Machine Model

ESD

(per EIA/JEDEC standard EIA/JESD22ꢀA115)

Class I, Level A

(per JESD78)

IC Latch-Up Test

RoHS Compliant

Yes

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information.

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IRS26072DSPbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM unless otherwise specified. The thermal resistance and

power dissipation ratings are measured under board mounted and still air conditions.

Symbol

Definition

Min.

Max.

Units

V_B

V_S

High side floating supply voltage

High side floating supply offset voltage

High side floating output voltage

Low side and logic fixed supply voltage

Low side output voltage

ꢀ0.3

620

V_Bꢀ 20^†

V_Sꢀ 0.3

ꢀ0.3

V_B+ 0.3

V_HO

V

20^†

V_CC+ 0.3

—

V_CC

V_LO

V_IN

PW_HIN

dV_S/dt

ꢀ0.3

500

Logic and analog input voltages

Highꢀside input pulse width

ns

Allowable offset supply voltage slew rate

—

50

V/ns

P_D

—

0.625

W

Package power dissipation @ TA ≤ +25°C

Rth_JA

T_J

T_S

Thermal resistance, junction to ambient

Junction temperature

Storage temperature

—

ꢀ50

200

150

°C/W

°C

T_L

Lead temperature (soldering, 10 seconds)

—

300

†

All supplies are fully tested at 25 V. An internal 20 V clamp exists for each supply.

Recommended Operating Conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters are

absolute voltages referenced to COM unless otherwise specified. The V_Soffset ratings are tested with all supplies

biased at 15 V.

Symbol

Definition

Min.

Max.

Units

V_B

V_S

High side floating supply voltage

Static high side floating supply offset voltage^†

Transient high side floating supply offset voltage^††

High side floating output voltage

Low side and logic fixed supply voltage

Low side output voltage

V_S+10

ꢀ8

V_S+ 20

600

V_B

V_S(t)

V_HO

V_CC

V_LO

V_IN

ꢀ50

V_S

V

10

20

0

V_CC

125

Logic input voltage

0

T_A

Ambient temperature

ꢀ40

°C

†

V

Logic operation for _Sof –8 V to 600 V. Logic state held for _Sof –8 V to –V_BS.

†† Operational for transient negative V_Sof ꢀ50 V with a 50 ns pulse width. Guaranteed by design. Refer to the

Application Information section of this datasheet for more details.

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IRS26072DSPbF

Static Electrical Characteristics

(V_CCꢀCOM) = (V_BꢀV_S) = 15 V and T_A= 25 ^oC unless otherwise specified. The V_INand I_INparameters are referenced

to COM. The V_Oand I_Oparameters are referenced to COM and V_Sand are applicable to the output leads LO and

HO respectively. The

and

parameters are referenced to COM and V_Srespectively.

V_CCUV

V_BSUV

Symbol

Definition

Min. Typ. Max. Units

Test Conditions

V_IH

V_IL

Logic “1” input voltage

2.5

—

0.8

—

Logic “0” input voltage

V_IN,_TH+

V_IN,_THꢀ

V_OH

Input positive going threshold

Input negative going threshold

High level output voltage

Low level output voltage

1.9

1

—

0.8

0.2

1.4

0.6

I_O= 20 mA

V

V_OL

V_CCUV+

V_BSUV+

V_CCUVꢀ

V_BSUVꢀ

V_CCUVH

V_BSUVH

V_CCand V_BSsupply underꢀvoltage positive

going threshold

V_CCand V_BSsupply underꢀvoltage negative

going threshold

8.0

6.9

8.9

7.7

1.2

9.8

8.5

—

V_CCand V_BSsupply underꢀvoltage hysteresis

0.35

I_LK

I_QBS

I_QCC

I_IN+

I_INꢀ

Offset supply leakage current

Quiescent V_BSsupply current

Quiescent V_CCsupply current

Logic “1” input bias current

—

1

50

70

1.8

20

2

V_B=V_S= 600 V

V_IN= 0 V or 5 V

ꢁA

mA

ꢁA

45

—

1.1

5

—

V_IN= 5 V

V_IN= 0 V

Logic “0” input bias current

—

I_o+

Output high short circuit pulsed current

Output low short circuit pulsed current

Bootstrap resistance ^††

120

250

—

200

350

200

—

V_O= 0 V or 15 V

PW ≤ 10 ꢁs

mA

ꢂ

I_oꢀ

R_BS

††

Integrated bootstrap diode is suitable for Complimentary PWM schemes only. IRS26072D is suitable for

sinusoidal motor control applications. IRS26072D is NOT recommended for Trapezoidal motor control

applications.

Refer to the Integrated Bootstrap Functionality section of this datasheet for more details.

Dynamic Electrical Characteristics

V_CC= V_B= 15 V, V_S= COM, T_A= 25 ^oC and C_L= 1000 pF unless otherwise specified.

Symbol

Definition

Min. Typ. Max. Units

Test Conditions

V_IN= 0V and 5V

PW input =10ꢁs

t_on

t_off

t_r

Turnꢀon propagation delay

Turnꢀoff propagation delay

Turnꢀon rise time

100

—

200

150

50

300

220

80

ns

t_f

Turnꢀoff fall time

—

MT

PM

t_on, t_offpropagation delay matching time

PW pulse width distortion^†

—

50

—

75

†

PM is defined as PW_INꢀ PW_OUT.

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IRS26072DSPbF

Functional Block Diagram

VB

UV

DETECT

R

HO

R

Q

HV

LEVEL

SHIFTER

PULSE

FILTER

S

HIN

PULSE

GENERATOR

VS

Integrated BS

DIODE

VCC

UV

DETECT

LO

DELAY

LIN

COM

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IRS26072DSPbF

Input/Output Pin Equivalent Circuit Diagrams

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IRS26072DSPbF

Lead Definitions

Symbol

Description

VCC

VB

Low side and logic power supply

High side floating power supply

High side floating supply return

VS

HIN

LIN

HO

Logic input for high side gate driver output HO, input is inꢀphase with output

Logic input for low side gate driver output LO, input is inꢀphase with output

High side gate driver output

LO

Low side gate driver output

COM

Low side supply return

Lead Assignments

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IRS26072DSPbF

Application Information and Additional Details

•

IGBT/MOSFET Gate Drive

Switching and Timing Relationships

Matched Propagation Delays

Input Logic Compatibility

UnderꢀVoltage Lockout Protection

Truth Table: UnderꢀVoltage lockout

Integrated Bootstrap Functionality

Bootstrap Power Supply Design

Tolerant to Negative V_STransients

PCB Layout Tips

Integrated Bootstrap FET limitation

Additional Documentation

IGBT/MOSFET Gate Drive

The IRS26072D HVIC is designed to drive high side and low side MOSFET or IGBT power devices. Figures 1 and

2 show the definition of some of the relevant parameters associated with the gate driver output functionality. The

output current that drives the gate of the external power switches is defined as I_O. The output voltage that drives

the gate of the external power switches is defined as V_HOfor the high side and V_LOfor the low side; this parameter

is sometimes generically called V_OUTand in this case the high side and low side output voltages are not

differentiated.

V_B

(or V_CC)

I_O+

HO

(or LO)

+

I_Oꢀ

V_HO(or V_LO)

ꢀ

V_S

(or COM)

Figure 1: HVIC sourcing current

Figure 2: HVIC sinking current

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IRS26072DSPbF

Switching and Timing Relationships

The relationship between the input and output signals of the IRS26072D HVIC is shown in Figure 3. The

definitions of some of the relevant parameters associated with the gate driver input to output transmission are

given.

LIN

or HIN

50%

PW

IN

t_OFFt_F

90%

t_ONt_R

PW

OUT

90%

10%

LO

or HO

10%

Figure 3: Switching time waveforms

During interval A of Figure 4 the HVIC receives the command to turn on both the high and low side switches at the

same time; correspondingly, the high and low side signals HO and LO turn on simultaneously.

Figure 4: Input/output timing diagram

Matched Propagation Delays

The IRS26072D HVIC is designed for propagation delay matching. With this feature, the input to output

propagation delays t_ON, t_OFFare the same for the low side and the high side channels; the maximum difference

being specified by the delay matching parameter MT as defined in Figure 6.

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IRS26072DSPbF

Figure 6: Delay Matching Waveform Definition

Input Logic Compatibility

The IRS26072D HVIC is designed with inputs compatible with standard CMOS and TTL outputs with 3.3 V and 5

V logic level signals. Figure 7 shows how an input signal is logically interpreted.

Figure 7: HIN & LIN input thresholds

Under-Voltage Lockout Protection

The IRS26072D HVIC provides underꢀvoltage lockout protection on both the V_CClow side and logic fixed power

supply and the VBS high side floating power supply. Figure 8 illustrates this concept by considering the V_CC(or

V_BS) plotted over time: as the waveform crosses the UVLO threshold, the underꢀvoltage protection is entered or

exited.

Upon power up, should the V_CCvoltage fail to reach the V_CCUV+threshold, the gate driver outputs LO and HO will

remain disabled. Additionally, if the V_CCvoltage decreases below the V_CCUVꢀthreshold during normal operation, the

underꢀvoltage lockout circuitry will shutdown the gate driver outputs LO and HO.

Upon power up, should the V_BSvoltage fail to reach the V_BSUVthreshold, the gate driver output HO will remain

disabled. Additionally, if the V_BSvoltage decreases below the V_BSUVthreshold during normal operation, the underꢀ

voltage lockout circuitry will shutdown the high side gate driver output HO.

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IRS26072DSPbF

The UVLO protection ensures that the HVIC drives external power devices only with a gate supply voltage

sufficient to fully enhance them. Without this protection, the gates of the external power switches could be driven

with a low voltage, which would result in power switches conducting current while with a high channel impedance,

which would produce very high conduction losses possibly leading to power device failure.

V_CC

(or V_BS

)

V_{CCUV +}

(or V_{BSUV +}

)

V_CCUV

ꢀ

(or V_{BSUV ꢀ}

)

Time

UVLO Protection

(Gate Driver Outputs Disabled)

Normal

Operation

Figure 8: UVLO protection

Truth Table: Under-Voltage lockout

Table 2 provides the truth table for the IRS26072D HVIC.

The 1^stline shows that for V_CCbelow the UVLO threshold both the gate driver outputs LO and HO are disabled.

fter V returns above , the gate driver outputs return functional.

A

V_CCUV

CC

The 2^ndline shows that for V_BSbelow the UVLO threshold, the gate driver output HO is disabled. After V_BSreturns

above , HO remains low until a new rising transition of HIN is received.

V_BSUV

The last line shows the normal operation of the HVIC.

outputs

LO

VCC

VBS

HO

<

15 V

UVLO V_CC

UVLO V_BS

Normal operation

0

LIN

0

HIN

V_CCUV

<

V_BSUV

15 V

Table 2: UVLO truth table

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IRS26072DSPbF

Integrated Bootstrap Functionality

The IRS26072D HVIC embeds an integrated bootstrap FET that eliminates the need of external bootstrap diodes

and resistors allowing an alternative drive of the bootstrap supply for a wide range of applications.

A bootstrap FET is connected between the high side floating power supply VB and the low side and logic fixed

power supply VCC (see Fig. 9).

Bootstrap FET

VCC

VB

Figure 9: Simplified Bootstrap FET connection

The bootstrap FET is suitable for complimentary PWM switching schemes only. Complimentary PWM refers to

PWM schemes where the HIN & LIN input signals are alternately switched on and off. IRS26072D is suitable for

sinusoidal motor control and the integrated bootstrap feature can be used either in parallel with the external

bootstrap network (diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a

replacement of the external bootstrap network may have some limitations at very high PWM duty cycle,

corresponding to very short LIN pulses, due to the bootstrap FET equivalent resistance R_BS. IRS26072D is NOT

recommended for trapezoidal motor control, even if an external bootstrap network is employed in parallel.

The bootstrap FET is conditioned as follows:

•

bootstrap turnsꢀoff (immediately) or stays off when either:

ꢀ

HO goes/stays high;

V_Bgoes/ stays high (> 1.1*V_CC);

•

bootstrap turnsꢀon when:

ꢀ

LO is high (low side is on) AND V_Bis low (<1.1*V_CC);

LO and HO are low after a transition of LIN from high to low AND V_Bgoes low (<1.1*V_CC) before

a fixed time of 20us;

ꢀ

LO and HO are low after a transition of HIN from high to low AND V_Bgoes low (<1.1*V_CC) before

a reꢀtriggerable time of 20us. In this case the time counter is kept in reset state until VB goes

high (>1.1V_CC).

In Figure 10 the BootFET timing diagram details are represented.

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IRS26072DSPbF

20 us timer

counter

Timer is reset

Timer expired

Timer is reset

HIN

LIN

BootStrap

Fet

VB

+

ꢀ

1.1*Vcc

Figure 10: BootFET timing diagram

Bootstrap Power Supply Design

For information related to the design of the bootstrap power supply while using the integrated bootstrap

functionality of the IRS26072D, please refer to Application Note 1123 (ANꢀ1123) entitled “Bootstrap Network

Analysis: Focusing on the Integrated Bootstrap Functionality.” This application note is available at www.irf.com.

For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode)

please refer to Design Tip 04ꢀ4 (DT04ꢀ4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is

available at www.irf.com.

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IRS26072DSPbF

Tolerant to Negative VS Transients

A common problem in today’s highꢀpower switching converters is the transient response of the switch node’s

voltage as the power devices switch on and off quickly while carrying a large current. A typical 3ꢀphase inverter

circuit is shown in Figure 11; where we define the power switches and diodes of the inverter.

If the highꢀside switch (e.g., the IGBT Q1 in Figures 12 and 13) switches off, while the U phase current is flowing

to an inductive load, a current commutation occurs from highꢀside switch (Q1) to the diode (D2) in parallel with the

lowꢀside switch of the same inverter leg. At the same instance, the voltage node V_S1, swings from the positive DC

bus voltage to the negative DC bus voltage.

Figure 11: Three phase inverter

DC+ BUS

Q1

ON

I_U

V_S1

D2

Q2

OFF

DCꢀ BUS

Figure 12: Q1 conducting

Figure 13: D2 conducting

Also when the V phase current flows from the inductive load back to the inverter (see Figures 14 and 15), and Q4

IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2,

swings from the positive DC bus voltage to the negative DC bus voltage.

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IRS26072DSPbF

Figure 14: D3 conducting

Figure 15: Q4 conducting

However, in a real inverter circuit, the V_Svoltage swing does not stop at the level of the negative DC bus, rather it

swings below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”.

The circuit shown in Figure 16 depicts one leg of the three phase inverter; Figures 17 and 18 show a simplified

illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit

from the die bonding to the PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the highꢀside

switch is on, V_S1is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic

elements of the circuit. When the highꢀside power switch turns off, the load current momentarily flows in the lowꢀ

side freewheeling diode due to the inductive load connected to V_S1(the load is not shown in these figures). This

current flows from the DCꢀ bus (which is connected to the COM pin of the HVIC) to the load and a negative

voltage between V_S1and the DCꢀ Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the V_S

pin).

Figure 16: Parasitic Elements

Figure 17: V_Spositive

Figure 18: V_Snegative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3ꢀ5 V/ns. The negative V_Stransient

voltage can exceed this range during some events such as short circuit and overꢀcurrent shutdown, when di/dt is

greater than in normal operation.

International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding

applications. An indication of the IRS26072D’s robustness can be seen in Figure 19, where there is represented

the IRS26072D Safe Operating Area at V_BS=15V based on repetitive negative V_Sspikes. A negative V_Stransient

voltage falling in the grey area (outside SOA) may lead to IC permanent damage; vice versa unwanted functional

anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA.

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IRS26072DSPbF

At V_BS=15V in case of ꢀV_Stransients greater than ꢀ16.5 V for a period of time greater than 50 ns; the HVIC will

hold by design the highꢀside outputs in the off state for 4.5 ꢃs.

Figure 19: Negative V_Stransient SOA @ VBS=15V

Even though the IRS26072D has been shown able to handle these large negative VS transient conditions, it is

highly recommended that the circuit designer always limit the negative V_Stransients as much as possible by

careful PCB layout and component use.

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IRS26072DSPbF

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to

the floating voltage pins (V_Band V_S) near the respective high voltage portions of the device. Please see the Case

Outline information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure

20). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive

loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the

IGBT collectorꢀtoꢀgate parasitic capacitance. The parasitic autoꢀinductance of the gate loop contributes to

developing a voltage across the gateꢀemitter, thus increasing the possibility of a self turnꢀon effect.

I_GC

V_B

(or V_CC)

C_GC

G

R

HO

(or LO )

Gate Drive

V_GE

Loop

V_S

(or COM)

Figure 20: Antenna Loops

Supply Capacitor: It is recommended to place a bypass capacitor between the VCC and COM pins. This

connection is shown in Figure 21. A ceramic 1 ꢃF ceramic capacitor is suitable for most applications. This

component should be placed as close as possible to the pins in order to reduce parasitic elements.

Up to 600V

Vcc

HIN1,2,3

LIN1,2,3

V

B1,2,3

HIN1,2,3

LIN1,2,3

HO1,2,3

V

S1,2,3

TO

LOAD

LO1,2,3

COM

GND

Figure 21: Supply capacitor

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IRS26072DSPbF

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at

the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such

conditions, it is recommended to 1) minimize the highꢀside source to lowꢀside collector distance, and 2) minimize

the lowꢀside emitter to negative bus rail stray inductance. However, where negative V_Sspikes remain excessive,

further steps may be taken to reduce the spike. This includes placing a resistor (5 ꢂ or less) between the V_Spin

and the switch node (see Figure 22), and in some cases using a clamping diode between COM and V_S(see

Figure 23). See DT04ꢀ4 at www.irf.com for more detailed information.

DC+ BUS

V_B

C_BS

HO

V_S

LO

HO

V_S

R_VS

To

Load

To

Load

D_VS

LO

COM

DCꢀ BUS

Figure 22: V_Sresistor

Figure 23: V_Sclamping diode

Integrated Bootstrap FET limitation

The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied

to the HVIC:

•

VCC pin voltage = 0V AND

VS or VB pin voltage > 0

In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a current

conduction path is created between VCC & VB pins, as illustrated in Fig.24 below, resulting in power loss and

possible damage to the HVIC.

Figure 24: Current conduction path between VCC and VB pin

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IRS26072DSPbF

Relevant Application Situations:

The above mentioned bias condition may be encountered under the following situations:

•

In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF. In

this condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS nodes

resulting unwanted current flow to VCC.

•

Potential situations in other applications where VS/VB node voltage potential increases before the VCC

voltage is available (for example due to sequencing delays in SMPS supplying VCC bias)

Application Workaround:

Insertion of a standard pꢀn junction diode between VCC pin of IC and positive terminal of VCC capacitors (as

illustrated in Fig.25) prevents current conduction “outꢀof” VCC pin of gate driver IC. It is important not to connect the

VCC capacitor directly to pin of IC. Diode selection is based on 25V rating or above & current capability aligned to

ICC consumption of IC ꢀ 100mA should cover most application situations. As an example, Part number # LL4154

from Diodes Inc (25V/150mA standard diode) can be used.

VCC

VB

VCC

Capacitor

VSS

(or COM)

Figure 25: Diode insertion between VCC pin and VCC capacitor

Note that the forward voltage drop on the diode (V_F) must be taken into account when biasing the VCC pin of

the IC to meet UVLO requirements. VCC pin Bias = VCC Supply Voltage – V_Fof Diode.

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search

function and the document number to quickly locate them. Below is a short list of some of these documents.

DT97ꢀ3: Managing Transients in Control IC Driven Power Stages

ANꢀ1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04ꢀ4: Using Monolithic High Voltage Gate Drivers

ANꢀ978: HV Floating MOSꢀGate Driver ICs

Parameter Temperature Trends

Figures 26ꢀ43 provide information on the experimental performance of the IRS26072D HVIC. The line plotted

in each figure is generated from actual experimental data. A small number of individual samples were tested

at three temperatures (ꢀ40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The line consist

of three data points (one data point at each of the tested temperatures) that have been connected together to

illustrate the understood temperature trend. The individual data points on the curve were determined by

calculating the averaged experimental value of the parameter (for a given temperature).

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IRS26072DSPbF

100

80

60

40

20

0

1.0

0.8

0.6

0.4

0.2

0.0

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 26: I_QCCvs. temperature

Figure 27: I_QBSvs. temperature

10

8

10

8

6

4

2

0

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 28: I_LKvs. temperature

Figure 29: I_IN+vs. temperature

1000

800

600

400

200

0

1000

800

600

400

200

0

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 30: t_ONvs. temperature

Figure 31: t_OFFvs. temperature

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23

IRS26072DSPbF

100

80

60

40

20

0

200

160

120

80

40

0

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 32: t_RISEvs. temperature

Figure 33: t_FALLvs. temperature

1000

800

600

400

200

0

100

80

60

40

20

0

ꢀ50

ꢀ25

0

25

50

75

ꢀ50

ꢀ25

0

25

50

75

Temperature (^oC)

Figure 34: MT vs. temperature

Figure 35: R_BSvs. temperature

1000

800

600

400

200

0

1000

800

600

400

200

0

ꢀ50

ꢀ25

0

25

50

75

ꢀ50

ꢀ25

0

25

50

75

Temperature (^oC)

Figure 36: I_O+vs. temperature

Figure 37: I_O-vs. temperature

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24

IRS26072DSPbF

10

8

10

8

6

4

2

0

ꢀ50

ꢀ25

0

25

50

75

100

125

ꢀ50

ꢀ25

0

25

50

75

100

125

Temperature (^oC)

Figure 38: V_CCUV-vs. temperature

Figure 39: V_BSUV-vs. temperature

10

8

10

8

6

4

2

0

ꢀ50

ꢀ25

0

25

50

75

100

ꢀ50

ꢀ25

0

25

50

75

100

Temperature (^oC)

Figure 40: V_CCUV+vs. temperature

Figure 41: V_BSUV+vs. temperature

2.0

1.6

1.2

0.8

0.4

0.0

2.0

1.6

1.2

0.8

0.4

0.0

ꢀ50

ꢀ25

0

25

50

75

100

ꢀ50

ꢀ25

0

25

50

75

100

Temperature (^oC)

Figure 42: V_CCUVHvs. temperature

Figure 43: V_BSUVHvs. temperature

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25

IRS26072DSPbF

Package Details

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26

IRS26072DSPbF

Tape and Reel Details

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 8SOICN

Metric

Imperial

Min

0.311

0.153

0.46

Code

A

B

C

D

E

F

G

H

Min

7.90

3.90

11.70

5.45

6.30

5.10

1.50

Max

8.10

4.10

12.30

5.55

6.50

5.30

n/a

Max

0.318

0.161

0.484

0.218

0.255

0.208

n/a

0.214

0.248

0.200

0.059

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 8SOICN

Metric

Imperial

Max

Code

A

B

C

D

Min

329.60

20.95

12.80

1.95

Max

330.25

21.45

13.20

2.45

Min

12.976

0.824

0.503

0.767

3.858

n/a

13.001

0.844

0.519

0.096

4.015

0.724

0.673

0.566

E

F

G

H

98.00

n/a

14.50

12.40

102.00

18.40

17.10

14.40

0.570

0.488

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27

IRS26072DSPbF

Part Marking Information

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28

IRS26072DSPbF

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Form

Quantity

XXX

Tube/Bulk

IRS26072D SPBF

SOIC 8

IRS26072D

Tape and Reel

XXX

IRS26072D STRPBF

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the

consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third

parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International

Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information

previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

www.irf.com

29

IRS26072DSPbF

Revision History

Revision Date

Change comments

Prelim.

01

02

Presumably a copy of IRS2607D datasheet

Preliminary with input filter removed

Formatting of IRS2334 datasheet, sections copied and added from IRS26042D

datasheet, parameters limits checked against test limits

Date and datasheet PD number added

Updated to reflect that integrated bootstrap diode works only with complimentary PWM.

And also added “NOT recommended for trapezoidal motor control”

Released by Ramanan

Parameter temperature trend graphs updated, first page footer updated

Added Bootstrap fet limitation

30 Apr 09

02 Jul 09

03

04

13ꢀJulꢀ09

18ꢀAugꢀ09

05

06

07

18ꢀAugꢀ09

21ꢀAugꢀ09

30ꢀMayꢀ11

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30


型号：	IRS26072DSPBF_11
厂家：	Infineon
描述：	HIGH AND LOW SIDE DRIVER 高端和低端驱动器驱动器
文件：	总30页 (文件大小：844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRS26072DSPBF_11 [INFINEON]

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