IRU1010 [INFINEON]
1A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR; 1A低压差正可调稳压器
| 型号： | IRU1010 |
| 厂家： | 
Infineon |
| 描述： | 1A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR |
| 文件： | 总6页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94119
IRU1010
1A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
DESCRIPTION
FEATURES
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
The IRU1010 is a low dropout, three-terminal adjustable
regulator with minimum of 1A output current capability.
This product is specifically designed to provide well regu-
lated supply for low voltage IC applications such as high
speed bus termination and low current 3.3V logic sup-
ply. The IRU1010 is also well suited for other applica-
tions such as VGA and sound cards. The IRU1010 is
guaranteed to have <1.3V dropout at full load current
making it ideal to provide well regulated outputs of 2.5V
to 3.6V with 4.75V to 7V input supply.
1% Voltage Reference Initial Accuracy
Built-In Thermal Shutdown
Available in SOT-223, D-Pak, Ultra Thin-Pak and
8-Pin SOIC Surface-Mount Packages
APPLICATIONS
VGA & Sound Card Applications
Low Voltage High Speed Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
D1
5V
C1
10uF
Vin
3
2
1
IRU1010
Vout
2.85V / 1A
R1
121
C2
Adj
22uF
R2
1010app1-1.4
154
Figure 1 - Typical application of IRU1010 in a 5V to 2.85V SCSI termination regulator
PACKAGE ORDER INFORMATION
Tj (°C)
2-PIN PLASTIC
TO-252 (D-Pak)
IRU1010CD
3-PIN PLASTIC
SOT-223 (Y)
IRU1010CY
2-PIN PLASTIC
Ultra Thin-Pak (P)
IRU1010CP
8-PIN PLASTIC
SOIC (S)
0 To 150
IRU1010CS
Rev. 1.4
06/29/01
1
IRU1010
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range ..................... 0°C To 150°C
PACKAGE INFORMATION
2-PIN PLASTIC TO-252 (D-Pak)
3-PIN PLASTIC SO-223 (Y)
2-PIN ULTRA THIN-PAK (P)
8-PIN PLASTIC SOIC (S)
FRONT VIEW
FRONT VIEW
TOP VIEW
TOP VIEW
3
3
Vin
Vin
1
2
3
4
8
7
6
5
Vin
NC
NC
Adj
Vout
Vout
Vout
Vout
3
Vin
Tab is
Vout
Tab is
Vout
Tab is
2
Vout
Vout
1
Adj
1
1
Adj
Adj
θJA=70ꢀC/W for 0.5" Sq pad
θJA=90ꢀC/W for 0.4" Sq pad
θJA=70ꢀC/W for 0.5" Sq pad
θJA=55ꢀC/W for 1" Sq pad
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Cin=1µF, Cout=10µF, and Tj=0 to 150ꢀC.
Typical values refer to Tj=25ꢀC.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Reference Voltage
Vref
Io=10mA, Tj=25ꢀC, (Vin-Vo)=1.5V 1.238 1.250
1.262
V
Io=10mA, (Vin-Vo)=1.5V
Io=10mA, 1.3V<(Vin-Vo)<7V
Vin=3.3V, Vadj=0, 10mA<Io<1A
Note 2 , Io=1A
Vin=3.3V, dVo=100mV
Vin=3.3V, Vadj=0V
1.225 1.250 1.275
Line Regulation
0.2
0.4
1.3
%
%
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
∆Vo
1.1
5
V
1.1
A
Minimum Load Current
(Note 3)
Thermal Regulation
Ripple Rejection
10
mA
30ms Pulse, Vin-Vo=3V, Io=1A
f=120Hz, Co=25µF Tantalum,
Io=0.5A, Vin-Vo=3V
0.01
70
0.02
%/W
dB
60
Adjust Pin Current
Iadj Io=10mA, Vin-Vo=1.5V, Tj=25ꢀC,
Io=10mA, Vin-Vo=1.5V
55
0.2
120
5
µA
µA
%
%
%Vo
Adjust Pin Current Change
Temperature Stability
Long Term Stability
Io=10mA, Vin-Vo=1.5V, Tj=25ꢀC
Vin=3.3V, Vadj=0V, Io=10mA
Tj=125ꢀC, 1000Hrs
0.5
0.3
1
RMS Output Noise
Tj=25ꢀC, 10Hz<f<10KHz
0.003
Note 1: Low duty cycle pulse testing with Kelvin con- Note 3: Minimum load current is defined as the mini-
nections is required in order to maintain accurate data. mum current required at the output in order for the out-
put voltage to maintain regulation. Typically, the resistor
Note 2: Dropout voltage is defined as the minimum dif- dividers are selected such that it automatically main-
ferential voltage between Vin and Vout required to main- tains this current.
tain regulation at Vout. It is measured when the output
voltage drops 1% below its nominal value.
Rev. 1.4
2
06/29/01
IRU1010
PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1
A resistor divider from this pin to the Vout pin and ground sets the output voltage.
Adj
2
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
Vout
to ground to insure stability.
3
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum dropout
voltage during the load transient response. This pin must always be 1.3V higher than Vout
in order for the device to regulate properly.
Vin
BLOCK DIAGRAM
Vin 3
2 Vout
+
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
1 Adj
1010blk1-1.0
Figure 2 - Simplified block diagram of the IRU1010
APPLICATION INFORMATION
Introduction
The IRU1010 adjustable Low Dropout (LDO) regulator is memory termination need to switch the load current from
a three-terminal device which can easily be programmed zero to full load in tens of nanoseconds at their pins,
with the addition of two external resistors to any volt- which translates to an approximately 300 to 500ns cur-
ages within the range of 1.25 to 5.5V. This regulator, rent step at the regulator. In addition, the output voltage
unlike the first generation of the three-terminal regula- tolerances are sometimes tight and they include the tran-
tors such as LM117 that required 3V differential between sient response as part of the specification.
the input and the regulated output, only needs 1.3V dif-
ferential to maintain output regulation. This is a key re- The IRU1010 is specifically designed to meet the fast
quirement for today’s low voltage IC applications that current transient needs as well as providing an accurate
typically need 3.3V supply and are often generated from initial voltage, reducing the overall system cost with the
the 5V supply. Other applications such as high speed
need for fewer output capacitors.
Rev. 1.4
06/29/01
3
IRU1010
Output Voltage Setting
regulator and not to the load. In fact, if R1 is connected
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+R2/
R1), or the effective resistance will be, Rp(eff)=Rp*(1+R2/
R1). It is important to note that for high current applica-
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
The IRU1010 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
R2
VOUT = VREF × o1 +
p + IADJ × R2
R1
Where:
VREF = 1.25V Typically
IADJ = 50µA Typically
PARASITIC LINE
RESISTANCE
R1 and R2 as shown in figure 3:
Rp
Vin
Vout
Vin
Vin
Vout
Vin
Vout
IRU1010
IRU1010
R
L
Adj
R1
R2
Adj
R1
R2
Vref
IAdj = 50uA
1010app2-1.0
1010app3-1.0
Figure 3 - Typical application of the IRU1010
for programming the output voltage
Figure 4 - Schematic showing connection
for best load regulation
Stability
The IRU1010 keeps a constant 1.25V between the out- The IRU1010 requires the use of an output capacitor as
put pin and the adjust pin. By placing a resistor R1 across part of the frequency compensation in order to make the
these two pins a constant current flows through R1, add- regulator stable. Typical designs for microprocessor ap-
ing to the I
current and into the R2 resistor producing plications use standard electrolytic capacitors with a
adj
a voltage equal to the (1.25/R1)*R2 + Iadj*R2 which will typical ESR in the range of 50 to 100mΩ and an output
be added to the 1.25V to set the output voltage. This is capacitance of 500 to 1000µF. Fortunately as the ca-
summarized in the above equation. Since the minimum pacitance increases, the ESR decreases resulting in a
load current requirement of the IRU1010 is 10mA, R1 is fixed RC time constant. The IRU1010 takes advantage
typically selected to be 121Ω resistor so that it auto- of this phenomena in making the overall regulator loop
matically satisfies the minimum current requirement. stable. For most applications a minimum of 100µF alu-
Notice that since Iadj is typically in the range of 50µA it minum electrolytic capacitor such as Sanyo MVGX se-
only adds a small error to the output voltage and should ries, Panasonic FA series as well as the Nichicon PL
only be considered when a very precise output voltage series insures both stability and good transient response.
setting is required. For example, in a typical 3.3V appli-
cation where R1=121Ω and R2=200Ω the error due to Thermal Design
Iadj is only 0.3% of the nominal set point.
The IRU1010 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Load Regulation
Since the IRU1010 is only a three-terminal device, it is Although this device can operate with junction tempera-
not possible to provide true remote sensing of the output tures in the range of 150ꢀC, it is recommended that the
voltage at the load. Figure 4 shows that the best load selected heat sink be chosen such that during maxi-
regulation is achieved when the bottom side of R2 is mum continuous load operation the junction tempera-
connected to the load and the top side of R1 resistor is ture is kept below this number. The example below for
connected directly to the case or the Vout pin of the a SCSI terminator application shows the steps in sellect-
Rev. 1.4
4
06/29/01
IRU1010
ing the proper regulator in a surface-mount package. To set the output DC voltage, we need to select R1 and
(See IRU1015 for non-surface-mount packages)
R2:
Assuming the following specifications:
4) Assuming R1 = 121Ω, 1%
VIN = 5V
2.85
VOUT
VF = 0.5V
Vo = 2.85V
IOUT(MAX) = 0.8A
TA = 35ꢀC
R2 =o
-1p× R1 =o
- 1p× 121 = 154.8Ω
1.25
VREF
Select R2 = 154Ω, 1%
D1
Where: VF is the forward voltage drop of the D1diode as
shown in Figure 5.
Vin
Vout
5V
2.85V
C1
C2
IRU1010
10uF
22uF
The steps for selecting the right package with proper
board area for heatsinking to keep the junction tempera-
ture below 135ꢀC is given as:
R1
Adj
121
1%
R2
1) Calculate the maximum power dissipation using:
PD = IOUT × (VIN - VF - VOUT)
154
1%
1010app4-1.3
PD = 0.8 × (5 - 0.5 - 2.85) = 1.32W
Figure 5 - Final Schematic for half of the
GTL+ termination regulator
2) Calculate the maximum θJA allowed for our example:
TJ - TA
PD
135 - 35
1.32
θJA(MAX) =
=
= 75.6ꢀC/W
Layout Consideration
The output capacitors must be located as close to the
Vout terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the Vout pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
3) Select a package from the datasheet with lower θJA
than the one calculated in the previous step.
Selecting TO-252 (D-Pak) with at least 0.5" square
of 0.062" FR4 board using 1 oz. copper has 70°C/W
which is lower than the calculated number.
Rev. 1.4
06/29/01
5
Notes
IRU1010
IR WORLD HEADQUARTERS : 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 02/01
Rev. 1.4
06/29/01
6
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