IRU1015CM [INFINEON]
1.5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR; 1.5A低压差正可调稳压器型号: | IRU1015CM |
厂家: | Infineon |
描述: | 1.5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR |
文件: | 总8页 (文件大小:107K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Data Sheet No. PD94122
IRU1015
1.5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
DESCRIPTION
FEATURES
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
The IRU1015 is a low dropout three-terminal adjustable
regulator with minimum of 1.5A output current capabil-
ity. This product is specifically designed to provide well
regulated supply for low voltage IC applications such as
486DX4 processor, P55C I/O supply as well as high
speed bus termination and low current 3.3V logic sup-
ply. The IRU1015 is also well suited for other applica-
tions such as VGA and sound card. The IRU1015 is
guaranteed to have <1.3V dropout at full load current
making it ideal to provide well regulated outputs of 2.5V
to 3.3V with 4.75V to 7V input supply.
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
APPLICATIONS
486DX4 Supply Voltage
P55 I/O Supply Voltage
VGA & Sound Card Applications
Low Voltage High Speed Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
C1
1500uF
Vin
3
Vout
2
3.3V / 1.5A
IRU1015
R1
121
C2
1500uF
R2
Adj
1
200
1015app1-1.1
Figure 1 - Typical application of IRU1015 in a 5V to 3.3V regulator
Note: P55C is trademark of Intel Corp.
PACKAGE ORDER INFORMATION
T (°C)
j
3-PIN PLASTIC
3-PIN PLASTIC
2-PIN PLASTIC
TO-252 (D-Pak)
IRU1015CD
TO-220 (T)
TO-263 (M)
0 To 150
IRU1015CT
IRU1015CM
Rev. 1.1
06/29/01
1
IRU1015
ABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range ..................... 0°C To 150°C
PACKAGE INFORMATION
3-PIN PLASTIC TO-220 (T)
3-PIN PLASTIC TO-263 (M)
2-PIN PLASTIC TO-252 (D-Pak)
FRONT VIEW
FRONT VIEW
FRONT VIEW
3
3
3
Vin
Vin
Vin
Tab is
Vout
Tab is
Vout
Tab is
2
1
Vout
Adj
Vout
Vout
1
1
Adj
Adj
θJT=2.7°C/W θJA=60°C/W
θJA=35°C/W for 1" Square pad
θJA=70°C/W for 0.5" Square pad
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Cin=1µF, Cout=10µF, and Tj=0 to 150ꢀC.
Typical values refer to Tj=25ꢀC.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX
UNITS
Reference Voltage
Vref
Io=10mA, Tj=25ꢀC, (Vin-Vo)=1.5V 1.238 1.250
1.262
V
Io=10mA, (Vin-Vo)=1.5V
Io=10mA, 1.3V<(Vin-Vo)<7V
Vin=3.3V, Vadj=0, 10mA<Io<1.5A
Note 2, Io=1.5A
Vin=3.3V, dVo=100mV
Vin=3.3V, Vadj=0V
1.225 1.250 1.275
Line Regulation
0.2
0.4
1.3
%
%
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Current Limit
∆Vo
1.1
5
V
1.6
60
A
Minimum Load Current
(Note 3)
Thermal Regulation
Ripple Rejection
10
mA
30ms Pulse, Vin-Vo=3V, Io=1.5A
f=120Hz, Co=25µF Tantalum,
Io=0.75A, Vin-Vo=3V
0.01
70
0.02
%/W
dB
Adjust Pin Current
Iadj Io=10mA, Vin-Vo=1.5V, Tj=25ꢀC,
Io=10mA, Vin-Vo=1.5V
55
0.2
120
5
µA
µA
%
%
%Vo
Adjust Pin Current Change
Temperature Stability
Long Term Stability
Io=10mA, Vin-Vo=1.5V, Tj=25ꢀC
Vin=3.3V, Vadj=0V, Io=10mA
Tj=125ꢀC, 1000Hrs
0.5
0.3
1
RMS Output Noise
Tj=25ꢀC, 10Hz<f<10KHz
0.003
Note 1: Low duty cycle pulse testing with Kelvin con- Note 3: Minimum load current is defined as the mini-
nections is required in order to maintain accurate data. mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
Note 2: Dropout voltage is defined as the minimum dif- dividers are selected such that it automatically main-
ferential voltage between Vin and Vout required to main-
tain regulation at Vout. It is measured when the output
voltage drops 1% below its nominal value.
tains this current.
Rev. 1.1
06/29/01
2
IRU1015
PIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
Adj
A resistor divider from this pin to the Vout pin and ground sets the output voltage.
1
Vout
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
2
to ground to insure stability.
Vin
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than Vout
in order for the device to regulate properly.
3
BLOCK DIAGRAM
Vin 3
2 Vout
+
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
1 Adj
1015blk1-1.0
Figure 2 - Simplified block diagram of the IRU1015
APPLICATION INFORMATION
Introduction
The IRU1015 adjustable Low Dropout (LDO) regulator is sors is the need to switch the load current from zero to
a three-terminal device which can easily be programmed full load in tens of nanoseconds at their pins, which
with the addition of two external resistors to any volt- translates to an approximately 300 to 500ns current step
ages within the range of 1.25 to 5.5 V.This regulator un- at the regulator. In addition, the output voltage toler-
like the first generation of the three-terminal regulators ances are sometimes tight and they include the tran-
such as LM117 that required 3V differential between the sient response as part of the specification.
input and the regulated output, only needs 1.3V differen-
tial to maintain output regulation. This is a key require- The IRU1015 is specifically designed to meet the fast
ment for today’s microprocessors that need typically current transient needs as well as provide an accurate
3.3V supply and are often generated from the 5V sup- initial voltage, reducing the overall system cost with the
ply. Another major requirement of these microproces- need for fewer output capacitors.
Rev. 1.1
3
06/29/01
IRU1015
Output Voltage Setting
The IRU1015 can be programmed to any voltages in the regulator and not to the load. In fact, if R1 is connected
range of 1.25V to 5.5V with the addition of R1 and R2 to the load side, the effective resistance between the
external resistors according to the following formula:
regulator and the load is gained up by the factor of (1+R2/
R1), or the effective resistance will be, Rp(eff)=Rp*(1+R2/
R1). It is important to note that for high current applica-
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
R2
VOUT = VREF × o1 +
p + IADJ × R2
R1
Where:
VREF = 1.25V Typically
IADJ = 50µA Typically
R1 and R2 as shown in figure 3:
PARASITIC LINE
RESISTANCE
Rp
Vin
Vout
Vin
Vin
Vout
Vin
Vout
IRU1015
IRU1015
R
L
Adj
R1
R2
Adj
R1
R2
Vref
IAdj = 50uA
1015app2-1.0
1015app3-1.0
Figure 3 - Typical application of the IRU1015
for programming the output voltage.
Figure 4 - Schematic showing connection
for best load regulation
The IRU1015 keeps a constant 1.25V between the out- Stability
put pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, add-
ing to the Iadj current and into the R2 resistor producing
a voltage equal to the (1.25/R1)*R2 + Iadj*R2 which will
be added to the 1.25V to set the output voltage. This is
summarized in the above equation. Since the minimum
load current requirement of the IRU1015 is 10mA, R1 is
typically selected to be 121Ω resistor so that it auto-
matically satisfies the minimum current requirement.
Notice that since Iadj is typically in the range of 50µA it
only adds a small error to the output voltage and should
only be considered when a very precise output voltage
setting is required. For example, in a typical 3.3V appli-
cation where R1=121Ω and R2=200Ω the error due to
Iadj is only 0.3% of the nominal set point.
The IRU1015 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor ap-
plications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100mΩ and an output
capacitance of 500 to 1000µF. Fortunately as the ca-
pacitance increases, the ESR decreases resulting in a
fixed RC time constant. The IRU1015 takes advantage
of this phenomena in making the overall regulator loop
stable. For most applications a minimum of 100µF alu-
minum electrolytic capacitor such as Sanyo MVGX se-
ries, Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
Thermal Design
The IRU1015 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 150ꢀC, it is recommended that the
selected heat sink be chosen such that during maxi-
mum continuous load operation the junction tempera-
ture is kept below this number. The example below
Load Regulation
Since the IRU1015 is only a three-terminal device, it is
not possible to provide true remote sensing of the output
voltage at the load. Figure 4 shows that the best load
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the Vout pin of the
Rev. 1.1
06/29/01
4
IRU1015
shows the steps in selecting the proper regulator heat
sink for an AMD 486DX4-120 MHz processor.
Air Flow (LFM)
100
0
Thermalloy 6041PB
No HS Required
AAVID
574602
No HS Required
Assuming the following specifications:
Note: For further information regarding the above com-
panies and their latest product offerings and application
support contact your local representative or the num-
bers listed below:
VIN = 5V
VOUT = 3.45V
IOUT(MAX) = 1.2A
TA = 35ꢀC
AAVID...............PH# (603) 528 3400
Thermalloy.........PH# (214) 243-4321
The steps for selecting a proper heat sink to keep the
junction temperature below 135°C is given as:
Designing for Microprocessor Applications
As it was mentioned before the IRU1015 is designed
specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the 5V
supply. These processors demand a fast regulator that
supports their large load current changes. The worst case
current step seen by the regulator is anywhere in the
range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from “Stop
Clock” mode to the “Full Active” mode. The load current
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however, the de-coupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
frequency low ESR and low ESL output capacitor is
imperative in the design of these regulator circuits.
1) Calculate the maximum power dissipation using:
PD = IOUT × (VIN - VOUT)
PD = 1.2 × (5 - 3.45) = 1.86W
2) Select a package from the regulator data sheet and
record its junction to case (or Tab) thermal resistance.
Selecting TO-220 package gives us:
θJC = 2.7ꢀC/W
3) Assuming that the heat sink is black anodized, cal-
culate the maximum Heat sink temperature allowed:
Assume, θcs=0.05°C/W (heat-sink-to-case thermal
resistance for black anodized)
TS = TJ - PD × (θJC + θCS)
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the (∆VESR=ESR*∆I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor (∆VESL
=L*∆I/∆t). The output capacitance effect is a droop in
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current,
(∆VC = ∆t * ∆I / C ) where ∆t is the response time of the
regulator.
TS = 135 - 1.86 × (2.7 + 0.05) = 129ꢀC
4) With the maximum heat sink temperature calculated
in the previous step, the heat-sink-to-air thermal re-
sistance (θSA) is calculated by first calculating the
temperature rise above the ambient as follows:
∆T = TS - TA = 129 - 35 = 94ꢀC
∆T = Temperature Rise Above Ambient
∆T
94
θSA =
=
= 50ꢀC/W
PD 1.86
5) Next, a heat sink with lower θsa than the one calcu-
lated in step 4 must be selected. One way to do this
is to simply look at the graphs of the "Heat Sink Temp
Rise Above the Ambient" vs. the "Power Dissipation"
and select a heat sink that results in lower tempera-
ture rise than the one calculated in the previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Rev. 1.1
06/29/01
5
IRU1015
2) With the output capacitance being 1500µF:
VESR
VESL
∆t × ∆I
2 × 1.2
1500
∆Vc =
=
= 1.6mV
VC
C
T
Where:
∆t = 2µs is the regulator response time
To set the output voltage, we need to select R1 and R2:
3) Assuming R1 = 121Ω, 1%
LOAD
1015plt1-1.0
CURRENT
LOAD CURRENT RISE TIME
Figure 5 - Typical regulator response to the
fast load current step
VOUT
3.45
1.25
o
- 1p× 121 =o
- 1p× 121 = 213Ω
R2 =
VREF
An example of a regulator design to meet the AMD speci-
fication for 486DX4-120MHz is given below.
Select R2 = 215Ω, 1%
Selecting both R1 and R2 resistors to be 1% toler-
ance results in the least amount of error introduced
by the resistor dividers leaving a ≈ ±2.5% error bud-
get for the IRU1015 reference which is well within the
initial accuracy of the device.
Assume the specification for the processor as shown in
Table 1:
Type of
Processor
AMD 486DX4
Vout
Nominal
3.45 V
Imax
Max Allowed
Output Tolerance
±150 mV
1.2 A
Finally, the input capacitor is selected as follows:
Table 1 - GTL+ specification for Pentium Pro
4) Assuming that the input voltage can drop 150mV be-
fore the main power supply responds, and that the
main power supply response time is ≈ 50ms, then
the minimum input capacitance for a 1.2A load step
is given by:
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR:
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is ≈ ±86mV (±2.5% of 3.45V
nominal), then the total step allowed for the ESR and
the ESL, is -64mV.
1.2 × 50
CIN =
= 400µF
0.15
Assuming that the ESL drop is -10mV, the remaining
ESR step will be -54mV. Therefore the output ca-
pacitor ESR must be:
The ESR should be less than:
(VIN - VOUT - ∆V - VDROP)
ESR =
∆I
54
ESR ≤
= 45mΩ
Where:
1.2
VDROP L Input voltage drop allowed in step 4
∆V L Maximum regulator dropout voltage
∆I L Load current step
The Sanyo MVGX series is a good choice to achieve
both price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typi-
cal. Selecting a single capacitor achieves our design
goal.
(5 - 3.45 - 1.2 - 0.15)
ESR =
= 0.167Ω
1.2
The next step is to calculate the drop due to the ca-
pacitance discharge and make sure that this drop in
voltage is less than the selected ESL drop in the
previous step.
Select a single 1500µF the same type as the output
capacitors exceeds our requirements.Figure 6 shows
the completed schematic for our example.
Rev. 1.1
06/29/01
6
IRU1015
Layout Consideration
Vin
Vout
The output capacitors must be located as close to the
Vout terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the Vout pin to the output capacitors to
prevent any high frequency oscillation that may result
from excessive trace inductance.
5V
3.45V
C1
C2
IRU1015
1500uF
1500uF
R1
Adj
121
1%
R2
215
1%
1015app4-1.1
Figure 6 - Final schematic for the regulator design
Rev. 1.1
06/29/01
7
Notes
IRU1015
IR WORLD HEADQUARTERS : 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 02/01
Rev. 1.1
06/29/01
8
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