概述
数据手册
替代型号IRU1050CM 概述
5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR 5A低压差正可调稳压器 稳压芯片
IRU1050CM 数据手册
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PDF下载Data Sheet No. PD94126
IRU1050
5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURES
DESCRIPTION
Guaranteed < 1.3V Dropout at Full Load Current
Fast Transient Response
The IRU1050 is a low dropout three-terminal adjustable
regulator with minimum of 5A output current capability.
This product is specifically designed to provide well regu-
lated supply for low voltage IC applications such as
Pentiumä P54Cä ,P55Cä as well as GTL+ termination
forPentiumProä and Klamathä processor applications.
The IRU1050 is also well suited for other processors
such as Cyrixä , AMD and Power PCä applications.
The IRU1050 is guaranteed to have <1.3V dropout at full
load current making it ideal to provide well regulated
outputs of 2.5V to 3.3V with 4.75V to 7V input supply.
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-In Thermal Shutdown
APPLICATIONS
Low Voltage Processor Applications such as:
P54Cä , P55Cä , Cyrix M2ä ,
POWER PCä , AMD
GTL+ Termination
PENTIUM PROä , KLAMATHä
Low Voltage Memory Termination Applications
Standard 3.3V Chip Set and Logic Applications
TYPICAL APPLICATION
5V
C1
1500uF
V
IN
3
2
1
V
OUT
3.38V / 5A
R1
IRU1050
121
C2
2x 1500uF
R2
205
Adj
Figure 1 - Typical Application of IRU1050 in a 5V to 3.38V regulator designed
to meet the Intel P54C ä processors.
Notes:Pentium P54C, P55C, Klamath, Pentium Pro,VRE are trademarks of Intel Corp. Cyrix M2 is trademark of Cyrix Corp.
Power PC is trademark of IBM Corp.
PACKAGE ORDER INFORMATION
TJ (°C)
2-PIN PLASTIC
TO-252 (D-Pak)
IRU1050CD
3-PIN PLASTIC
TO-263 (M)
IRU1050CM
2-PIN PLASTIC
Ultra Thin-PakTM (P)
IRU1050CP
3-PIN PLASTIC
TO-220 (T)
0 To 150
IRU1050CT
Rev. 1.8
08/20/02
www.irf.com
1
IRU1050
ABSOLUTE MAXIMUM RATINGS
Input Voltage (VIN) .................................................... 7V
Power Dissipation ..................................................... Internally Limited
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 150°C
PACKAGE INFORMATION
2-Pin Plastic TO-252 (D-Pak)
3-Pin Plastic TO-263 (M)
2-Pin Plastic ULTRA THIN-PAKTM (P)
3-Pin Plastic TO-220 (T)
FRONT VIEW
FRONT VIEW
FRONT VIEW
FRONTVIEW
3
2
1
3
3
VIN
VIN
VIN
Tab is
3
2
1
V
IN
VOUT
Tab is
VOUT
Tab is
VOUT
Tab is
VOUT
VOUT
Adj
VOUT
Adj
1
1
Adj
Adj
qJA=70°C/W for 0.5" Sq pad
qJA=35°C/W for 1" Square pad
qJA=70°C/W for 1" Square pad
qJT=2.7°C/W qJA=60°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over CIN=1µF, COUT=10µF, and TJ=0 to 1508C.
Typical values refer to TJ=258C.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX UNITS
Reference Voltage
VREF Io=10mA, TJ=258C, VIN-Vo=1.5V
Io=10mA, VIN-Vo=1.5
1.238 1.25
1.225 1.25
1.262
1.275
0.2
0.4
1.2
V
Line Regulation
Load Regulation (Note 1)
Dropout Voltage (Note 2)
Io=10mA, 1.3V<(VIN-Vo)<7V
VIN=3.3V, VADJ=0V, 10mA<Io<5A
∆Vo Note 2, Io=4A
%
%
V
Io=5A
1.1
1.3
Current Limit
VIN=3.3V, ∆Vo=100mV
VIN=3.3V, VADJ=0V
5.1
A
mA
5
10
Minimum Load Current (Note 3)
Thermal Regulation
Ripple Rejection
30ms Pulse, VIN-Vo=3V, Io=5A
f=120Hz, Co=25µF Tantalum,
Io=2.5A, VIN-Vo=3V
0.01
0.02
%/W
60
70
dB
Adjust Pin Current
IADJ
Io=10mA, VIN-Vo=1.5V, TJ=258C,
Io=10mA, VIN-Vo=1.5V
55
0.2
120
5
µA
µA
%
Io=10mA, VIN-Vo=1.5V, TJ=258C
VIN=3.3V, VADJ=0V, Io=10mA
TJ=1258C, 1000Hrs
Adjust Pin Current Change
Temperature Stability
Long Term Stability
0.5
0.3
1
%
TJ=258C, 10Hz<f<10KHz
0.003
%Vo
RMS Output Noise
Note 1: Low duty cycle pulse testing with Kelvin con- Note 3: Minimum load current is defined as the mini-
nections is required in order to maintain accurate data. mum current required at the output in order for the out-
put voltage to maintain regulation. Typically the resistor
Note 2: Dropout voltage is defined as the minimum dif- dividers are selected such that it automatically main-
ferential voltage between VIN and VOUT required to main- tains this current.
tain regulation at VOUT. It is measured when the output
voltage drops 1% below its nominal value.
Rev. 1.8
08/20/02
www.irf.com
2
IRU1050
PIN DESCRIPTIONS
PIN # PIN SYMBOL
PIN DESCRIPTION
1
2
Adj
A resistor divider from this pin to the VOUT pin and ground sets the output voltage.
VOUT
The output of the regulator. A minimum of 10µF capacitor must be connected from this pin
to ground to insure stability.
3
VIN
The input pin of the regulator. Typically a large storage capacitor is connected from this
pin to ground to insure that the input voltage does not sag below the minimum drop out
voltage during the load transient response. This pin must always be 1.3V higher than VOUT
in order for the device to regulate properly.
BLOCK DIAGRAM
VIN 3
2 VOUT
+
+
1.25V
CURRENT
LIMIT
THERMAL
SHUTDOWN
1 Adj
Figure 2 - Simplified block diagram of the IRU1050.
APPLICATION INFORMATION
Introduction
The IRU1050 adjustable Low Dropout (LDO) regulator is nanoseconds at the processor pins, which translates to
a three-terminal device which can easily be programmed an approximately 300 to 500ns current step at the regu-
with the addition of two external resistors to any volt- lator. In addition, the output voltage tolerances are also
ages within the range of 1.25 to 5.5 V. This regulator extremely tight and they include the transient response
unlike the first generation of the three-terminal regula- as part of the specification.For example Intel VREä
tors such as LM117 that required 3V differential between specification calls for a total of ±100mV including initial
the input and the regulated output, only needs 1.3V dif- tolerance, load regulation and 0 to 4.6A load step.
ferential to maintain output regulation. This is a key re-
quirement for today’s microprocessors that need typi- The IRU1050 is specifically designed to meet the fast
cally 3.3V supply and are often generated from the 5V current transient needs as well as providing an accurate
supply. Another major requirement of these micropro- initial voltage, reducing the overall system cost with the
cessors such as the Intel P54Cä is the need to switch need for fewer output capacitors.
the load current from zero to several amps in tens of
Rev. 1.8
08/20/02
www.irf.com
3
IRU1050
Output Voltage Setting
regulator and the load is gained up by the factor of (1+R2/
The IRU1050 can be programmed to any voltages in the R1), or the effective resistance will be RP(eff)=RP×(1+R2/
range of 1.25V to 5.5V with the addition of R1 and R2 R1). It is important to note that for high current applica-
external resistors according to the following formula:
tions, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to mini-
mize this effect.
R2
R1
VOUT = VREF× 1+
+IADJ×R2
( )
Where:
PARASITIC LINE
RESISTANCE
VREF = 1.25V Typically
IADJ = 50µA Typically
RP
VIN
Vin
VOUT
R1 and R2 as shown in Figure 3:
IRU1050
VOUT
VIN
VIN
VOUT
RL
Adj
R1
R2
IRU1050
Adj
VREF
R 1
R 2
IADJ = 50uA
Figure 4 - Schematic showing connection
for best load regulation.
Figure 3 - Typical application of the IRU1050
for programming the output voltage.
Stability
The IRU1050 keeps a constant 1.25V between the out- The IRU1050 requires the use of an output capacitor as
put pin and the adjust pin. By placing a resistor R1 across part of the frequency compensation in order to make the
these two pins a constant current flows through R1, add- regulator stable. Typical designs for microprocessor ap-
ing to the IADJ current and into the R2 resistor producing plications use standard electrolytic capacitors with a
a voltage equal to the (1.25/R1)×R2 + IADJ×R2 which typical ESR in the range of 50 to 100mΩ and an output
will be added to the 1.25V to set the output voltage. capacitance of 500 to 1000µF. Fortunately as the ca-
This is summarized in the above equation. Since the pacitance increases, the ESR decreases resulting in a
minimum load current requirement of the IRU1050 is fixed RC time constant. The IRU1050 takes advantage
10mA, R1 is typically selected to be 121Ω resistor so of this phenomena in making the overall regulator loop
that it automatically satisfies the minimum current re- stable. For most applications a minimum of 100µF alu-
quirement. Notice that since IADJ is typically in the range minum electrolytic capacitor such as Sanyo MVGX se-
of 50µA it only adds a small error to the output voltage ries, Panasonic FA series as well as the Nichicon PL
and should only be considered when a very precise out- series insures both stability and good transient response.
put voltage setting is required. For example, in a typical
3.3V application where R1=121Ω and R2=200Ω the er- Thermal Design
ror due to IADJ is only 0.3% of the nominal set point.
The IRU1050 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Load Regulation
Since the IRU1050 is only a three-terminal device, it is Although this device can operate with junction tempera-
not possible to provide true remote sensing of the output tures in the range of 1508C, it is recommended that the
voltage at the load. Figure 4 shows that the best load selected heat sink be chosen such that during maxi-
regulation is achieved when the bottom side of R2 is mum continuous load operation the junction tempera-
connected to the load and the top side of R1 resistor is ture is kept below this number. The example below shows
connected directly to the case or the VOUT pin of the the steps in selecting the proper regulator heat sink for
regulator and not to the load. In fact, if R1 is connected the worst case current consumption using Intel 200MHz
to the load side, the effective resistance between the microprocessor as the load.
Rev. 1.8
08/20/02
www.irf.com
4
IRU1050
Assuming the following specifications:
Air Flow (LFM)
100 200
0
300
400
VIN = 5V
Thermalloy
AAVID
6021PB 6021PB 6073PB 6109PB 7141D
534202B 534202B 507302 575002 576802B
VOUT = 3.5V
IOUT(MAX) = 4.6A
TA = 358C
Note: For further information regarding the above com-
The steps for selecting a proper heat sink to keep the panies and their latest product offerings and application
junction temperature below 1358C is given as:
support contact your local representative or the num-
bers listed below:
1) Calculate the maximum power dissipation using:
AAVID.................PH# (603) 528 3400
Thermalloy...........PH# (214) 243-4321
PD = IOUT×(VIN - VOUT)
PD = 4.6×(5 - 3.5) = 6.9W
Designing for Microprocessor Applications
2) Select a package from the regulator data sheet and As it was mentioned before, the IRU1050 is designed
record its junction to case (or tab) thermal resistance. specifically to provide power for the new generation of
the low voltage processors requiring voltages in the range
Selecting TO-220 package gives us:
of 2.5V to 3.6V generated by stepping down the 5V sup-
ply. These processors demand a fast regulator that sup-
ports their large load current changes. The worst case
θJC = 2.78C/W
3) Assuming that the heat sink is black anodized, cal- current step seen by the regulator is anywhere in the
culate the maximum heat sink temperature allowed: range of 1 to 7A with the slew rate of 300 to 500ns which
could happen when the processor transitions from “Stop
Assume, θcs=0.05°C/W (heat-sink-to-case thermal Clock” mode to the “Full Active” mode. The load current
resistance for black anodized)
step at the processor is actually much faster, in the or-
der of 15 to 20ns, however, the decoupling capacitors
placed in the cavity of the processor socket handle this
transition until the regulator responds to the load current
levels. Because of this requirement the selection of high
TS = TJ - PD×(θJC + θCS)
TS = 135 - 6.9×(27 + 0.05) = 1168C
4) With the maximum heat sink temperature calculated frequency low ESR and low ESL output capacitor is
in the previous step, the heat-sink-to-air thermal re- imperative in the design of these regulator circuits.
sistance (θSA) is calculated by first calculating the
temperature rise above the ambient as follows:
Figure 5 shows the effects of a fast transient on the
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the (∆VESR=ESR×∆I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (∆VESL
=L×∆I/∆t). The output capacitance effect is a droop in
∆T = TS - TA = 116 - 35 = 818C
DT = Temperature Rise Above Ambient
81
6.9
∆T
PD
θSA =
=
= 11.78C/W
5) Next, a heat sink with lower θSA than the one calcu- the output voltage proportional to the time it takes for
lated in Step 4 must be selected. One way to do this the regulator to respond to the change in the current,
is to simply look at the graphs of the “Heat Sink Temp (∆Vc=∆t×∆I/C) where ∆t is the response time of the
Rise Above the Ambient” vs. the “Power Dissipation” regulator.
and select a heat sink that results in lower tempera-
ture rise than the one calculated in previous step.
The following heat sinks from AAVID and Thermalloy
meet this criteria.
Rev. 1.8
08/20/02
www.irf.com
5
IRU1050
2) The output capacitance is 5×1500µF = 7500µF
V ESR
V ESL
∆t × ∆I
2 × 4.6
7500
∆Vc =
=
= 1.2mV
V C
C
T
Where:
∆t = 2µs is the regulator response time
LOAD
CURRENT
1050plt1-1.0
To set the output DC voltage, we need to select R1 and
R2:
LOAD CURRENT RISE TIME
3) Assuming R1=121Ω, 0.1%:
Figure 5 - Typical regulator response
to the fast load current step.
3.5
VOUT -1
-1
×121 = 217.8Ω
R2 =
×R1 =
( VREF ) ( 1.25 )
An example of a regulator design to meet the Intel P54Cä
VRE specification is given below.
Select R2=218Ω, 0.1%
Assume the specification for the processor as shown in
Table 1:
Selecting both R1 and R2 resistors to be 0.1% toler-
ance, results in the least amount of error introduced
by the resistor dividers leaving » ±1.3% error budget
for the IRU1050 reference which is within the initial
accuracy of the device.
Type of
VOUT
Nominal
3.50 V
IMAX
Max Allowed
Output Tolerance
±100 mV
Processor
Intel-P54C VRE
4.6 A
Table 1 - Processor Specification
Finally, the input capacitor is selected as follows:
The first step is to select the voltage step allowed in the 4) Assuming that the input voltage can drop 150mV be-
output due to the output capacitor’s ESR:
fore the main power supply responds, and that the
main power supply response time is » 50µs, then
the minimum input capacitance for a 4.6A load step
is given by:
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is » ±53mV (±1.5% of 3.5V
nominal), then the total step allowed for the ESR and
the ESL is - 47mV.
4.6 × 50
CIN =
= 1530µF
0.15
Assuming that the ESL drop is - 10mV, the remain-
ing ESR step will be - 37mV. Therefore the output
capacitor ESR must be:
The ESR should be less than:
(VIN - VOUT - ∆V - VDROP)
ESR =
∆I
37
4.6
ESR ≤
= 8mΩ
Where:
VDROP L Input voltage drop allowed in step 4
∆V L Maximum regulator dropout voltage
∆I L Load current step
The Sanyo MVGX series is a good choice to achieve
both price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typi-
cal. Selecting 5 of these capacitors in parallel has an
ESR of » 7.2mΩ which achieves our design goal.
(5 - 3.5 - 1.2 - 0.15)
ESR =
= 0.032Ω
4.6
The next step is to calculate the drop due to the ca-
pacitance discharge and make sure that this drop in
voltage is less than the selected ESL drop in the
previous step.
Selecting two Sanyo 1500µF, the same type as the
output capacitors, meets our requirements.
Rev. 1.8
08/20/02
www.irf.com
6
IRU1050
Figure 6 shows the completed schematic for our ex-
ample.
Layout Consideration
The output capacitors must be located as close to the
VOUT terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the VOUT pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
VOUT
VIN
5V
3.50V
C1
1500uF
C2
5x 1500uF
IRU1050
R1
Adj
121
0.1%
R2
218
0.1%
Figure 6 - Final schematic for
the Intel VRE application.
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.8
08/20/02
www.irf.com
7
IRU1050
(D) TO-252 Package
2-Pin
K
A
B
C
L
M
N
78
458
D
J
E
O
P
Q
R
G
F
S
H
R1
SYMBOL MIN
MAX
A
B
6.477 6.731
5.004 5.207
0.686 0.838
7.417 8.179
C
D
E
C
L
9.703 10.084
0.635 0.889
2.286 BSC
F
G
H
J
4.521 4.623
∅1.52 ∅1.62
2.184 2.388
0.762 0.864
K
L
M
N
O
P
1.016
1.118
5.969 6.223
1.016
0
1.118
0.102
Q
R
R1
S
0.534 0.686
R0.31 TYP
R0.51 TYP
0.428 0.588
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.8
08/20/02
www.irf.com
8
IRU1050
(M) TO-263 Package
3-Pin
A
E
U
K
S
V
B
M
H
L
P
D
G
N
R
C
C
L
SYMBOL
MIN
MAX
A
B
C
D
E
G
H
K
L
10.05 10.312
8.28
4.31
0.66
1.14
8.763
4.572
0.91
1.40
2.54 REF
14.73 15.75
1.40
0.00
2.49
0.33
1.68
0.254
2.74
M
N
P
R
S
U
V
0.58
2.286 2.794
08
88
2.41
2.67
6.50 REF
7.75 REF
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.8
08/20/02
www.irf.com
9
IRU1050
(P) Ultra Thin-PakTM
2-Pin
A
A1
E
U
K
B
V
H
M
L
P
G
D
G1
N
C
R
C
L
SYMBOL
MIN
5.91
5.54
6.02
1.70
0.63
0.17
2.16
4.45
9.42
0.76
0.02
0.89
0.25
0.94
28
MAX
6.17
5.79
6.27
2.03
0.79
0.33
2.41
4.70
9.68
1.27
0.13
1.14
0.25
1.19
68
A
A1
B
C
D
E
G
G1
H
K
L
M
N
P
R
U
V
2.92
3.30
5.08 NOM
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.8
08/20/02
www.irf.com
10
IRU1050
(T) TO-220 Package
3-Pin
H1
Q
L
b1
e3
e
e1
C
L E
b
R
E-PIN
CP
a (5x)
C1
J1
A
C
L
F
D
SYMBOL
MIN
4.06
38
MAX
A
a
4.83
7.58
b
0.63
1.14
0.38
1.02
1.52
0.56
b1
C1
CP
D
3.71D 3.96D
14.22 15.062
E
9.78
2.29
4.83
1.14
1.14
5.94
2.29
10.54
2.79
5.33
1.40
1.40
6.55
2.92
e
e1
e3
F
H1
J1
L
13.716 14.22
Q
2.62
2.87
6.17
R
5.588
NOTE: ALL MEASUREMENTS
ARE IN MILLIMETERS.
Rev. 1.8
08/20/02
www.irf.com
11
IRU1050
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
D
M
P
T
TO-252, (D-Pak)
TO-263
Ultra Thin-PakTM
2
3
2
3
75
50
75
50
2500
750
2500
---
Fig A
Fig B
Fig C
---
TO-220
1
1
1
1
1
1
Feed Direction
Figure A
Feed Direction
FigureB
1
1
1
Feed Direction
FigureC
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.8
08/20/02
www.irf.com
12
IRU1050CM 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| IRU1050CMTR | INFINEON | Adjustable Positive LDO Regulator, 1.25V Min, 5.5V Max, 1.3V Dropout, PSSO2, PLASTIC, TO-2 | 完全替代 |
|
IRU1050CM 相关器件
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| IRU1050CMPBF | INFINEON | Adjustable Positive LDO Regulator, 1.25V Min, 5.5V Max, 1.3V Dropout, PSSO2, PLASTIC, TO-263, 3 PIN | 获取价格 |
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| IRU1050CMTR | INFINEON | Adjustable Positive LDO Regulator, 1.25V Min, 5.5V Max, 1.3V Dropout, PSSO2, PLASTIC, TO-263, 3 PIN | 获取价格 |
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| IRU1050CTPBF | INFINEON | Adjustable Positive LDO Regulator, 1.25V Min, 5.5V Max, 1.3V Dropout, PSFM3, PLASTIC, TO-220, 3 PIN | 获取价格 |
|
| IRU1075 | INFINEON | 7.5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR | 获取价格 |
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| IRU1075CM | INFINEON | VOLT REGULATOR|ADJUSTABLE|+1.25 TO +5.5V|BIPOLAR|SIP|3PIN|PLASTIC | 获取价格 |
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| IRU1075CMPBF | INFINEON | Adjustable Positive LDO Regulator, 1.25V Min, 5.5V Max, 1.2V Dropout, PSSO2, PLASTIC, TO-263, 3 PIN | 获取价格 |
|
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