IRU3046CFPBF [INFINEON]
Dual Switching Controller, Voltage-mode, 0.5A, 450kHz Switching Freq-Max, PDSO24, PLASTIC, TSSOP-24;
| 型号： | IRU3046CFPBF |
| 厂家： | 
Infineon |
| 描述： | Dual Switching Controller, Voltage-mode, 0.5A, 450kHz Switching Freq-Max, PDSO24, PLASTIC, TSSOP-24 开关 光电二极管 |
| 文件： | 总20页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD94251
IRU3046
DUAL SYNCHRONOUS PWM CONTROLLER WITH
CURRENT SHARING CIRCUITRY AND LDO CONTROLLER
PRELIMINARY DATA SHEET
FEATURES
DESCRIPTION
The IRU3046 IC combines a Dual synchronous Buck
controller and a linear regulator controller, providing a
cost-effective, high performance and flexible solution for
Dual Synchronous Controller in 24-Pin Package
with 1808 out-of-phase operation
LDO Controller with Independent Bias Supply
Can be configured as 2-Independent or 2-Phase multi-output applications. The Dual synchronous con-
PWM Controller troller can be configured as 2-independent or 2-phase
Programmable Current Sharing in 2-Phase Configu- controller. In 2-phase configuration, the IRU3046 provides
ration
a programmable current sharing which is ideal when the
output power exceeds any single input power budget.
IRU3046 provides a separate adjustable output by driv-
Flexible, Same or Separate Supply Operation
Operation from 4V to 25V Input
Programmable Switching Frequency up to 400KHz ing a switch as a linear regulator. This device features
Soft-Start controls all outputs
programmable switching frequency up to 400KHz per
phase, under-voltage lockout for all input supplies, an
external programmable soft-start function as well as out-
put under-voltage detection that latches off the device
when an output short is detected.
Precision Reference Voltage Available
500mA Peak Output Drive Capability
Short Circuit Protection for all outputs
Power Good Output
Synchronizable with External Clock
APPLICATIONS
Graphic Card
Hard Disk Drive
Dual-Phase Power Supply
DDR Memory Source Sink Vtt Application
Power supplies requiring multiple outputs
TYPICAL APPLICATION
D1
D2
12V
L1
C12
C11
5V
L2
C1
C2
C3
C4
C13
VCL
Vcc
VcH1 VcH2
HDrv1
Q2
Q3
C14
L3
R5
C5
VOUT1
C16
VccLDO
VSEN33
C15
R6
LDrv1
3.3V
Q1
VOUT3
C6
PGnd
VREF
Vp2
Fb1
R1
C7
U1
IRU3046
VOUT2
Fb3
R7
R8
Rt
R2
Sync
Comp1
R3
C8
C9
Fb2
R4
C17
Q4
Q5
Comp2
HDrv2
L4
R9
C18
R10
PGood
PGood
SS
LDrv2
Gnd
C10
Figure 1 - Typical application of IRU3046 configured as 2-phase converter with current sharing.
PACKAGE ORDER INFORMATION
TA (°C)
DEVICE
PACKAGE
FREQUENCY
0 To 70
IRU3046CF
24-Pin Plastic TSSOP (F)
200-400KHz
Rev. 1.9
09/27/02
www.irf.com
1
IRU3046
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage .................................................. 25V
VccLDO, VcH1, VcH2 and VCL Supply Voltage ........... 30V (not rated for inductive load)
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
PACKAGE INFORMATION
24-PIN PLASTIC TSSOP (F)
TOP VIEW
VREF 1
Vp2 2
Fb2 3
24 Gnd
qJA = 84°C/W
23 PGood
22 V
SEN33
Vcc
Comp1
Comp2
Rt
4
5
6
7
21 Fb1
20
SS
19 Fb3
18
VOUT3
17 VccLDO
16
Sync 8
9
VcH2
HDrv2 10
11
VcH1
15 HDrv1
14
LDrv2
PGnd 12
LDrv1
13 VCL
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, VcH1=VcH2=VCL=VccLDO=12V and TA=0 to
70°C. Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case tem-
peratures equal to the ambient temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP
MAX UNITS
Reference Voltage Section
Fb Voltage
Fb Voltage Line Regulation
UVLO Section
VFB
LREG
1.225 1.250 1.275
0.2
V
%
5<Vcc<12
UVLO Threshold - Vcc
UVLOVCC Supply Ramping Up
UVLOVCCLDO Supply Ramping Up
UVLOVCH1 Supply Ramping Up
UVLOVCH2 Supply Ramping Up
UVLOFb Fb Ramping Down
UVLOVSEN33 Supply Ramping Up
4.2
0.25
4.2
0.25
3.5
0.2
3.5
0.2
0.6
0.1
2.5
0.2
V
V
V
V
V
V
V
V
V
V
V
V
UVLO Hysteresis - Vcc
UVLO Threshold - VccLDO
UVLO Hysteresis - VccLDO
UVLO Threshold - VcH1
UVLO Hysteresis - VcH1
UVLO Threshold - VcH2
UVLO Hysteresis - VcH2
UVLO Threshold - Fb
UVLO Hysteresis - Fb
UVLO Threshold - VSEN33
UVLO Hysteresis - VSEN33
Supply Current Section
Vcc Dynamic Supply Current
VcH1 Dynamic Supply Current
VcH2 Dynamic Supply Current
Vcc Static Supply Current
VcH1 Static Supply Current
VcH2 Static Supply Current
VccLDO Static Supply Current
Dyn ICC
Freq=200KHz, CL=1500pF
5
7
7
3.5
2
2
mA
mA
mA
mA
mA
mA
mA
Dyn ICH1 Freq=200KHz, CL=1500pF
Dyn ICH2 Freq=200KHz, CL=1500pF
ICCQ
SS=0V
SS=0V
SS=0V
SS=0V
ICH1Q
ICH2Q
ICLDO
1
Rev. 1.9
09/27/02
www.irf.com
2
IRU3046
PARAMETER
SYM
TEST CONDITION
SS=0V
MIN
TYP
MAX UNITS
Soft-Start Section
Charge Current
SSIB
15
25
30
µA
Power Good Section
Fb1 Lower Trip Point
Fb1 Upper Trip Point
Fb2 Lower Trip Point
Fb2 Upper Trip Point
Fb3 Lower Trip Point
Fb3 Upper Trip Point
Power Good Voltage OK
Error Amp Section
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
Transconductance 1
Transconductance 2
Input Offset Voltage for PWM2
Oscillator Section
PGFB1L
PGFB1H
PGFB2L
PGFB2H
PGFB3L
PGFB3H
VPG
Fb1 Ramping Down
Fb1 Ramping Up
Fb2 Ramping Down
Fb2 Ramping Up
Fb3 Ramping Down
Fb3 Ramping Up
5K resistor pulled up to 5V
0.9VREF
1.1VREF
0.9VREF
1.1VREF
0.9VREF
1.1VREF
4.8
V
V
V
V
V
V
V
4.5
-2
5
IFB1
IFB2
gm1
SS=3V
SS=0V
-0.1
-64
400
600
0
µA
µA
µmho
µmho
mV
gm2
VOS(ERR)2
Fb2 to VP2
+2
Frequency
Freq
Rt=Open
Rt=Gnd
180
300
200
350
1.25
220
450
KHz
V
Ramp Amplitude
Output Drivers Section
Rise Time
VRAMP
Tr
Tf
TDB
TON
TOFF
CL=1500pF
CL=1500pF
35
50
150
90
0
100
100
250
ns
ns
ns
%
%
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
LDO Controller Section
Drive Current
50
85
0
Fb=1V, Freq=200KHz
Fb=1.5V
ILDO
VFBLDO
ILDO(BIAS)
30
1.225
45
mA
V
µA
Fb Voltage
Input Bias Current
1.25 1.275
0.5
2
PIN DESCRIPTIONS
PIN# PIN SYMBOL
PIN DESCRIPTION
1
2
VREF
Vp2
Reference Voltage.
Non-inverting input to the second error amplifier. In the current sharing mode, it is con-
nected to the programming resistor. In independent 2-channel mode it is connected to
VREF pin when Fb2 is connected to the resistor divider to set the output voltage.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
3
21
Fb2
Fb1
4
Vcc
Supply voltage for the internal blocks of the IC.
5,6 Comp1, Comp2 Compensation pins for the error amplifiers.
7
Rt
The switching frequency can be programmed between 200KHz and 400KHz by connect-
ing a resistor between Rt and Gnd. By floating the pin, the switching frequency will be
200KHz and by grounding the pin, the switching frequency will be 400KHz.
The internal oscillator may be synchronized to an external clock via this pin.
Supply voltage for the high side output drivers. These are connected to voltages that must
be at least 4V higher than their bus voltages (assuming 5V threshold MOSFET). A mini-
mum of 1µF, high frequency capacitor must be connected from these pins to PGnd to
provide peak drive current capability.
8
9
16
Sync
VcH2
VcH1
Rev. 1.9
09/27/02
www.irf.com
3
IRU3046
PIN# PIN SYMBOL
PIN DESCRIPTION
10,15 HDrv2, HDrv1 Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148,
from these pins to ground for the application when the inductor current goes negative
(Source/Sink), soft-start at no load and for the fast load transient from full load to no load.
11,14 LDrv2, LDrv1
Output driver for the synchronous power MOSFET.
12
PGnd
This pin serves as the separate ground for MOSFET’s driver and should be connected to
the system’s ground plane. A high frequency capacitor (0.1 to 1µF) must be connected
from Vcc, VCL, VcH1 and VcH2 pins to this pin for noise free operation.
Supply voltage for the low side output drivers.
Separate input supply for LDO controller.
Driver signal for the LDO’s external transistor.
LDO’s feedback pin, connected to a resistor divider to set the output voltage of LDO.
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin below 0.5V.
Sense the LDO input voltage for UVLO.
13
17
18
19
20
VCL
VccLDO
VOUT3
Fb3
SS
22
23
VSEN33
PGood
Power good pin. This pin is a collector output that switches Low when any of the outputs
are outside of the specified under voltage trip point.
24
Gnd
Analog ground for internal reference and control circuitry. Connect to PGnd with a short
trace.
BLOCK DIAGRAM
4
16 VcH1
15 HDrv1
Vcc
VSEN33
SS
10K
25uA
3V
Bias
Generator
22
20
1.25V
64uA Max
4.2V
2.5V
/
/
4.0V
2.3V
POR
UVLO
Vsen33
VcH1
3.5V
3.5V
4.2V
/
/
3.3V
3.3V
4.0V
VcH2
13
14
VCL
/
POR
VccLDO
PWM Comp1
Error Amp1
LDrv1
25K
25K
1.25V
S
R
SS>2V
Q
Fb1 21
Ramp1
Ramp2
Set1
Set2
5
Comp1
Rt
9
ResetDom
VcH2
Two Phase
Oscillator
7
10
HDrv2
8
1
Sync
VREF
S
1.25V
25K
PWM Comp2
Q
Error Amp2
Vp2
Fb2
2
R
ResetDom
25K
3
6
0.5V
11 LDrv2
Fb2 Monitor Shut Down
PGnd
12
POR
Comp2
Fb1
PGood
Fb2
Fb3
PGood
23
17 VccLDO
25K
1.25V
VOUT3
Gnd
18
24
2V
SS
25K
Fb3 19
40mA LDO Controller
Figure 2 - Block diagram of the IRU3046.
www.irf.com
Rev. 1.9
09/27/02
4
IRU3046
THEORY OF OPERATION
Introduction
Soft-Start
The IRU3046 is designed for multi-outputs applications. The IRU3046 has a programmable soft start to control
It includes two synchronous buck controllers and a lin- the output voltage rise and limit the current surge at the
ear regulator controller. The two synchronous controller start-up. To ensure correct start-up, the soft-start se-
operates with fixed frequency voltage mode and can be quence initiates when the Vcc, VcH1, VcH2, VccLDO
configured as two independent controller or 2-phase con- and VSEN33 rise above their threshold and generates the
troller with current sharing. The timing of the IC is pro- Power On Reset (POR) signal. Soft-start function oper-
vided through an internal oscillator circuit. These are two ates by sourcing an internal current to charge an exter-
out of phase oscillators and can be programmed by us- nal capacitor to about 3V. Initially, the soft-start function
ing an external resistor from 200KHz to 400KHz per clamps the E/A’s output of the PWM converter. As the
phase. Figure 11 shows switching frequency versus ex- charging voltage of the external capacitor ramps up, the
ternal resistor.
PWM signals increase from zero to the point the feed-
back loop takes control.
Independent Mode
In this mode the IRU3046 provides two independent out- Shutdown
puts with either common or different input voltages. The The converter can be shutdown by pulling the soft-start
output voltage of the individual channel is set and con- pin below 0.5V. This can be easily done by using an
trolled by the output of the error amplifier, this is the external small signal transistor. During shutdown the
amplified error signal from the sensed output voltage and MOSFET drivers and the LDO controller turn off.
the reference voltage. This voltage is compared to the
ramp signal and generates fixed frequency pulses of vari- Power Good
able duty-cycle, which drives the two N-channel exter- The IRU3046 provides a power good signal. This is an
nal MOSFETs.
open collector output and it is pulled low if the output
voltages are not within the specified threshold. This pin
can be left floating if not used.
Current Sharing Mode
In the current sharing mode, the two converter’s outputs
tied together and provide one single output (see Figure Short-Circuit Protection
1). In this mode, one control loop acts as a master and The outputs are protected against the short circuit. The
sets the output voltage as a regular Voltage Mode buck IRU3046 protects the circuit for shorted output by sens-
controller and the other control loop acts as a slave and ing the output voltages. The IRU3046 shuts down the
monitors the current information for current sharing. The PWM signals and LDO controller, when the output volt-
current sharing is programmable and sets by using two ages drops below the set values.
external resistors in output currents’ path. The slave's
error amplifier, error amplifier 2 (see Block Diagram) mea- Under-Voltage Lockout
sures the voltage drops across the current sense resis- The under-voltage lockout circuit assures that the
tors, the differential of these signals is amplified and MOSFET driver outputs and LDO controller remain in
compared with the ramp signal and generate the fixed the off state whenever the supply voltages drop below
frequency pulses of variable duty cycle to match the set parameters. Normal operation resumes once the
output currents.
supply voltages rise above the set values.
Out of Phase Operation
Frequency Synchronization
The IRU3046 drives its two output stages 180o out of The IRU3046 can be synchronized with an external clock
phase. In 2-phase configuration, the two inductor ripple signal. The synchronizing pulses must have a minimum
currents cancel each other and result to a reduction of pulse width of 100ns. If the sync function is not used,
the output current ripple and contribute to a smaller out- the Sync pin can be either connected to ground or be
put capacitor for the same ripple voltage requirement.
floating.
In application with single input voltage, the 2-phase con-
figuration reduces the input ripple current. This results in
much smaller RMS current in the input capacitor and
reduction of input capacitor.
Rev. 1.9
09/27/02
www.irf.com
5
IRU3046
APPLICATION INFORMATION
Design Example:
Soft-Start Programming
The following example is a typical application for IRU3046 The soft-start timing can be programmed by selecting
in current sharing mode. The schematic is Figure 13 on the soft start capacitance value. The start up time of the
page 15.
converter can be calculated by using:
For Switcher:
For Linear Regulator:
VIN3 = 3.3V
VOUT2 = 2.5V
IOUT2 = 2A
t
START = 75 × Css (ms)
---(2)
VIN1(MASTER) = 5V
VIN2(SLAVE) = 12V
VOUT1 = 1.5V
IOUT = 16A
∆VOUT = 75mV
fS = 200KHz
Where:
CSS is the soft-start capacitor (µF)
For a start-up time of 7.5ms, the soft-start capacitor will
be 0.1µF. Choose a ceramic capacitor at 0.1µF.
PWM Section
Boost Supply
To drive the high-side switch it is necessary to supply a
gate voltage at least 4V greater than the bus voltage.
Output Voltage Programming
Output voltage is programmed by reference voltage and This is achieved by using a charge pump configuration
external voltage divider. The Fb1 pin is the inverting input as shown in Figure 1. The capacitor is charged up to
of the error amplifier, which is internally referenced to approximately twice the bus voltage. A capacitor in the
1.25V. The divider is ratioed to provide 1.25V at the Fb1 range of 0.1µF to 1µF is generally adequate for most
pin when the output is at its desired value. The output applications.
voltage is defined by using the following equation:
Sense Resistor Selection
R6
R5
These resistors will determine the current sharing
between two channels. The relationship between the
Master and Slave output currents is expressed by:
VOUT1 = VREF × 1 +
---(1)
( )
When an external resistor divider is connected to the
output as shown in Figure 3.
RSEN1 × IMASTER = RSEN2 × ISLAVE
---(3)
For an equal current sharing, RSEN1=RSEN1
Choose RSEN1=RSEN2=5mΩ
VOUT1
IRU3046
Fb1
Input Capacitor selection
R
6
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
ripple current generated during the on time of control
MOSFET should be provided by input capacitor. The RMS
value of this ripple is expressed by:
R5
Figure 3 - Typical application of the IRU3046 for
programming the output voltage.
IRMS = IOUT
D×(1-D)
---(4)
Where:
Equation (1) can be rewritten as:
D is the Duty Cycle, simply D=VOUT/VIN.
IRMS is the RMS value of the input capacitor current.
IOUT is the output current for each channel.
VOUT1
R6 = R5 ×
- 1
( VREF )
For VIN1=5V, IOUT1=8A and D1=0.3
Results to: IRMS1=3.6A
This will result to:
VOUT1 = 1.5V, VREF = 1.25V, R5 = 1K, R6 = 200Ω
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage set point can be
more accurate by using precision resistor.
And for VIN2=12V, IOUT2=8A and D2=0.125
Results to: IRMS2=2.6A
Rev. 1.9
09/27/02
www.irf.com
6
IRU3046
For higher efficiency, a low ESR capacitor is recom- For the buck converter, the inductor value for desired
mended.
operating ripple current can be determined using the fol-
lowing relation:
∆i
∆t
VOUT
VIN
For VIN1=5V, choose two Poscap from Sanyo
6TPB330M (6.3V, 330µF, 40mΩ, 3A)
1
fS
VIN - VOUT = L×
; ∆t = D×
; D =
VOUT
VIN×∆i×fS
L = (VIN - VOUT)×
---(6)
For VIN2=12V, choose two 16TPB47M (16V, 47µF,
70mΩ, 1.4A).
Where:
VIN = Maximum Input Voltage
VOUT = Output Voltage
Di = Inductor Ripple Current
fS = Switching Frequency
Dt = Turn On Time
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy sta-
bility requirements. The ESR of the output capacitor is
calculated by the following relationship:
D = Duty Cycle
For ∆i1=30% of I1, we get: L1=2.18µH
For ∆i2=30% of I2, we get: L2=2.7µH
∆VO
∆IO
The Coilcraft DO5022HC series provides a range of in-
ductors in different values and low profile for large cur-
rents.
ESR ≤
---(5)
Where:
∆VO = Output Voltage Ripple
∆IO = Output Current
For L1 choose: DO5022P-222HC (2.2µH,12A)
For L2 choose: DO5022P-332HC (3.3µH,10A)
∆VO=75mV and ∆IO=10A, result to ESR=7.5mΩ
Power MOSFET Selection
The Sanyo TPC series, Poscap capacitor is a good choice. The selections criteria to meet power transfer require-
The 6TPC150M 150µF, 6.3V has an ESR 40mΩ. Se- ments is based on maximum drain-source voltage (VDSS),
lecting six of these capacitors in parallel, results to an gate-source drive voltage (VGS), maximum output cur-
ESR of @ 7mΩ which achieves our low ESR goal.
rent, On-resistance RDS(ON) and thermal management.
The capacitor value must be high enough to absorb the The MOSFET must have a maximum operating voltage
inductor's ripple current. The larger the value of capaci- (VDSS) exceeding the maximum input voltage (VIN).
tor, the lower will be the output ripple voltage.
The gate drive requirement is almost the same for both
The resulting output ripple current is smaller then each MOSFETs. Caution should be taken with devices at very
channel ripple current due to the 1808 phase shift. These low VGS to prevent undesired turn-on of the complemen-
currents cancel each other. The cancellation is not the tary MOSFET, which results a shoot-through current.
maximum because of the different duty cycle for each
channel.
The total power dissipation for MOSFETs includes con-
duction and switching losses. For the Buck converter
the average inductor current is equal to the DC load cur-
Inductor Selection
The inductor is selected based on output power, operat- rent. The conduction loss is defined as:
2
ing frequency and efficiency requirements. Low induc-
tor value causes large ripple current, resulting in the
smaller size, but poor efficiency and high output noise.
Generally, the selection of inductor value can be reduced
PCOND (Upper Switch) = ILOAD × RDS(ON) × D × ϑ
2
PCOND (Lower Switch) = ILOAD × RDS(ON) × (1 - D) × ϑ
to desired maximum ripple current in the inductor (Di);
the optimum point is usually found between 20% and
ϑ = RDS(ON) Temperature Dependency
50% ripple of the output current.
The total conduction loss is defined as:
PCON(TOTAL)=PCON(Upper Switch)ϑ + PCON(Lower Switch)ϑ
Rev. 1.9
09/27/02
www.irf.com
7
IRU3046
The RDS(ON) temperature dependency should be consid- From IRF7460 data sheet we obtain:
ered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
IRF7460
tr = 6.9ns
tf = 4.3ns
These values are taken under a certain condition test.
Choose IRF7460 for control MOSFET and IRF7457 for For more detail please refer to the IRF7460 and IRF7457
synchronous MOSFET. These devices provide low on- data sheets.
resistance in a compact SOIC 8-Pin package.
By using equation (7), we can calculate the switching
The MOSFETs have the following data:
losses.
IRF7460
IRF7457
PSW(MASTER) = 44.8mW
VDSS = 20V
VDSS = 20V
PSW(SLAVE) = 107.5mW
ID = 10A @ 758C
RDS(ON) = 10mΩ @
VGS=10V
ϑ = 1.8 for 1508C
(Junction Temperature) (Junction Temperature)
ID = 12A @ 708C
RDS(ON) = 7.5mΩ @
VGS=10V
Feedback Compensation
The control scheme for master and slave channels is
based on voltage mode control, but the compensation of
these two feedback loops is slightly different.
ϑ = 1.5 for 1508C
The total conduction losses for the master channel is:
The Master channel sets the output voltage and its feed-
back loop should take care of double pole introduced by
the output filter as a regular voltage mode control loop.
The goal is to provide a close loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin. The slave feedback loop acts slightly different
PCON(MASTER) = 0.85W
The total conduction losses for the slave channel is:
PCON(SLAVE) = 0.77W
The control MOSFET contributes to the majority of the and its goal is using the current information for current
switching losses in synchronous Buck converter. The sharing.
synchronous MOSFET turns on under zero-voltage con-
dition, therefore the turn on losses for synchronous The master feedback loop sees the output filter. The out-
MOSFET can be neglected. With a linear approxima- put LC filter introduces a double pole, -40dB/decade gain
tion, the total switching loss can be expressed as:
slope above its corner resonant frequency, and a total
phase lag of 1808 (see Figure 5). The resonant frequency
of the LC filter expressed as follows:
VDS(OFF)
tr + tf
T
PSW =
×
× ILOAD
---(7)
2
Where:
1
FLC(MASTER) =
---(8)
VDS(OFF) = Drain to Source Voltage at off time
2π Lo×Co
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
Figure 5 shows gain and phase of the LC filter. Since we
already have 1808 phase shift just from the output filter,
the system risks being unstable.
DS
V
Gain
0dB
Phase
90%
08
-40dB/decade
10%
-180
8
FLC Frequency
FLC Frequency
VGS
t
d
(ON)
td(OFF)
tr
tf
Figure 5 - Gain and phase of LC filter.
Figure 4 - Switching time waveforms.
Rev. 1.9
09/27/02
www.irf.com
8
IRU3046
The master error amplifier is a differential-input transcon- First select the desired zero-crossover frequency (Fo):
ductance amplifier. The output is available for DC gain
control or AC phase compensation.
FO1 > FESR and FO1 ≤ (1/5 ~ 1/10)× fS
Use the following equation to calculate R4:
The E/A can be compensated with or without the use of
1
VOSC
FO1×FESR R5 + R6
local feedback. When operated without local feedback
the transconductance properties of the E/A become evi-
dent and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp1 pin to ground as shown in Figure 6.
R4 =
×
×
×
---(13)
2
VIN(MASTER)
FLC
R5
gm
Where:
VIN(MASTER) = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
FO1 = Crossover Frequency for the master E/A
FESR = Zero Frequency of the Output Capacitor
FLC(MASTER) = Resonant Frequency of Output Filter
gm = Error Amplifier Transconductor
R5 and R6 = Resistor Dividers for Output Voltage
Programming
The ESR zero of the LC filter expressed as follows:
1
FESR =
---(9)
2π×ESR×Co
VOUT
For:
VIN(MASTER) = 5V
VOSC = 1.25V
FO1 = 30KHz
FESR = 25.26KHz
FLC(MASTER) = 3.57KHz
R5 = 1K
R
6
Fb1
Comp1
E/A1
Ve
R5
C9
VREF
R4
R6 = 200Ω
gm = 600µmho
Gain(dB)
H(s) dB
This results to: R4=29.7KΩ. Choose: R4=29.4KΩ
To cancel one of the LC filter poles, place the zero be-
fore the LC filter resonant frequency pole:
Frequency
FZ
FZ @ 75%FLC(MASTER)
Figure 6 - Compensation network without local
feedback and its asymptotic gain plot.
1
FZ @ 0.75 ×
---(14)
2π LO × CO
The transfer function (Ve / VOUT) is given by:
For:
Lo = 2.2µH
Co = 900µF
Fz = 2.67KHz
R4 = 24.9KΩ
R5
R6 + R5
1 + sR4C9
sC9
H(s) = gm×
×
---(10)
( )
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain Using equations (12) and (14) to calculate C9, we get:
and zero, expressed by:
C9 = 2003pF
Choose: C9 = 2200pF
R5
R6 × R5
|H(s)| = gm ×
× R4
---(11)
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
pole is given by:
1
FZ =
---(12)
2π × R4 × C9
The gain is determined by the voltage divider and E/A's
transconductance gain.
1
FP =
C9 × CPOLE
2π × R4 ×
C9 + CPOLE
Rev. 1.9
09/27/02
www.irf.com
9
IRU3046
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
As known, transconductance amplifier has high imped-
ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli-
fier will not be able to swing its output voltage over the
necessary range.
1
1
CPOLE =
@
π × R4 × fS
1
C9
π × R4 × fS -
fS
For FP <<
2
The compensation network has three poles and two ze-
ros and they are expressed as follows:
For a general solution for unconditionally stability for any
type of output capacitors, in a wide range of ESR values
we should implement local feedback with a compensa-
tion network. The typically used compensation network
for voltage-mode controller is shown in Figure 7.
FP1 = 0
1
FP2 =
2π×R8×C10
1
V
OUT
1
ZIN
FP3 =
@
C
12
2π×R7×C12
C12×C11
2π×R7×
(C12+C11 )
C
10
R7
C
11
1
R8
R
6
Z
f
FZ1 =
FZ2 =
2π×R7×C11
1
1
Fb1
@
E/A1
Ve
2π×C10×(R6 + R8)
2π×C10×R6
R
5
Comp1
Cross Over Frequency:
VREF
Gain(dB)
VIN
1
FO1 = R7×C10×
×
---(16)
VOSC
2π×Lo×Co
H(s) dB
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Frequency
F
Z
1
F
Z
2
F
P
2
FP3
Co = Total Output Capacitors
Figure 7 - Compensation network with local
feedback and its asymptotic gain plot.
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (15) regarding transconduc-
tance error amplifier.
In such configuration, the transfer function is given by:
1 - gmZf
1 + gmZIN
Ve
VOUT
=
1) Select the crossover frequency:
The error amplifier gain is independent of the transcon-
ductance under the following condition:
Fo < FESR and Fo ≤ (1/10 ~ 1/6)× fS
gmZf >> 1
and
gmZIN >>1
---(15)
2
2) Select R7, so that R7 >>
gm
By replacing ZIN and Zf according to figure 7, the trans-
former function can be expressed as:
3) Place first zero before LC’s resonant frequency pole.
1
(1+sR7C11)×[1+sC10(R6+R8)]
×
H(s)=
FZ1 @ 75% FLC
C12C11
sR6(C12+C11)
1+sR7
×(1+sR8C10)
[ (C12+C11)]
1
C11 =
2π × FZ1 × R7
Rev. 1.9
09/27/02
www.irf.com
10
IRU3046
4) Place third pole at the half of the switching frequency. The transfer function of power stage is expressed by:
IL2(s)
Ve(s)
VIN - VOUT
sL2 × VOSC
fS
2
G(s) =
=
---(17)
FP3 =
C12 =
1
Where:
2π × R7 × FP3
VIN = Input Voltage
VOUT = Output Voltage
L2 = Output Inductor
VOSC = Oscillator Peak Voltage
C12 > 50pF
If not, change R7 selection.
5) Place R7 in (16) and calculate C10:
As shown the transfer function is a function of inductor
current.
2π × Lo × FO × Co
VOSC
VIN
C10 ≤
×
R7
The transfer function for the compensation network is
given by equation (18), when using a series RC circuit
as shown in Figure 8:
6) Place second pole at ESR zero.
FP2 = FESR
1
RS1
Ve(s)
RS2 × IL2(s)
1 + sC2R2
R8 =
---(18)
g
=
m×
×
D(s) =
( ) ( )
2π × C10 × FP2
RS2
sC2
1
Check if R8 >
gm
IL2
L2
If R8 is too small, increase R7 and start from step 2.
Fb2
7) Place second zero around the resonant frequency.
Comp2
RS2
FZ2 = FLC
E/A2
Ve
Vp2
1
R
2
R6 =
- R8
R
S1
2π × C10 × FZ2
C
2
L
1
8) Use equation (1) to calculate R5:
IL1
VREF
VOUT - VREF
R5 =
× R6
Figure 8 - The PI compensation network
for slave channel.
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient speed. The gain margin will be large enough to
provide high DC-regulation accuracy (typically -5dB to -
12dB). The phase margin should be greater than 458 for
overall stability.
The loop gain function is:
H(s)=[G(s)× D(s)× RS2]
RS1
1+sR2C2
VIN-VOUT
sL2×VOSC
×
H(s)=RS2× gm×
×
( ) ( ) ( )
RS2
sC2
Select a zero crossover frequency (FO2) one-tenth of the
switching frequency:
The slave error amplifier is a differential-input transcon-
ductance amplifier as well, the main goal for the slave
feed back loop is to control the inductor current to match
the masters inductor current as well provides highest
bandwidth and adequate phase margin for overall stabil-
ity.
fS
FO2 =
10
FO2 = 20KHz
Rev. 1.9
09/27/02
www.irf.com
11
IRU3046
VIN - VOUT
2π×Fo×L2×VOSC
LDO Power MOSFET Selection
H(Fo) = gm×RS1×R2×
=1
---(19)
---(20)
The first step in selecting the power MOSFET for the
linear regulator is to select the maximum RDS(ON) based
on the input to the dropout voltage and the maximum
load current.
From (18), R2 can be express as:
1
2π × FO2 × L2 × VOSC
R2 =
×
VIN3 - VOUT2
RDS(ON) =
VIN(SLAVE) - VOUT
g
m × RS1
IOUT2
For:
Set the zero of compensator to be half of FLC(SLAVE), the
compensator capacitor, C2, can be calculated as:
VIN3 = 3.3V
VOUT2 = 2.5V
IOUT2 = 2A
1
FLC(SLAVE) =
Results to: RDS(ON)(MAX) = 0.4Ω
2π
L2×COUT
FLC(SLAVE)
Note that since the MOSFET RDS(ON) increases with tem-
perature, this number must be divided by ~1.5 in order
to find the RDS(ON)(MAX) at room temperature. The IRLR2703
has a maximum of 0.065Ω RDS(ON) at room temperature,
which meets our requirements.
Fz =
C2 =
2
1
---(21)
2π × R2 × Fz
Using equations (20) and (21) we get the following val-
ues for R2 and C2.
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
R2=16.45K; Choose: R2=16.5K
C2=6606pF; Choose: C2=6800pF
LDO Section
Start to place the power components, make all the con-
nection in the top layer with wide, copper filled areas.
Output Voltage Programming
Output voltage for LDO is programmed by reference volt- The inductor, output capacitor and the MOSFET should
age and external voltage divider. The Fb3 pin is the in- be close to each other as possible. This helps to reduce
verting input of the error amplifier, which is internally ref- the EMI radiated by the power traces due to the high
erenced to 1.25V. The divider is ratioed to provide 1.25V switching currents through them. Place input capacitor
at the Fb3 pin when the output is at its desired value. directly to the drain of the high-side MOSFET, to reduce
The output voltage is defined by using the following equa- the ESR replace the single input capacitor with two par-
tion:
allel units. The feedback part of the system should be
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
one layer as power ground plane and have a control cir-
cuit ground (analog ground), to which all signals are ref-
erenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.
R7
R10
VOUT2 = VREF× 1+
( )
For:
VOUT2 = 2.5V
VREF = 1.25V
R10 = 1KΩ
Results to R7=1KΩ
VOUT3
IRU3046
R7
Fb3
R10
Figure 9 - Programming the output voltage for LDO.
Rev. 1.9
09/27/02
www.irf.com
12
IRU3046
TYPICAL APPLICATION
12V
D1
D2
C2
33uF
L2
1uH
C11
0.1uF
L1
5V
1uH
C1
33uF
C13
1uF
C14
2x 47uF
C3
1uF
C4
1uF
V
CL
VcH1 VcH2
HDrv1
Q2
IRF7460
L3
Vcc
VccLDO
C5
1uF
1.8V
@ 8A
C16
4.7uH
LDrv1
PGnd
Q3
IRF7457
3.3V
C6
47uF
V
SEN33
2x 150uF
Q1
VOUT3
IRLR2703
R1
R7
442
U1
IRU3046
Ω
2.5V
@ 2A
Fb3
Rt
Fb1
1K
C7
47uF
R2
1K
VREF
C17
2x 150uF
R8
1K
Sync
Vp2
HDrv2
Q4
IRF7457
L4
R3
2.5V
@ 8A
Comp1
Comp2
C8
2200pF
22K
3.9uH
Q5
IRF7457
LDrv2
Fb2
C12
2x 150uF
R4
C9
1500pF
25K
R5
1K
PGood
PGood
SS
Gnd
C10
0.1uF
R9
1K
Figure 10 - Typical application for IRU3046 configured as two independent controllers.
Switching Frequency vs. Rt
400
370
340
310
280
250
220
190
0
100
200
300
400
500
600
Rt
Figure 11 - Switching frequency per phase vs. Rt
Rev. 1.9
09/27/02
www.irf.com
13
IRU3046
TYPICAL APPLICATION
12V
L1
5V
1uH
C14
150uF
C1
33uF
C13
1uF
C4
1uF
C3
1uF
V
CL
VcH1 VcH2
HDrv1
1/2 of Q2
IRF7313
L2
C5
1uF
Vcc
VccLDO
1/2 of D1
BAT54A
VDDQ
5.6uH
2.5V @ 4A
C16
330uF
LDrv1
1/2 of Q2
IRF7313
3.3V
C6
47uF
V
SEN33
Q1
VOUT3
R7
1K
IRLR2703
R1
PGnd
Fb1
U1
IRU3046
1.8V
@ 2A
Fb3
Rt
R8
1K
442
C17
2x 150uF
R2
1K
C7
47uF
VREF
Sync
1/2 of Q3
IRF7313
HDrv2
L3
R3
1/2 of D1
BAT54A
V
TT
Comp1
Comp2
C8
3900pF
1.25V @ 4A
C12
330uF
4.7uH
16.2K
1/2 of Q3
IRF7313
LDrv2
R4
C9
5600pF
10K
Fb2
Vp2
PGood
PGood
SS
R5
1K
VDDQ
Gnd
C10
0.1uF
R9
1K
Figure 12 - Typical application for IRU3046 configured for DDR memory application.
Rev. 1.9
09/27/02
www.irf.com
14
IRU3046
DEMO-BOARD APPLICATION
Dual Input: 5V and 12V to 1.5V @ 16A
5V
C1
33uF
12V
L1
1uH
C2
33uF
L2
1uH
D1
BAT54S
C3
0.1uF
C4
47uF
C5
330uF
C7
1uF
C32
47uF
C31
330uF
C9
1uF
C6
1uF
V
CL
VcH1 VcH2
HDrv1
Q1
IRF7460
Vcc
C8
1uF
C10,C11,C12
3x 150uF
D2
BAT54A
L3 2.2uH
VccLDO
R3
5m
1.5V
@ 16A
C14
470pF
Ω
3.3V
V
SEN33
C15
1uF
R6 10
Ω
Q2
IRF7457
C13
47uF
Q3 IRLR2703
LDrv1
V
OUT3
R5
4.7
Ω
U1
IRU3046
PGnd
2.5V
@ 2A
R8
200
Fb3
R7 1K
VREF
R10
1K
C30
1uF
C18
47uF
Vp2
Fb1
Fb2
Rt
Sync
R16
29.4K
R21
C24
C19,C20,C21
3x 150uF
R13
15K
Comp1
Comp2
2200pF
R12
1K
C23
1uF
C34
Q4
IRF7460
HDrv2
LDrv2
6.8nF
16.5K
D4
BAT54A
L4 3.3uH
R17
5m
C26
470pF
Ω
PGood
PGood
SS
Q5
IRF7457
R19
4.7Ω
Gnd
C29
0.1uF
Figure 13 - Demo-board application of IRU3046.
Rev. 1.9
09/27/02
www.irf.com
15
IRU3046
DEMO-BOARD APPLICATION
Application Parts List
Ref Desig Description
Value
Qty
2
Part#
IRF7460
Manuf
Web site (www.)
irf.com
Q1,Q4
Q2,Q5
Q3
MOSFET
MOSFET
MOSFET
Controller
Diode
20V, 10mΩ, 12A
20V, 7mΩ, 15A
30V, 0.045Ω, 23A
Synchronous PWM
Fast Switching
Fast Switching
IR
IR
IR
IR
IR
IR
2
1
1
IRF7457
IRLR2703
IRU3046
U1
D1
1
2
BAT54S
BAT54A
D2,D4
Diode
or 1N4148
Any
L1,L2
L3
L4
Inductor
Inductor
Inductor
1µH, 6.8A
2.2µH, 12A
3.3µH, 10A
2
1
1
2
2
2
6
D03316P-102
D05022P-222HC
D05022P-332HC
ECS-T1CD336R
16TPB47M
6TPB330M
6TPC150M
Coilcraft
Coilcraft
Coilcraft
coilcraft.com
C1,C2
C4,C32
C5,C31
Cap, Tantalum 33µF, 16V
Cap, Poscap
Cap, Poscap
Panasonic maco.panasonic.co.jp
47µF, 16V
330µF, 6.3V
Sanyo
Sanyo
Sanyo
sanyo.com/industrial
C10,11,12, Cap, Poscap
19,20,21
150µF, 6.3V, 40mΩ
C3,C29
C9
C24
Cap, Ceramic 0.1µF, Y5V, 25V
Cap, Ceramic 1µF, X7R, 25V
Cap, Ceramic 2200pF, X7R, 50V
Cap, Ceramic 6800pF, X7R, 50V
Cap, Ceramic 470pF, X7R, 50V
Cap, Ceramic 1µF, Y5V, 16V
2
1
1
1
2
6
ECJ-2VF1E104Z
ECJ-3YB1E105K
ECJ-2VB1H222K
ECJ-2VB1H682K
ECJ-2VC1H471J
ECJ-2VF1C105Z
Panasonic maco.panasonic.co.jp
Panasonic
Panasonic
C34
Panasonic
C14,C26
C6,7,8,
15,23,30
C13,C18
R2,4,15,18 Resistor
R16
Panasonic
Panasonic
Cap, Tantalum 47µF, 10V
2
4
1
1
2
1
3
2
1
1
ECS-T1AD476R
Panasonic
2.15Ω
29.4K
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
R21
R5,R19
R8
16.5K
4.7Ω
200, 1%
1K, 1%
5mΩ, 1W, 1%
15K
R7,10,12
R3,R17
R13
ERJ-M1WSF5MOU Panasonic
R6
10Ω
Rev. 1.9
09/27/02
www.irf.com
16
IRU3046
WAVEFORMS
Figure 14 - Gate signals vs. inductor currents.
Ch1: Gate signal for control FET(master) (10V/div).
Ch2: Gate signal for control FET(slave) (20V/div).
Ch3: Inductor current for master channel (5A/div).
Ch4: Inductor current for slave channel (5A/div).
VMASTER=5V, VSLAVE=12V, IOUT=10A
Figure 15 - Inductors current matching.
Ch1: Gate signal for sync FET(master) (10V/div).
Ch2: Gate signal for sync FET(slave) (10V/div).
Ch3: Inductor current for master channel (5A/div).
Ch4: Inductor current for slave channel (5A/div).
VMASTER=5V, VSLAVE=12V, IOUT=10A
Figure 16 - Gate signals.
Ch1: Gate signal for control FET(master) (10V/div).
Ch2: Gate signal for sync FET(master) (10V/div).
Ch3: Gate signal for control FET(slave) (20V/div).
Ch4: Gate signal for sync FET(slave) (10V/div).
Rev. 1.9
09/27/02
www.irf.com
17
IRU3046
WAVEFORMS
VIN=5V
Vss
10A
VOUT
0A
Figure 17 - Start-up @ IOUT = 10A.
Figure 18 - Transient response @ IOUT = 0 to 10A.
2A
0A
Figure 19 - Transient response for
LDO @ IOUT = 0 to 2A.
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.9
09/27/02
www.irf.com
18
IRU3046
(F) TSSOP Package
24-Pin
A
L
Q
R1
B
C
1.0 DIA
R
E
N
M
P
O
PIN NUMBER 1
F
D
DETAIL A
DETAIL A
G
J
H
K
24-PIN
NOM
0.65 BSC
4.40
SYMBOL
MIN
4.30
0.19
MAX
4.50
0.30
DESIG
A
B
C
6.40 BSC
---
D
1.00
E
1.00
F
7.70
---
7.80
7.90
1.10
0.95
0.15
G
H
---
0.85
0.05
0.90
J
---
K
L
128 REF
128 REF
---
M
N
08
88
1.00 REF
0.60
O
P
0.50
0.75
0.20
Q
R
0.09
0.09
---
---
---
---
R1
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 1.9
09/27/02
www.irf.com
19
IRU3046
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
PARTS
PARTS
T & R
DESIG
DESCRIPTION
COUNT
PER TUBE
PER REEL
Orientation
F
TSSOP Plastic
24
74
2500
Fig A
1
1
1
Feed Direction
Figure A
IR WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.9
09/27/02
www.irf.com
20
相关型号：
IRU3047CW
DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND LDO CONTROLLER
INFINEON
IRU3047CWTR
Dual Switching Controller, Voltage-mode, 0.5A, 220kHz Switching Freq-Max, PDSO20, PLASTIC, SOIC-20
INFINEON
IRU3048CFPBF
Dual Switching Controller, Voltage-mode, 0.5A, 220kHz Switching Freq-Max, PDSO16, PLASTIC, TSSOP-16
INFINEON
IRU3048CSPBF
Dual Switching Controller, Voltage-mode, 0.5A, 220kHz Switching Freq-Max, PDSO16, PLASTIC, SOIC-16
INFINEON
©2020 ICPDF网 联系我们和版权申明