IRU3146CFTR [INFINEON]
Switching Controller, Current-mode, 345kHz Switching Freq-Max, PDSO28, TSSOP-28;
| 型号： | IRU3146CFTR |
| 厂家： | 
Infineon |
| 描述： | Switching Controller, Current-mode, 345kHz Switching Freq-Max, PDSO28, TSSOP-28 控制器 |
| 文件： | 总30页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No.PD 94702
IRU3146
DUAL SYNCHRONOUS PWM CONTROLLER WITH
CURRENT SHARING CIRCUITRYANDAUTO-RESTART
DESCRIPTION
FEATURES
The IRU3146 IC combines a Dual synchronous Buck
Dual Synchronous Controller with 180ꢀ out-of-phase
Configurable to 2-Independent Outputs or 2-Phase
Single Output
controller, providing a cost-effective, high performance
and flexible solution. The IRU3146 can configured as 2-
independent or as 2-phase controller. The 2-phase con-
figuration is ideal for high current applications. The
IRU3146 features 180ꢀ out of phase operation which re-
duces the required input/output capacitance and results
to few number of capacitor quantity. Other key features
offered by this device include two independent program-
mable soft starts, programmable switching frequency up
to 500KHz per phase, under voltage lockout function.
The current limit is provided by sensing the lower
MOSFET's on-resistance for optimum cost and perfor-
mance.
Current Sharing Using Inductor's DCR
Current Limit using MOSFET's RDS(ON)
Hiccup/Latched Current Limit
Latched Over-Voltage Protection
Vcc from 4.5V to 16V Input
Programmable Switching Frequency up to 500KHz
Two Independent Soft-Starts/ Shutdowns
0.8V Precision Reference VoltageAvailable
Power Good Output
External Frequency Synchronization
APPLICATIONS
Embedded Computer Systems
Telecom Systems
2-Phase Power Supply
Graphic Card
DDR Memory Applications
Point of Load Power Architectures
D1
C12
12V
C11
C13
C3
C4
C5
C14
V
CL VcH1
VcH2
VOUT3
HDrv1
Q2
Q3
Vcc
L3
R1
OCSet1
LDrv1
Hiccup
Sync
R5
1.8V @ 30A
C16
PGnd1
VP2
C15
R10
R11
VREF
D2
BAT54A
R2
U1
IRU3146
Rt
V
SEN1
R7
R8
R3
C8
VSEN2
Comp1
Fb1
Fb2
R9
L4
C17
R4
C9
Comp2
C18
HDrv2
Q4
R6
OCSet2
PGood
PGood
LDrv2
Q5
SS1 / SD
SS2 / SD
PGnd2
Gnd
C10
Figure 1 - Typical application of IRU3146 in 2-phase configuration with inductor current sensing
PACKAGE ORDER INFORMATION
DEVICE
PACKAGE
IRU3146CF
28-Pin TSSOP (F)
Rev. 1.1
6/25/04
www.irf.com
1
IRU3146
ABSOLUTE MAXIMUM RATINGS
Vcc, VCL Supply Voltage .............................................. -0.5V To 16V
VcH1 and VcH2 Supply Voltage ................................ -0.5V To 25V
PGOOD................. ................................................... -0.5V To 16V
Storage Temperature Range ...................................... -40°C To 125°C
Operating Junction Temperature Range ..................... -40°C To 125°C
Caution: Stresses above those listed in Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
28-PIN TSSOP (F)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGood
Gnd
VCC
VREF
3
VP2
VOUT3
4
Rt
Hiccup
Sync
5
VSEN2
Fb2
6
VSEN1
7
Fb1
Comp2
SS2 / SD
OCSet2
VcH2
8
Comp1
SS1 / SD
OCSet1
VcH1
9
10
11
12
13
14
HDrv2
PGnd2
LDrv2
HDrv1
PGnd1
LDrv1
VCL
θJA = 84°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=12V, VcH1=VcH2=VCL=12V and TA=0 to 70°C.
Typical values refer to TA=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures
equal to the ambient temperature.
PARAMETER
SYM
TEST CONDITION
MIN
TYP MAX UNITS
Reference Voltage Section
Reference Voltage
Voltage Line Regulation
UVLO Section
VREF
LREG
0.789 0.805 0.821
V
%/V
5<Vcc<12
0.02
0.04
4.5
3.8
3.8
UVLO Threshold - Vcc
UVLO Hysteresis - Vcc
UVLO Threshold - VcH1
UVLO Hysteresis - VcH1
UVLO Threshold - VcH2
UVLO Hysteresis - VcH2
Supply Current Section
Vcc Dynamic Supply Current
VcH1 & VcH2 Dynamic Current
VCL Dynamic Supply Current
Vcc Static Supply Current
VcH1/VcH2 Static Current
VCL Static Supply Current
UVLOVCC Supply Ramping Up
Ramp Up and Ramp Down
UVLOVCH1 Supply Ramping Up
Ramp Up and Ramp Down
UVLOVCH2 Supply Ramping Up
Ramp Up and Ramp Down
3.9
3.2
3.2
4.2
0.25
3.5
0.1
3.5
0.1
V
V
V
V
V
V
Dyn ICC
Dyn ICH
Dyn ICL
ICCQ
Freq=300KHz, CL=1500pF
Freq=300KHz, CL=1500pF
Freq=300KHz, CL=1500pF
SS=0V
SS=0V
SS=0V
10
15
15
10
6
15
25
25
15
10
10
mA
mA
mA
mA
mA
mA
ICHQ
ICLQ
6
Rev. 1.1
6/25/04
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2
IRU3146
PARAMETER
SYM
TEST CONDITION
SS=0V
MIN
TYP MAX UNITS
Soft-Start Section
Charge Current
SSIB
20
25
32
µA
Power Good Section
VSENS1 Lower Trip Point
VSENS2 Lower Trip Point
PGood Output Low Voltage
Error Amp Section
PGFB1L
PGFB2H
VSENS1 Ramping Down
VSENS2 Ramping Down
ISINK=2mA
0.8VREF 0.9VREF 0.95VREF
0.8VREF 0.9VREF 0.95VREF
V
V
V
0.1
0.5
Fb Voltage Input Bias Current
Transconductance 1
Transconductance 2
Error Amp Source/Sink Current
Input Offset Voltage for PWM1/2
VP2 Voltage Range
IFB1
gm1
gm2
SS=3V
-0.1
-0.5
2300 µmho
2300 µmho
140
+5
1.5
µA
1400
1400
60
-5
0.8
100
0
µA
mV
V
VOS(ERR)2
VP2
Fb to VREF
Note1
Oscillator Section
Frequency
Ramp Amplitude
Synch Frequency Range
Synch Pulse Duration
Synch High Level Threshold
Synch Low Level Threshold
VOUT3 Internal Regulator
Output Voltage
KHz
Freq
VRAMP
Rt(SET) to 30K
Note1
20% above free running freq
Note1
Note1
255
345
800
1.25
300
V
KHz
ns
V
200
2
0.8
6.7
V
5.9
50
6.2
V
mA
Output Current
Protection Section
OVP Trip Threshold
OVP Fault Prop Delay
Current Limit Threshold
Current Source
Hiccup Duty Cycle
Hiccup High Level Threshold
Hiccup Low Level Threshold
Output Drivers Section
Rise Time
OVP
1.1VREF 1.15VREF 1.2VREF
V
µs
µA
Output forced to 1.125VREF,Note1
Hiccup pin pulled high, Note1
Note1
5
OCSet
16
2
20
5
24
%
V
V
0.8
Tr
Tf
TDB
DMAX
DMIN
CL=1500pF, Figure 2
CL=1500pF, Figure 2
Figure 2
Fb=0.6V, FSW=300KHz
Fb=1V
18
25
50
85
0
50
50
100
ns
ns
ns
%
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
%
Min Pulse Width
Thermal Shutdown Trip Point
Thermal Shutdown Hysteresis
Puls(min) FSW=300KHz, Note1
Note 1
ns
ꢀC
ꢀC
150
140
20
Note 1: Guaranteed by design but not tested for production.
Rev. 1.1
6/25/04
www.irf.com
3
IRU3146
DEADBAND TIME
Tf
Tr
90%
High Side
Driver HD
2V
10%
Tf
Tr
90%
Low Side
Driver LD
2V
10%
Deadband
H_to_L
Deadband
L_to_H
Figure 2 - Deadband time definition.
TDB(TYP)=(Deadband H_toL+Deadband L_to -H)/2
PIN DESCRIPTIONS
PIN# PIN SYMBOL
PIN DESCRIPTION
1
2
PGood
Vcc
Power Good pin. Low when any of the outputs fall 10% below the set voltages.
Supply voltage for the internal blocks of the IC.
3
VOUT3
Output of the internal LDO.
4
5,23
6,22
Rt
Switching frequency setting resistor. (see Figure 10 for selecting resistor values).
Sense pins for OVP and PGood. For 2-Phase operation tie these pins together.
Inverting inputs to the error amplifiers. In current sharing mode, Fb1 is connected to a
resistor divider to set the output voltage and Fb2 is connected to programming resistor to
achieve current sharing. In independent 2-channel mode, these pins work as feedback
inputs for each channel.
VSEN2, VSEN1
Fb2,Fb1
7,21 Comp2, Comp1 Compensation pins for the error amplifiers.
These pins provide soft-start for the switching regulator.An internal current source charges
8
20
SS2 / SD
SS1 / SD
external capacitors that are connected from these pins to ground which ramp up the
output of the switching regulators, preventing them from overshooting as well as limiting
the input current. The converter can be shutdown by pulling these pins below 0.3V.
9,19 OCSet2,OCSet1 Current limit resistor (RLIM) connection pins for output 1 and 2. The other ends of RLIMs are
connected to the corresponding switching nodes.
10,18 VcH2, VcH1 Supply voltage for the high side output drivers. These are connected to voltages that must
be typically 6V higher than their bus voltages. A 1µF high frequency capacitor must be
connected from these pins to GND to provide peak drive current capability.
11,17 HDrv2, HDrv1 Output drivers for the high side power MOSFETs. 1)
12,16 PGnd2, PGnd1 These pins serve as the separate grounds for MOSFET drivers and should be connected
to the system’s ground plane.
13,15 LDrv2, LDrv1 Output drivers for the synchronous power MOSFETs.
14
24
25
VCL
Sync
Hiccup
Supply voltage for the low side output drivers. This pin should be high for normal operation
The internal oscillator may be synchronized to an external clock via this pin.
When pulled High, it puts the device current limit into a hiccup mode. When pulled Low,
the output latches off, after an overcurrent event.
Rev. 1.1
6/25/04
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4
IRU3146
PIN DESCRIPTIONS
PIN# PIN SYMBOL
PIN DESCRIPTION
26
VP2
Non-inverting input to the second error amplifier. In the current sharing mode, it is con-
nected to the programming resistor. In independent 2-channel mode it is connected to
VREF pin when Fb2 is connected to the resistor divider to set the output voltage.
Reference Voltage. The drive capability of this pin is about 2uA.
Analog ground for internal reference and control circuitry. Connect to PGnd plane with a
short trace.
27
28
VREF
Gnd
1) These pins should not go negative (-0.5V), this may cause instability for the gate drive circuits. To prevent this,
a low forward voltage drop diode is required between these pins and ground as shown in Figure 1.
BLOCK DIAGRAM
2
Vcc
25uA 25uA
Mode
V
P2
3V
POR
Bias
Generator
Mode
Control
64uA
Max
18 VcH1
0.8V
0.8V
Mode
8
SS2 / SD
SS1 / SD
64uA
4.2V / 4.0V
POR
UVLO
17 HDrv1
3.5V / 3.3V
3.5V / 3.3V
20
VcH1
VcH2
0.3V
POR
Thermal
14
VCL
Shutdown
PWM Comp1
SS1
15
Error Amp1
LDrv1
R
SS1
0.8V
16 PGnd1
3uA
Q
22
21
4
Fb1
Comp1
Rt
19
OCSet1
Set1
Ramp1
Ramp2
S
20uA
Reset Dom
Two Phase
Oscillator
Set2
Reset Dom
10
11
VcH2
24
27
Sync
S
HDrv2
SS1
SS2
PWM Comp2
Hiccup
Control
0.8V
VREF
Q
R
25
Hiccup
Error Amp2
Mode
26
P2
V
0.3V
SS2
13
LDrv2
6
7
Fb2
12 PGnd2
SS2
Comp2
9
OCSet2
OVP
23
5
V
SEN1
3uA
20uA
PGood / OVP
Regulator
HDrv OFF / LDrv ON
VSEN2
1
PGood
28
Gnd
VOUT3
3
Figure 3 - Block diagram of IRU3146.
Rev. 1.1
6/25/04
www.irf.com
5
IRU3146
FUNCTIONAL DESCRIPTION
Introduction
The IRU3146 is versatile device for high performance Buck
information for current sharing. The voltage drops across
converters. It is included of two synchronous Buck con- the current sense resistors (or DCR of inductors) are
trollers which can be operated both in two independent measured and their difference is amplified by the slave
mode or in 2-phase mode.
error amplifier and compared with the ramp signal to
The timing of the IC is provided through an internal oscil- generate the PWM pulses to match the output current.
lator circuit. These are two out-of-phase oscillators that In this mode the SS2 pin should be floating.
can be programmed up to 400KHz per phase.
IRU3146
Supply Voltage
Comp
0.8V
PWM Comp1
PWM Comp2
Master E/A
Vcc is the supply voltage for internal controller. The op-
erating range is from 4.5V to 16V. It also is fed to the
internal LDO. When Vcc is below under-voltage thresh-
old, all MOSFET drivers will be turned off.
L1
VOUT
RL1
Fb1
R1
C1
VP2
Internal Regulator
The regulator powers directly from VCC and generates a
regulated voltage (Typ. 6.2V@50mA). The output is pro-
tected for short circuit. This voltage can be used for charge
pump circuitry as describe in Figure12.
FB2
L2
R
L2
Slave E/A
R2
C2
Input Supplies UnderVoltage LockOut
Figure 4 - Loss-less inductive current sensing
and current sharing.
The IRU3146 UVLO block monitors three input voltages
(VCC, VCH1 and VCH2) to ensure reliable start up. The
MOSFET driver output turn off when any of the supply
voltages drops below set thresholds. Normal operation
resumes once the supply voltages rise above the set
values.
In the diagram, L1 and L2 are the output inductors. RL1
and RL2 are inherent inductor resistances. The resistor
R1 and capacitor C1 are used to sense the average in-
ductor current. The voltage across the capacitors C1
and C2 represent the average current flowing into resis-
tance RL1 and RL2. The time constant of the RC network
should be equal or at most three times larger than the
Independent Mode
In this mode the IRU3146 provides control to two inde-
pendent output power supplies with either common or
different input voltages. The output voltage of each indi-
vidual channel is set and controlled by the output of the
error amplifier, which is the amplified error signal from
the sensed output voltage and the reference voltage. The
error amplifier output voltage is compared to the ramp
signal thus generating fixed frequency pulses of variable
duty-cycle, which are applied to the FET drivers, Fig-
ure18 shows a typical schematic for such application.
time constant L /R .
L1
1
L1
RL1
R1×C1=(1~3)×
---(1)
2-Phase Mode
This feature allows to connect both outputs together to
increase current handling capability of the converter to
support a common load. The current sharing can be done
either using external resistors or sensing the DCR of
inductors (see Figure 4). In this mode, one control loop
acts as a master and sets the output voltage as a regu-
lar Voltage Mode Buck controller and the other control
loop acts as a slave and monitors the current
Figure 5 - 30A Current Sharing using Inductor sensing
(5A/Div)
Rev. 1.1
6/25/04
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6
IRU3146
25uA 25uA
Dual Soft-Start
64uA
Max
The IRU3146 has programmable soft-start to control the
output voltage rise and limit the inrush current during
start-up. It provides a separate Soft-Start function for each
outputs. This will enable to sequence the outputs by
controlling the rise time of each output through selection
of different value soft-start capacitors. The soft-start pins
will be connected together for applications where, both
outputs are required to ramp-up at the same time.
8
SS2 / SD
SS1 / SD
64uA
20
POR
Error Amp1
0.8V
To ensure correct start-up, the soft-start sequence ini-
tiates when the VCC, VCH1 and VCH2 rise above their
threshold (4.2V and 3.5V respectively) and generate the
Power On Reset (POR) signal. Soft-start function oper-
ates by sourcing an internal current to charge an exter-
nal capacitor to about 3V. Initially, the soft-start function
clamps the E/A’s output of the PWM converter. During
power up, the converter output starts at zero and thus
the voltage at Fb is about 0V. A current (64µA) injects
into the Fb pin and generates a voltage about 1.6V
(64µA×25K) across the negative input of E/A and (see
Figure6).
22
21
Fb1
Comp1
Error Amp2
26
P2
V
6
7
Fb2
Comp2
The magnitude of this current is inversely proportional to
the voltage at soft-start pin. The 25µA current source
starts to charge up the external capacitor. In the mean
time, the soft-start voltage ramps up, the current flowing
into Fb pin starts to decrease linearly and so does the
voltage at negative input of E/A.
Figure 6 -Soft-start circuit for IRU3146
Output of POR
3V
≅2V
When the soft-start capacitor is around 1V, the current
flowing into the Fb pin is approximately 32µA. The volt-
age at the positive input of the E/A is approximately:
≅1V
Soft-Start
Voltage
0V
64uA
Current flowing
into Fb pin
32µA×25K = 0.8V
0uA
The E/A will start to operate and the output voltage starts
to increase. As the soft-start capacitor voltage contin-
ues to go up, the current flowing into the Fb pin will keep
decreasing. Because the voltage at pin of E/A is regu-
lated to reference voltage 0.8V, the voltage at the Fb is:
≅1.6V
Voltage at negative input
of Error Amp
0.8V
0.8V
VFB = 0.8-(25K×Injected Current)
0V
Voltage at Fb pin
The feedback voltage increases linearly as the injecting
current goes down. The injecting current drops to zero
when soft-start voltage is around 2V and the output volt-
age goes into steady state. Figure 7 shows the theoreti-
cal operational waveforms during soft-start.
Figure 7 - Theoretical operational waveforms
during soft-start.
The output start-up time is the time period when soft-
start capacitor voltage increases from 1V to 2V. The
start-up time will be dependent on the size of the exter-
nal soft-start capacitor. The start-up time can be esti-
mated by:
25µA×TSTART/CSS = 2V-1V
Rev. 1.1
6/25/04
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7
IRU3146
For a given start up time, the soft-start capacitor can be The internal current source develops a voltage across
calculated by:
RSET. When the low side switch is turned on, the induc-
tor current flows through the Q2 and results a voltage
which is given by:
CSS ≅ 25µA×TSTART/1V
The soft-start is part of Over Current Protection scheme,
during the overload or short circuit condition the external
soft start capacitors will be charged and discharged in
certain slope rate to achieve the hiccup mode function.
VOCSET = IOCSET×RSET-RDS(ON)×iL
---(2)
25uA
IOCSET
Hiccup
IRU3146
Q1
Q2
VOUT
RSET
L1
OCSet
20
SS1 / SD
Hiccup
Control
3uA
Figure 9 - Diagram of the over current sensing.
Figure 8 - 3uA current source for discharging soft
start-capacitor during Hiccup mode
The critical inductor current can be calculated by set-
ting:
Out-of-Phase Operation
VOCSET = IOCSET×RSET - RDS(ON)×IL = 0
The IRU3146 drives its two output stages 180ꢀ out-of-
phase. In 2-phase configuration, the two inductor ripple
currents cancel each other and result in a reduction of
the output current ripple and yield a smaller output ca-
pacitor for the same ripple voltage requirement.
RSET×IOCSET
ISET = IL(CRITICAL)
=
---(3)
RDS(ON)
In single input voltage applications, the input ripple cur-
rent reduces. This result in much smaller input capacitor's
RMS current and reduces the input capacitor quantity.
The value of RSET should be checked in an actual
circuit to ensure that the Over Current Protection
circuit activates as expected. The IRU3146 current
limit is designed primarily as disaster preventing, "no
blow up" circuit, and is not useful as a precision
current regulator.
Over-Current Protection
The IRU3146 can provide two different schemes for Over-
Current Protection (OCP). When the pin Hiccup is pulled
high, the OCP will operate in hiccup mode. In this mode,
during overload or short circuit, the outputs enter hiccup
mode and stay in that mode until the overload or short
circuit is removed. The converter will automatically re-
cover.
When the Hiccup pin is pulled low, the OCP scheme
will be changed to the latch up type, in this mode the
converter will be turned off during Overcurrent or short
circuit. The power needs to be recycled for normal
operation.
Each phase has its own independent OCP circuitry.
The OCP is performed by sensing current through the
RDS(ON) of low side MOSFET. As shown in Figure 9, an
external resistor (RSET) is connected between OCSet pin
and the drain of low side MOSFET (Q2) which sets the
current limit set point.
In two independent mode, the output of each channel
is protected independently which means if one output
is under overload or short circuit condition, the other
output will remain functional. The OCP set limit can be
programmed to different levels by using the external
resistors. This is valid for both hiccup mode and latch
up mode.
In 2-phase configuration, the OCP's output depends on
any one channel, which means as soon as one
channel goes to overload or short circuit condition the
output will enter either hiccup or latch-up, dependes on
status of Hiccup pin.
If using one soft start capacitor in dual configuration for a
precise power up the OCP needs to be set to latch mode.
Rev. 1.1
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IRU3146
Operation Frequency Selection
Frequency Synchronization
The optimum operating frequency range for IRU3146 is
300KHz per phase, theoretically the IRU3146 can be
operated at higher switching frequency (e.g. 500KHz).
However the power dissipation for IC, which is function
of applied voltage, gate drivers load and switching fre-
quency, will result in higher junction temperature of de-
vice. It may exceed absolute maximum rating of junc-
tion temperature, figure 18 (page 16) shows case tem-
perature versus switching frequency with different ca-
pacitive loads.
The IRU3146 is capable of accepting an external digital
synchronization signal. Synchronization will be enabled
by the rising edge at an external clock. Per-channel switch-
ing frequency is set by external resistor (Rt). The free
running oscillator frequency is twice the per-channel fre-
quency. During synchronization, Rt is selected such that
the free running frequency is 20% below the sync fre-
quency. Synchronization capability is provided for both 2-
output and 2-phase configurations. When unused, the
Sync pin will remain floating and is noise immune.
This should be considered when using IRU3146 for such
application. The below equation shows the relationship
between IC's maximum power dissipation and Junction
temperature:
Thermal Shutdown
Temperature sensing is provided inside IRU3146. The trip
threshold is typically set to 140ꢀC. When trip threshold is
exceeded, thermal shutdown turns off both FETs. Ther-
mal shutdown is not latched and automatic restart is ini-
tiated when the sensed temperature drops to normal
range. There is a 20ꢀC hysteresis in the shutdown thresh-
old.
ΤJ-ΤA
Pd =
θJA
Where:
Tj: Maximum Operating Junction Temperature (125°C)
TA:Ambient Temperature (70°C)
θJA = Thermal Impedance of package (84°C/W)
For Tj=125°C TA=70°C and θJA=84°C/W
This will result to power dissipation of 650mW, this in-
cludes biasing current for all four external MOSFETs
and IC's biasing current.
The switching frequency is determined by an external
resistor (Rt). The switching frequency is approximately
inversely proportioned to resistance (see Fig 10).
Power Good
The IRU3146 provides a power good signal. The power
good signal should be available after both outputs have
reached regulation. This pin needs to be externally pulled
high. High state indicates that outputs are in regulation.
Power good will be low if either one of the output voltages
is 10% below the set value. There is only one power good
for both outputs.
Per channel Switching Frequency vs. RT
700
650
600
550
500
450
400
350
300
250
200
Over-Voltage Protection OVP
Over-voltage is sensed through separate VOUT sense pins
Vsen1 and Vsen2. A separate OVP circuit is provided for
each output. Upon over-voltage condition of either one of
the outputs, the OVP forces a latched shutdown on both
outputs. In this mode, the upper FET drivers turn-off and
the lower FET drivers turn-on, thus crowbaring the out-
puts. Reset is performed by recycling either Vcc.
Error Amplifier
The IRU3146 is a voltage mode controller. The error am-
plifiers are of transconductance type. In independent mode,
each amplifier closes the loop around its own output volt-
age. In current sharing mode, amplifier 1 becomes the
master which regulates the common output voltage. Am-
plifier 2 performs the current sharing function. Both am-
plifiers are capable of operating with Type III compensa-
tion control scheme.
10
20
30
40
50
RT(Kohm)
Figure 10- Switching Frequency versus External Resistor.
Shutdown
The outputs can be shutdown independently by pulling
the respective soft-start pins below 0.3V. This can be
easily done by using an external small signal transis-
tor. During shutdown both MOSFETs will be turned off.
During this mode the LDO will stay on. Cycling soft-
start pins will clear all fault latches and normal opera-
tion will resume.
Low Temperature Start-Up
The controller is capable of starting at -40ꢀC ambient
temperature.
Rev. 1.1
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9
IRU3146
APPLICATION INFORMATION
Soft-Start Programming
The soft-start timing can be programmed by selecting
the soft-start capacitance value. The start-up time of
the converter can be calculated by using:
Design Example:
The following example is a typical application for IRU3146,
the schematic is Figure18 on page17.
VIN = 12V
VOUT(2.5V) = 2.5V @ 10A
VOUT(1.8V) = 1.8V @ 10A
∆VOUT = Output voltage ripple ≅ 3% of VOUT
FS = 300KHz
Css ≅ 25×tSTART (µF)
---(5)
Where tSTART is the desired start-up time (ms)
For a start-up time of 4ms for both output, the soft-start
capacitor will be 0.1µF. Connect ceramic capacitors at
0.1µF from SS1 pin and SS2 pin to GND.
Output Voltage Programming
Output voltage is programmed by reference voltage and
external voltage divider. The Fb1 pin is the inverting input
of the error amplifier, which is referenced to the voltage
on non-inverting pin of error amplifier. For this applica-
tion, this pin (VP) is connected to reference voltage (VREF).
The output voltage is defined by using the following equa-
tion:
Supply VCH1 and VCH2
To drive the high side switch, it is necessary to supply
a gate voltage at least 4V grater than the bus voltage.
This is achieved by using a charge pump configuration
as shown in Figure 12. This method is simple and inex-
pensive. The operation of the circuit is as follows: when
the lower MOSFET is turned on, the capacitor (C1)
charges up to VOUT3, through the diode (D1). The bus
voltage will be added to this voltage when upper
MOSFET turns on in next cycle, and providing supply
voltage (VCH1) through diode (D2). Vc is approximately:
R6
R5
VOUT = VP × 1 +
---(4)
( )
VP2 = VREF = 0.8V
When an external resistor divider is connected to the
output as shown in Figure 11.
VCH1 ≅ VOUT3 + VBUS - (VD1 + VD2)
VOUT
Capacitors in the range of 0.1µF and 1µF are generally
adequate for most applications. The diode must be a
fast recovery device to minimize the amount of charge
fed back from the charge pump capacitor into VOUT3.
The diodes need to be able to block the full power rail
voltage, which is seen when the high side MOSFET is
switched on. For low voltage application, schottky di-
odes can be used to minimize forward drop across the
diodes at start up.
IRU3146
R
6
V
REF
Fb
R5
V
P
Figure 11 - Typical application of the IRU3146 for
programming the output voltage.
D1
D2
Equation (4) can be rewritten as:
C3
VOUT
R6 = R5 ×
- 1
V
OUT3
( VP )
V
BUS
VCH1
Will result to:
VOUT(2.5V) = 2.5V
VREF = 0.8V
Regulator
C2
C1
Q1
VOUT(1.8V) = 1.8V
VREF = 0.8
R7= 1.24K, R8 = 1K
L2
R9= 2.14K, R5= 1K
HDrv
Q2
IRU3146
If the high value feedback resistors are used, the input
bias current of the Fb pin could cause a slight increase
in output voltage. The output voltage can be set more
accurately by using low value, precision resistors.
Figure 12 - Charge pump circuit.
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IRU3146
For ∆i(1.8V) = 30%(IO(1.8V) ), then the output inductor will
be:
Input Capacitor Selection
The 1800 out of phase will reduce the RMS value of the
ripple current seen by input capacitors. This reduces
numbers of input capacitors. The input capacitors must
be selected that can handle both the maximum ripple
RMS at highest ambient temperature as well as the
maximum input voltage. The RMS value of current ripple
for duty cycles under 50% is expressed by:
L3 = 1.7µH
Panasonic provides a range of inductors in different val-
ues and low profile for large currents.
Choose ETQP6F1R8BFA (1.71µH, 14A, 3.3mΩ) both
for L3 and L4.
For 2-phase application, equation (7) can be used for
calculating the inductors value. In such case the induc-
tor ripple current is usually chosen to be between 10-
40% of maximum phase current.
IRMS= (I12D1(1-D1)+I22D2(1-D2)-2I1I2D1D2) --- (6)
Where:
IRMS is the RMS value of the input capacitor current
D1 and D2 are the duty cycle for each output
I1 and I2 are the current for each output
For this application the IRMS =4.8A
Output Capacitor Selection
The criteria to select the output capacitor is normally
based on the value of the Effective Series Resistance
(ESR). In general, the output capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy sta-
bility requirements. The ESR of the output capacitor is
calculated by the following relationship:
(ESL, Equivalent Series Inductance is neglected)
For higher efficiency, low ESR capacitors is recom-
mended.
Choose two Poscap from Sanyo 16TPB47M (16V, 47µF,
70mΩ ) with a maximum allowable ripple current of 1.4A
for inputs of each channel.
∆VO
∆IO
Inductor Selection
ESR ≤
---(8)
The inductor is selected based on operating frequency,
transient performance and allowable output voltage ripple.
Low inductor value results to faster response to step
load (high ∆i/∆t) and smaller size but will cause larger
output ripple due to increase of inductor ripple current.
As a rule of thumb, select an inductor that produces a
ripple current of 10-40% of full load DC.
Where:
∆VO = Output Voltage Ripple
∆i = Inductor Ripple Current
∆VO = 3% of VO will result to ESR(2.5V) =19.7mΩ and
ESR(1.8V) =16mΩ
The Sanyo TPC series, Poscap capacitor is a good choice.
The 6TPC330M, 330µF, 6.3V has an ESR 40mΩ. Se-
lecting two of these capacitors in parallel for 2.5V out-
put, results to an ESR of ≅ 20mΩ which achieves our
low ESR goal. And selecting four of these capacitors in
parallel for 1.8V output, results to an ESR of ≅ 10mΩ
which achieves our low ESR goal.
For the buck converter, the inductor value for desired
operating ripple current can be determined using the fol-
lowing relation:
∆i
∆t
1
fS
VOUT
VIN
VIN - VOUT = L×
; ∆t = D×
; D =
The capacitors value must be high enough to absorb the
inductor's ripple current.
VOUT
L = (VIN - VOUT)×
---(7)
VIN×∆i×fS
Power MOSFET Selection
Where:
The IRU3146 uses four N-Channel MOSFETs. The se-
lections criteria to meet power transfer requirements is
based on maximum drain-source voltage (VDSS), gate-
source drive voltage (VGS), maximum output current, On-
resistance RDS(ON) and thermal management.
VIN = Maximum Input Voltage
VOUT = Output Voltage
∆i = Inductor Ripple Current
fS = Switching Frequency
∆t = Turn On Time
D = Duty Cycle
The both control and synchronous MOSFETs must have
a maximum operating voltage (VDSS) that exceeds the
maximum input voltage (VIN).
For ∆i(2.5V) = 38%(IO(2.5V) ), then the output inductor will
be:
L4 = 1.71µH
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IRU3146
The gate drive requirement is almost the same for both
MOSFETs. Logic-level transistor can be used and cau-
tion should be taken with devices at very low VGS to pre-
vent undesired turn-on of the complementary MOSFET,
which results a in shoot-through.
VDS(OFF)
tr + tf
T
PSW =
Where:
×
× ILOAD
---(9)
2
VDS(OFF) = Drain to Source Voltage at off time
tr = Rise Time
tf = Fall Time
T = Switching Period
ILOAD = Load Current
The total power dissipation for MOSFETs includes con-
duction and switching losses. For the Buck converter,
the average inductor current is equal to the DC
load current. The conduction loss is defined as:
VDS
90%
2
PCOND(Upper Switch) = ILOAD×RDS(ON)×D×ϑ
2
PCOND(Lower Switch) = ILOAD×RDS(ON)×(1 - D)×ϑ
ϑ = RDS(ON) Temperature Dependency
10%
V
GS
The RDS(ON) temperature dependency should be consid-
ered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
td(OFF)
td(ON)
tr
tf
Figure 13 - Switching time waveforms.
From IRF7457 data sheet we obtain:
IRF7457
Choose IRF7457 both for control and synchronous
MOSFET. This device provide low on-resistance in a com-
pact SOIC 8-Pin package.
tr = 16ns
tf = 7ns
These values are taken under a certain condition test.
For more details please refer to the IRF7457 data sheet.
The MOSFET have the following data:
IRF7457
VDSS = 20V
ID = 15A
RDS(ON) = 7mΩ
By using equation (9), we can calculate the total switch-
ing losses.
PSW(TOTAL,2.5V) = 0.414W
PSW(TOTAL,1.8V) = 0.414W
The total conduction losses for each output will be:
PCON(TOTAL, 2.5V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 2.5V) = 1.0W
Programming the Over-Current Limit
The over-current threshold can be set by connecting a
resistor (RSET) from drain of low side MOSFET to the
OCSet pin. The resistor can be calculated by using equa-
tion (3).
PCON(TOTAL, 1.8V) = PCON(UPPER) + PCON(LOWER)
PCON(TOTAL, 1.8V) = 1.0W
The RDS(ON) has a positive temperature coefficient and it
should be considered for the worse case operation.
The switching loss is more difficult to calculate, even
though the switching transition is well understood. The
reason is the effect of the parasitic components and
switching times during the switching procedures such RDS(ON) = 7mΩ×1.5 = 10.5mΩ
as turn-on / turnoff delays and rise and fall times. The
ISET ≅ IO(LIM) = 10A×1.5 = 15A
control MOSFET contributes to the majority of the switch- (50% over nominal output current)
ing losses in a synchronous Buck converter. The syn-
chronous MOSFET turns on under zero voltage condi-
tions, therefore, the switching losses for synchronous
MOSFET can be neglected. With a linear approxima-
tion, the total switching loss can be expressed as:
This results to:
RSET = R1=R6=7.8KΩ
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IRU3146
Feedback Compensation
The ESR zero of the output capacitor is expressed as
follows:
The IRU3146 is a voltage mode controller; the control
loop is a single voltage feedback path including error
amplifier and error comparator. To achieve fast transient
response and accurate output regulation, a compensa-
tion circuit is necessary. The goal of the compensation
network is to provide a closed loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin (greater than 45ꢀ).
1
FESR =
---(10A)
2π×ESR×Co
VOUT
R6
Fb
Comp
The output LC filter introduces a double pole, –40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180ꢀ (see Figure 14). The Reso-
nant frequency of the LC filter is expressed as follows:
Ve
E/A
R
5
C9
Vp=VREF
R4
1
Gain(dB)
FLC =
---(10)
2π× LO×CO
H(s) dB
Where: Lo is the output inductor
For 2-phase application, the effective output
inductance should be used
Frequency
FZ
Co is the total output capacitor
Figure 15 - Compensation network without local
feedback and its asymptotic gain plot.
Figure 14 shows gain and phase of the LC filter. Since
we already have 180ꢀ phase shift just from the output
The transfer function (Ve / VOUT) is given by:
Gain
0dB
Phase
0ꢀ
R5
1 + sR4C9
sC9
H(s) = gm×
×
---(11)
-40dB/decade
( )
R6 + R5
The (s) indicates that the transfer function varies as a
function of frequency. This configuration introduces a gain
and zero, expressed by:
-180
ꢀ
Frequency
FLC
F
LC Frequency
Figure14 - gain and phase of LC filter
R5
R6+R5
|H(s=j×2π×FO)| = gm×
×R4
---(12)
The IRU3146’s error amplifier is a differential-input
transconductance amplifier. The output is available for
DC gain control or AC phase compensation.
The E/A can be compensated with or without the use of
local feedback. When operated without local feedback,
the transconductance properties of the E/A become evi-
dent and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC circuit
from Comp pin to ground as shown in Figure 15.
1
FZ =
---(13)
2π×R4×C9
|H(s)| is the gain at zero cross frequency.
First select the desired zero-crossover frequency (FO1):
FO1 > FESR and FO1 ≤ (1/5 ~ 1/10)×fS
Note that this method requires the output capacitor to
have enough ESR to satisfy stability requirements. In
general, the output capacitor’s ESR generates a zero
typically at 5KHz to 50KHz which is essential for an
acceptable phase margin.
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IRU3146
For a general solution for unconditional stability for ce-
ramic output capacitor with very low ESR or any type of
output capacitors, in a wide range of ESR values we
should implement local feedback with a compensation
network. The typically used compensation network for a
voltage-mode controller is shown in Figure 16.
1
gm
VOSC
VIN
FO1×FESR
R5 + R6
R5
R4 =
×
×
×
---(14)
2
FLC
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
FO1 = Crossover Frequency
VOUT
ZIN
C12
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R5 and R6 = Resistor Dividers for Output Voltage
Programming
C10
R7
C11
R8
R6
Zf
gm = Error Amplifier Transconductance
For V2.5V:
VIN = 12V
VOSC = 1.25V
FO1 = 30KHz
FESR = 12KHz
Fb
Ve
E/A
FLC = 4.75KHz
R5 = 1K
R6 = 2.14K
Comp
R5
Vp=VREF
Gain(dB)
gm = 2000µmho
H(s) dB
This results to R4=2.61K
Choose R4=2.61K
Frequency
F
Z
1
F
Z
2
F
P
2
FP3
To cancel one of the LC filter poles, place the zero be-
fore the LC filter resonant frequency pole:
FZ ≅ 75%FLC
Figure 16- Compensation network with local
feedback and its asymptotic gain plot.
1
FZ ≅ 0.75×
---(15)
2π LO × CO
In such configuration, the transfer function is given by:
For:
Ve
VOUT
1 - gmZf
1 + gmZIN
Lo = 1.71µH
Co = 660µF
FZ = 3.56KHz
R4 = 2.61K
=
The error amplifier gain is independent of the transcon-
ductance under the following condition:
Using equations (13) and (15) to calculate C9, we get:
gmZf >> 1 and gmZIN >>1
---(16)
C9 ≅ 17.18nF; Choose C9 =18nF
By replacing ZIN and Zf according to Figure 16, the trans-
former function can be expressed as:
Same calcuation For V1.8V will result to: R3 = 2.8K and
C8 = 22nF
(1+sR7C11)×[1+sC10(R6+R8)]
1
×
H(s) =
One more capacitor is sometimes added in parallel with
C9 and R4. This introduces one more pole which is mainly
used to suppress the switching noise. The additional
sR6(C12+C11)
C12C11
1+sR7
×(1+sR8C10)
[ (C12+C11)]
pole is given by:
1
As known, transconductance amplifier has high imped-
ance (current source) output, therefore, consider should
be taken when loading the E/A output. It may exceed its
source/sink output current capability, so that the ampli-
fier will not be able to swing its output voltage over the
necessary range.
FP =
C9×CPOLE
2π×R4×
C9 + CPOLE
The pole sets to one half of switching frequency which
results in the capacitor CPOLE:
1
1
CPOLE =
≅
π×R4×fS
1
C9
π×R4×fS -
The compensation network has three poles and two ze-
ros and they are expressed as follows:
fS
2
for FP <<
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14
IRU3146
FP1 = 0
FP2 =
Compensation for Slave Error Amplfier for 2-Phase
Configuration
1
The slave error amplifier is a differential-input transcon-
ductance amplifier, in 2-phase configuration the main goal
for the slave feed back loop is to control the inductor
current to match the masters inductor current as well
provides highest bandwidth and adequate phase margin
for overall stability. The following analysis is valid for both
using external current sense resistor and using DCR of
inductors.
2π×R8×C10
1
1
FP3 =
≅
2π×R7×C12
C12×C11
(C12+C11 )
2π×R7×
1
FZ1 =
2π×R7×C11
1
1
FZ2 =
≅
2π×C10×(R6 + R8)
The transfer function of power stage is expressed by:
2π×C10×R6
IL2(s)
Ve(s)
VIN - VOUT
sL2 × VOSC
Cross Over Frequency:
G(s) =
=
---(18)
VIN
FO = R7×C10×
VOSC
1
---(17)
×
2π×Lo×Co
Where:
VIN = Input Voltage
VOUT = Output Voltage
L2 = Output Inductor
VOSC = Oscillator Peak Voltage
Where:
VIN = Maximum Input Voltage
VOSC = Oscillator Ramp Voltage
Lo = Output Inductor
Co = Total Output Capacitors
As shown the transfer function is a function of inductor
current.
The stability requirement will be satisfied by placing the
poles and zeros of the compensation network according
to following design rules. The consideration has been
taken to satisfy condition (16) regarding transconduc-
tance error amplifier.
The transfer function for the compensation network is
given by equation (19), when using a series RC circuit
as shown in Figure 17:
RS1
Ve(s)
RS2 × IL2(s)
1 + sC2R2
---(19)
g
=
m×
×
D(s) =
These design rules will give a crossover frequency ap-
proximately one-tenth of the switching frequency. The
higher the band width, the potentially faster the load tran-
sient response. The DC gain will be large enough to pro-
vide high DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45ꢀ for overall
stability.
( )
( )
RS2
sC2
IL2
L
2
Fb2
Comp2
Ve
R
S2
Based on the frequency of the zero generated by ESR
versus crossover frequency, the compensation type can
be different. The table below shows the compensation
type and location of crossover frequency.
E/A2
Vp2
R2
RS1
C2
L
1
Compensator
Type
Location of Zero
Crossover Frequency
(FO)
Typical
Output
I
L1
Capacitor
Electrolytic,
Tantalum
Tantalum,
Ceramic
Figure 17 - The PI compensation network
for slave channel.
Type II (PI)
FPO < FZO < FO < fS/2
Type III (PID)
Method A
FPO < FO < FZO < fS/2
FPO < FO < fS/2 < FZO
The loop gain function is:
Type III (PID)
Method B
Ceramic
H(s)=[G(s) × D(s) × RS2]
Table - The compensation type and location of zero
crossover frequency.
Details are dicussed in application Note AN-1043 which
can be downloaded from the IR Web-Site.
RS1
RS2
1+sR2C2
VIN-VOUT
sL2×VOSC
×
×
H(s)=RS2× gm×
( ) ( ) ( )
sC2
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15
IRU3146
Layout Consideration
Select a zero crossover frequency for control loop (FO2)
1.25 times larger than zero crossover frequency for volt-
age loop (FO1):
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Fo2 ≅ 1.25%xF01
VIN - VOUT
2π×Fo×L2×VOSC
Start by placing the power components. Make all the
connections in the top layer with wide, copper filled ar-
eas. The inductor, output capacitor and the MOSFET
should be as close to each other as possible. This helps
to reduce the EMI radiated by the power traces due to
the high switching. Place input capacitor near to the
drain of the high-side MOSFET.
H(Fo) = gm×RS1×R2×
=1 ---(20)
From (20), R2 can be express as:
1
2π × FO2 × L2 × VOSC
---(21)
R2 =
×
VIN - VOUT
gm × RS1
The layout of driver section should be designed for a low
resistance (a wide, short trace) and low inductance (a
wide trace with ground return path directly beneath it),
this directly affects the driver's performance.
Set the zero of compensator to be half of FLC(SLAVE), the
compensator capacitor, C2, can be calculated as:
1
FLC(SLAVE) =
To reduce the ESR, replace the one input capacitor with
two parallel ones. The feedback part of the system should
be kept away from the inductor and other noise sources
and must be placed close to the IC. In multilayer PCB's,
use one layer as power ground plane and have a sepa-
rate control circuit ground (analog ground), to which all
signals are referenced. The goal is to localize the high
current paths to a separate loops that does not interfere
with the more sensitive analog control function. These
two grounds must be connected together on the PC board
layout at a single point.
2π L2×COUT
FLC(SLAVE)
Fz =
2
1
C2 =
---(22)
2π × R2 × Fz
When using the DCR of inductors as current sense ele-
ment, replace RS1 in equation (21) with DCR value of in-
ductor.
Switching Frequency vs. Case Temp
90
80
70
60
50
40
30
100pF
1000pF
1800pF
3300pF
200
300
400
500
600
700
Freq (KHz)
Figure18- Case Temperature versus Switching Frequency at Room Temperature
Test Condition: Vin=Vcl=Vch1=Vch2=12V, Capacitors used as loads for output
drivers.
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16
IRU3146
D1
BAT54S
C12
1uF
L1
12V
1uH
C11
0.1uF
C1
47uF
C2
47uF
C14
2x 47uF
16TPB47M
C13
1uF
C3
1uF
C4
1uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
IRF7457
R1
7.8K
C5
1uF
OCSet1
LDrv1
1.8V @ 10A
C16
4x 330uF, 40m
1.7uH
Q3
Hiccup
IRF7457
Ω
PGnd1
Sync
6TPB330M
V
P2
R20
1.24K
VSEN1
VREF
D2
BAT54A
R21
1K
R2
33K
R7
1.24K
U1
IRU3146
Rt
V
SEN1
V
SEN1
R3
VSEN2
C8
20nF
VSEN2
R8
1K
Comp1
Fb1
Fb2
2.8K
R5
1K
R9
C17
2x 47uF
16TPB47M
R4
C9
18nF
Comp2
Q4
2.61K
HDrv2
L4
2.14K
IRF7457
R6
7.8K
OCSet2
2.5V @ 10A
1.7uH
Q5
IRF7457
PGood
PGood
C18
2x 330uF, 40m
6TPB330M
LDrv2
Ω
SS1 / SD
SS2 / SD
R22
2.24K
PGnd2
Gnd
C10
0.1uF
VSEN2
C15
0.1uF
R23
1K
Figure 19 - Typical application of IRU3146.
12V input and two independent outputs.
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17
IRU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 21 - Input Supply Ramps up/down.
Ch1: 1.8V, Ch2: 2.5V, Ch3: Input Supply
Figure 20 - Input Supply Ramps up.
Ch1: 1.8V, Ch2: 2.5V, Ch3: Input Supply
Figure 22 - Normal condition at No Load.
Ch1: HDrv2, Ch2: HDrv1, Ch3 and Ch4: Inductor
Currents
Figure 23 - Normal condition at 10A Load.
Ch1: HDrv2, Ch2: HDrv1, Ch3 and Ch4: Inductor
Currents
Ch3:ch4: 5A/div
Ch3:ch4: 5A/div
Rev. 1.1
6/25/04
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18
IRU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 25 - Soft_Start.
Ch1: Vin, Ch2: Vout3(LDO), Ch3: SS2, Ch4: SS2
Figure 24 - Soft_Start.
Ch1: SS2, Ch2: 1.8V, Ch3: SS1, Ch4: 2.5V
Figure 27 - Deadband Time (2.5V Output).
Ch1: LDrv1, Ch2: HDrv1, Ch3: Switching Node
Figure 26 - Deadband Time (1.8V Output).
Ch1: LDrv2, Ch2: HDrv2, Ch3: Switching Node
Rev. 1.1
6/25/04
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19
IRU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 29 - Shut Down (pulling down the SS2 pin).
Figure 28 - Shut Down (Pulling down the SS1 pin).
Ch1: HDrv1, Ch2: LDrv1, Ch3: SS1
Ch1: HDrv2, Ch2: LDrv2, Ch3: SS2
Figure 31 - High side and Low side Drivers peak
Current for 2.5V Output
Ch1: HDrv1, Ch2: LDrv1, Ch3: High Side Peak
Current, Ch4: Low Side Peak Current
Figure 30 - High side and Low side Drivers peak
Current for 1.8V Output
Ch1: HDrv2, Ch2: LDrv2, Ch3: High Side Peak
Current, Ch4: Low Side Peak Current
Ch3:ch4: 1A/div
Ch3:ch4: 1A/div
Rev. 1.1
6/25/04
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20
IRU3146
TYPICAL OPERATING CHARACTERISTICS
Test Conditions:
VIN=12V, VOUT1=2.5V, IOUT1=0-10A, VOUT2=1.8V, IOUT2=0-10A, Fs=300KHz
Figure 32 - Load Transient Response.
Ch2: 2.5V, Ch4: Step Load (0-10A)
Figure 33 - Load Transient Response.
Ch1: 1.8V, Ch3: Step Load (0-10A)
Ch3:ch4: 5A/div
Ch3:ch4: 5A/div
Figure 35 - Short Circuit Condition (Hiccup Mode).
Ch1: SS1 pin, Ch2: SS2 pin, Ch3 and Ch4 : Inductor
Currents
Figure 34 - Power Good Signal
Ch1: Input Supply, Ch2: 2.5V Output, Ch3: 1.8V
Output, Ch4 : Power Good Signal
Ch3:ch4: 10A/div
Rev. 1.1
6/25/04
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21
IRU3146
TYPICALAPPLICATION
D1
BAT54S
C12
L1
1uF
12V
1uH
C11
0.1uF
C1
C2
47uF
47uF
C14
3x 47uF
C13
1uF
C3
1uF
C4
1uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
IRFR3706
R1
12K
C5
1uF
OCSet1
LDrv1
1uH, 2mΩ DCR
Q3
Hiccup
Sync
R5
IRFR3711
1.8V @ 30A
C16
8x 330uF, 40m
6TPB330M
PGnd1
1K
C15
1uF
VP2
VREF
D2
Ω
V
SEN
BAT54A
R2
33K
U1
IRU3146
R20
1.24K
Rt
R21
1K
V
SEN1
R7
1.24K
VSEN
R3
C8
22nF
VSEN2
Comp1
Fb1
Fb2
2.2K
R8
1K
R9
1K
L4
C6 120pF
C17
R4
3x 47uF
C9
Comp2
C18
1uF
12nF
8K
Q4
HDrv2
IRFR3706
R6
OCSet2
C7
82pF
1uH, 2mΩ DCR
12K
Q5
PGood
PGood
LDrv2
IRFR3711
SS1 / SD
SS2 / SD
PGnd2
Gnd
C10
0.1uF
Figure 36 - 2-phase operation with inductor current sensing.
12V to 1.8V @ 30A output
Rev. 1.1
6/25/04
www.irf.com
22
IRU3146
TYPICALAPPLICATION
D1
BAT54S
C12
L1
1uF
12V
1uH
C11
0.1uF
C1
C2
47uF
47uF
C14
3x 47uF
C13
1uF
C3
1uF
C4
1uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
IRFR3706
R1
12K
R5
2m
C5
1uF
OCSet1
LDrv1
1.8V @ 30A
C16
8x 330uF, 40m
1uH
Ω
Q3
Hiccup
Sync
IRFR3711
Ω
PGnd1
VP2
6TPB330M
R20
1.24K
VREF
D2
VSEN
BAT54A
R2
33K
U1
IRU3146
R21
1K
Rt
V
SEN1
R7
1.24K
R3
V
SEN
C8
22nF
VSEN2
Comp1
Fb1
Fb2
2.2K
R8
1K
C6 120pF
C17
3x 47uF
R4
C9
12nF
8K
Comp2
Q4
IRFR3706
HDrv2
L4
R9
2m
R6
OCSet2
C7
82pF
1uH
12K
Ω
Q5
IRFR3711
PGood
PGood
LDrv2
SS1 / SD
SS2 / SD
PGnd2
Gnd
C10
0.1uF
Figure 37 - 2-phase operation with resistor current sensing.
12V to 1.8V @ 30A output
Rev. 1.1
6/25/04
www.irf.com
23
IRU3146
TYPICALAPPLICATION
L2
5V
1uH
C17
C18
3x 150uF
150uF
C19
0.1uF
D3
D1
BAT54S
BAT54S
C12
1uF
C20
1uF
C13
1uF
L1
12V
C11
0.1uF
1uH
C2
47uF
C1
C14
3x 47uF
C3
1uF
C4
1uF
47uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
IRFR3706
R1
C5
1uF
OCSet1
LDrv1
1.8V @ 30A
C16
8x 330uF, 40m
6TPB330M
1uH,
2mΩ
12K
Q3
DCR
R5
1K
Hiccup
Sync
IRFR3711
Ω
PGnd1
C21
1uF
VP2
R20
VREF
D2
1.24K
BAT54A
R2
33K
U1
IRU3146
Rt
R21
1K
V
SEN1
R7
1.24K
R3
C8
22nF
VSEN2
Comp1
Fb1
Fb2
2.2K
C22
1uF
R8
1K
C6 120pF
R9
1K
R4
C9
Q4
IRFR3706
R6
12K
IRFR3711
Comp2
HDrv2
4.7nF
C7
23K
L4
1uH,
OCSet2
LDrv2
27pF
Q5
PGood
PGood
2mΩ DCR
SS1 / SD
SS2 / SD
PGnd2
Gnd
C10
0.1uF
Figure 38 - Typical application of IRU3146 using 5V and 12V supplies to generate single output voltage.
1.8V @ 30A using inductor sensing.
Rev. 1.1
6/25/04
www.irf.com
24
IRU3146
TYPICALAPPLICATION
L2
1uH
5V
C17
3x 150uF
C18
150uF
C19
0.1uF
D3
D1
BAT54S
BAT54S
C20
1uF
C13
1uF
C12
1uF
L1
12V
1uH
C11
0.1uF
C1
47uF
C2
47uF
C14
3x 47uF
C3
1uF
C4
1uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
IRFR3706
R1
R5
2m
C5
1uF
OCSet1
LDrv1
1.8V @ 30A
C16
1uH
15K
Ω
Q3
Hiccup
Sync
IRFR3711
8x 330uF, 40m
Ω
PGnd1
VP2
6TPB330M
R20
1.24K
VREF
D2
BAT54A
R2
33K
U1
IRU3146
R21
1K
Rt
VSEN1
R7
R3
C8
22nF
1.24K
V
SEN2
Comp1
Fb1
Fb2
2.2K
R8
1K
C6 120pF
R4
C9
Comp2
Q4
IRFR3706
4.7nF
C7
23K
HDrv2
L4
R9
3m
R6
OCSet2
27pF
1uH
10K
Ω
Q5
IRFR3711
PGood
PGood
LDrv2
SS1 / SD
SS2 / SD
PGnd2
Gnd
C10
0.1uF
Figure 39 - Typical application of IRU3146.
1.8V @ 30A output with 5V and 12V input and different input current setting.
(5V @ 5A and 12V @ 3A)
Rev. 1.1
6/25/04
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25
IRU3146
TYPICALAPPLICATION
D1
BAT54S
C12
L1
1uF
5V
1uH
C11
0.1uF
C1
47uF
C2
47uF
C14
3x 330uF
6TPB330M
C13
1uF
C3
1uF
C4
1uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
IRF7457
R1
C5
1uF
OCSet1
LDrv1
1.8V @ 10A
C16
4x 330uF, 40m
6TPB330M
1uH
10K
Q3
Hiccup
IRF7460
Ω
R20
1.24K
PGnd1
Sync
VP2
VSEN1
VREF
D2
BAT54A
R21
1K
R2
33K
R7
1.24K
U1
IRU3146
Rt
V
SEN1
R3
6K
C8
8.2nF
VSEN2
R8
1K
Comp1
Fb1
Fb2
R5
1K
R9
C17
3x 330uF
6TPB330M
C6 47pF
R4
C9
4.7nF
15K
Comp2
Q4
HDrv2
L4
1/2 IRF7910
2.14K
R6
OCSet2
2.5V @ 5A
C7
27pF
3.3uH
8.5K
Q5
PGood
PGood
C18
2x 330uF, 40m
6TPB330M
LDrv2
1/2 IRF7910
Ω
SS1 / SD
SS2 / SD
PGnd2
Gnd
C10
0.1uF
C15
0.1uF
R22
2.14K
VSEN2
R23
1K
Figure 40 - Single 5V input and two independent outputs.
Rev. 1.1
6/25/04
www.irf.com
26
IRU3146
TYPICALAPPLICATION
12V
L1
5V
1uH
C14
C1
47uF
C2
47uF
3x 330uF
6TPB330M
C13
1uF
C3
1uF
C4
1uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
IRF7457
R1
C5
1uF
OCSet1
LDrv1
1.8V @ 10A
C16
4x 330uF, 40m
1uH
10K
Q3
Hiccup
IRF7460
Ω
R20
1.24K
PGnd1
Sync
6TPB330M
VP2
VSEN1
V
REF
D2
BAT54A
R21
1K
R2
33K
R7
1.24K
U1
IRU3146
Rt
V
SEN1
R3
6K
C8
8.2nF
VSEN2
R8
1K
Comp1
Fb1
Fb2
R5
1K
C17
C6 47pF
3x 330uF
6TPB330M
R4
C9
Comp2
4.7nF
15K
R9
2.14K
Q4
HDrv2
L4
IRF7457
R6
OCSet2
2.5V @ 5A
C7
27pF
3.3uH
5.1K
Q5
PGood
PGood
C18
2x 330uF, 40m
6TPB330M
LDrv2
IRF7460
Ω
SS1 / SD
SS2 / SD
PGnd2
Gnd
R22
2.14K
C10
0.1uF
C15
0.1uF
VSEN2
R23
1K
Figure 41 - Typical application of IRU3146.
5V input, 12V drive and two independent outputs.
Rev. 1.1
6/25/04
www.irf.com
27
IRU3146
TYPICALAPPLICATION
3.3V
D1
BAT54S
C12
1uF
L1
5V
1uH
C11
0.1uF
C1
47uF
C2
47uF
C14
2x 330uF
6TPB330M
C13
1uF
C3
1uF
C4
1uF
V
CL VcH1
VcH2
VOUT3
Q2
HDrv1
Vcc
L3
1/2 IRF7910
R1
C5
1uF
OCSet1
LDrv1
2.5V @ 5A
C16
2x 330uF, 40m
6TPB330M
3.3uH
8.5K
Q3
Hiccup
1/2 IRF7910
Ω
R20
2.14K
PGnd1
Sync
VP2
VSEN1
VREF
D2
BAT54A
R21
1K
R2
33K
R7
2.14K
R8
U1
IRU3146
V
V
SEN1
Rt
SEN2
R3
C8
4.7nF
Fb1
Fb2
Comp1
15K
1K
C6 27pF
C17
2x 330uF
6TPB330M
R5
1K
R4
C9
Comp2
R9
1.24K
5.6nF
8.2K
Q4
HDrv2
L4
1/2 IRF7910
R6
OCSet2
1.8V @ 5A
C7
27pF
2.2uH
8.5K
Q5
PGood
PGood
C18
2x 330uF, 40m
6TPB330M
LDrv2
1/2 IRF7910
Ω
SS1 / SD
SS2 / SD
PGnd2
Gnd
C10
0.1uF
C15
0.1uF
R22
1.24K
VSEN2
R23
1K
Figure 42 - Typical application of IRU3146.
5V to 2.5V and 3.3V to 1.8V inputs and two independent outputs.
Rev. 1.1
6/25/04
www.irf.com
28
IRU3146
(F) TSSOP Package
28-Pin
A
L
Q
R1
C
B
1.0 DIA
R
E
N
M
P
O
PIN NUMBER 1
F
D
DETAIL A
DETAIL A
G
J
H
K
28-PIN
NOM
0.65 BSC
SYMBOL
MIN
4.30
0.19
MAX
DESIG
A
4.40
6.40 BSC
---
4.50
0.30
B
C
D
1.00
1.00
9.70
---
E
F
9.60
---
9.80
1.10
0.95
0.15
G
H
0.85
0.05
0.90
---
J
K
12ꢀ REF
12ꢀ REF
---
L
M
N
0ꢀ
8ꢀ
1.00 REF
0.60
0.20
---
O
P
0.50
0.75
Q
R
0.09
0.09
---
---
---
R1
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
Rev. 1.1
6/25/04
www.irf.com
29
IRU3146
PACKAGE SHIPMENT METHOD
PKG
PACKAGE
PIN
COUNT
28
PARTS
PER TUBE
50
PARTS
PER REEL
2500
T & R
Orientation
Fig A
DESIG
DESCRIPTION
F
TSSOP
1
1
1
Feed Direction
Figure A
This product has been designed and qualified for the Industrial market.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 02/01
Rev. 1.1
6/25/04
www.irf.com
30
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