IRUH330118AK [INFINEON]
+3.3VIN to +1.8VOUT @3.0A; + 3.3VIN至+ 1.8VOUT @ 3.0A型号: | IRUH330118AK |
厂家: | Infineon |
描述: | +3.3VIN to +1.8VOUT @3.0A |
文件: | 总9页 (文件大小:201K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD-97530A
IRUH330118AK
IRUH330118AP
Radiation Hardended Ultra Low Dropout
Fixed Positive Linear Regulator
+3.3V to +1.8V
@3.0A
IN
OUT
Product Summary
I
V
V
Part Number
O
IN
OUT
IRUH330118AK
IRUH330118AP
3.0A
3.3V
1.8V
8-LEAD FLAT PACK
Features
Description
The IRUH330118 is a space qualified, ultra low dropout
linear regulator designed specifically for applications
requiring high reliability, low noise and radiation hardness.
n
Silicon On Insulator (SOI) CMOS Regulator
IC, CMOS Latch-Up Immune,
Inherently Rad Hard
n
n
Total Dose Capability up to 300Krads(Si)
(Condition A); Tested to 500Krad (Si)
ELDRS up to 100Krad(Si) (Condition D)
n
n
n
n
n
n
SEU Immune up to LET = 80 MeV*cm2/mg
Space Level Screened
Fast Transient Response
Timed Latch-Off Over-Current Protection
Internal Thermal Protection
On/Off Control via Shutdown Pin, Power
Sequencing Easily Implemented
Isolated Hermetic 8-Lead Flat Pack
Ensures Higher Reliability
This part is also available in MO-078 Package
as IRUH330118BK / IRUH330118BP
n
n
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
P
D
-
25
W
Power Dissipation @ T = 125°C
C
Maximum Output Current @ Maximum
Power Dissipation with no Derating
Non-Operating Input Voltage
Operating Input Voltage
I
-
See Fig 4
A
O
V
V
-0.3
2.9
+8.0
6.4
IN
IN
V
Ground
0.3
GND
-0.3
-0.3
V
V
V
+ 0.3
+ 0.3
Shutdown Pin Voltage
SHDN
IN
IN
Output Pin Voltage
V
-0.3
OUT
T
O
Operating Case Temperature Range
Storage Temperature Range
Maximmum Junction Temperature
Lead Temperature (Soldering 10sec)
Pass Transistor Thermal Resistance, Junction to Case
-55
+140
T
S
-65
+150
+150
+300
1.0
°C
T
J
-
-
-
T
L
R
°C/W
THJC
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1
08/02/10
IRUH330118AK
IRUH330118AP
Electrical Characteristics
Pre-Radiation @TC = 25°C, VIN = 3.3V (Unless Otherwise Specified)
Parameter
Test Conditions
Symbol
Min. Typ. Max. Units
2.8V ≤ V ≤ 3.8V, 50mA ≤ I
≤ 3.0A
1.773
1.8
1.827
IN
OUT
≤
≤
≤
≤
≤
≤
2.8V
V
3.8V, 50mA
I
3.0A,
3.0A,
IN
OUT
OUT
1.728
1.8
1.872
Output Voltage
-55°C to +125°C
V
V
OUT
≤
≤
3.8V, 50mA
2.8V
V
I
IN
1.755
3.5
1.8
-
1.836
-
Post -Rad
Over-Current Latching, -55°C to +125°C,
Post -Rad
Current Limit
A
I
t
LATCH
I
> I
LATCH
10
-
-
-
-
Over-Current Time-to-Latch
Maximum Shutdown Temp.
-
ms
°C
O
LATCH
T
125
65
40
140
LATCH
F= 120Hz, I = 50mA, -55°C to +125°C
-
-
O
Ripple Rejection
PSRR
dB
F= 120Hz, I = 50mA, Post -Rad
O
Temp. Coefficient of
Output Voltage
-55°C to +125°C
-55°C to +125°C
V
_
-
-
-
-0.025
-
% / °C
OUT TEMPCO
V
Pin Current
I
1.6
-
-
mA
V
SENSE
SENSE
I
= 200µA, -55°C to +125°C
Minimum SHDN Pin "On"
Threshold Voltage
SOURCE
0.8
V
V
SHDN
SHDN
Post -Rad
= 200 A, -55°C to +125°C
µ
Maximum SHDN Pin "Off"
Threshold Voltage
I
SOURCE
1.2
-
-
-
V
Post -Rad
= 36 Ohms, V
R
= 3.3V
SHDN
LOAD
Output Voltage at Shutdown
SHDN Pin Leakage Current
V
-0.1
0.1
V
OUT
-55°C to +125°C, Post-Rad
V
V
V
V
= 3.3V, -55°C to +125°C,Post-Rad
I
-10
-98
-140
-98
-
-
-
10
-56
-30
-56
-
µA
SHDN
SHDN
SHDN
SHDN
SHDN
= 0.4V
= 0.4V, -55°C to +125°C
= 0.4V, Post-Rad
I
SHDN Pin Pull-Up Current
Power On Reset Threshold
Quiescent Current
-
µ
A
SHDN
-
Sweep V and Measure Output
IN
V
T-POR
1.7
V
15
No Load
Full Load
-
-
-
-
I
mA
Q
90
Notes:
Connected as shown in Fig.1 and measured at the junction of VOUT and VSENSE Pins.
Under normal closed-loop operation. Guaranteed by design. Not tested in production.
2
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IRUH330118AK
IRUH330118AP
Radiation Performance Characteristics
Test
Conditions
Min
Typ
Unit
MIL-STD-883, Method 1019 (Condition A)
Operating Bias applied during exposure
Minimum Rated Load, Vin = 6.4V
Total Ionizing Dose (Gamma)
300
500
Krads (Si)
MIL-STD-883, Method 1019 (Condition D)
See
Krads (Si)
MeV*cm2/mg
Neutrons/cm2
Total Ionizing Dose (Gamma) (ELDRS) Operating Bias applied during
exposure Minimum Rated Load, Vin = 6.4V
100
84
Single Event effects
Heavy Ions (LET)
SEU, SEL, SEGR, SEB
Operating Bias applied during exposure
under varying operating conditions
11
Neutron Fluence
MIL-STD-883, Method 1017
1.0e
Notes:
Tested to 500Krad (Si).
See Fig. 5.
Space Level Screening Requirements
TEST/INSPECTION
SCREENING LEVEL
MIL-STD-883
METHOD
SPACE
Nondestructive Bond Pull
Internal Visual
Seal
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
2023
2017
1014
1010
2001
2002
2020
Temperature Cycle
Constant Acceleration
Mechanical Shock
PIND
Pre Burn-In-Electrical
Burn-In
1015
Final Electrical
Radiographic
100%
100%
2012
2009
External Visual
Notes:
International Rectifier does not currently have a DSCC certified Radation Hardness Assurance Program.
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IRUH330118AK
IRUH330118AP
Application Information
Input
Voltage
Output
Voltage
VIN
VOUT
0.1uF and 1uF
Ceramic;
0.1uF and 1uF
Ceramic;
IRUH3301xxxx VSENSE
Two 100uF
Low ESR
Tantalum
Two 100uF
Low ESR
Tantalum
SHDN
GND
Fig. 1. Typical Regulator Circuit; Note the SHDN Pin is hardwired in the “ON” position.
The VSENSE Pin is connected as noted in the “General Layout Rules” section.
Over-Current & Over-Temperature Protection
The IRUH3301 series provides over-current protection by means of a timed latch function. Drive
current to the internal PNP pass transistor is limited by an internal resistor (Rb in Fig. 3) between
the base of the transistor and the control IC drive FET. If an over-current condition forces the
voltage across this resistor to exceed 0.5V (nom), the latch feature will be triggered. The time-to-
latch (tLATCH) is nominally 10ms. If the over-current condition exists for less than tLATCH , the latch
will not be set. If the latch is set the drive current to the PNP pass transistor will be disabled. The
latch will remain set until one of the following actions occur:
1. The SHDN Pin voltage is brought above 1.2V and then lowered below 0.8V.
2. The VIN Pin voltage is lowered below 1.7V.
If the junction temperature of the regulator IC exceeds 140°C nominal, the thermal shutdown circuit
will set the internal latch and disable the drive current to the PNP pass transistor as described
above. After the junction temperature falls below a nominal 125°C, the latch can be reset using
either of the actions described above.
Under-Voltage Lock-Out
The under-voltage lock-out (UVLO) function prevents operation when VIN is less than 1.7V
(nominal). There is a nominal 100mV hysteresis about this point.
Input Voltage Range
The device functions fully when VIN is greater than 2.8V. It enters into under-voltage lock-out at VIN
< 1.7V (nominal). When 1.7V (nominal) < VIN < 2.8V, VOUT will track VIN and overshoot may occur.
A larger output capacitor should be used to slow down the VOUT rise rate for slow VIN ramp
applications.
Shutdown (SHDN)
The regulator can be shutdown by applying a voltage of >1.2V to the SHDN Pin. The regulator will
restart when the SHDN Pin is pulled below the shutdown threshold of 0.8V. If the remote shutdown
feature is not required, the SHDN Pin should be connected to GND.
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IRUH330118AK
IRUH330118AP
Input Capacitance
Input bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX
TPS or equivalent), placed very close to the VIN Pin are required for proper operation. When the
input voltage supply capacitance is more than 4 inches from the device, additional input
capacitance is recommended. Larger input capacitor values will improve ripple rejection further
improving the integrity of the output voltage.
Output Capacitance
Output bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums
(AVX TPS or equivalent) are required for loop stability. Faster transient performance can be
achieved with multiple additional 1µF ceramic capacitors. Ceramic capacitors greater than 1µF in
value are not recommended as they can cause stability issues.
Tantalum capacitor values larger than the suggested value are recommended to improve the
transient response under large load current changes. The upper capacitance value limit is
governed by the delayed over-current latch function of the regulator and can be as much as
10,000µF without causing the device to latch-off during start-up.
General Layout Rules
Low impedance connections between the regulator output and load are essential. Solid power and
ground planes are highly recommended. In those cases where the board impedances are not kept
very small, oscillations can occur due to the effect of parasitic series resistance and inductance
on loop bandwidth and phase margin.
The VSENSE Pin must be connected directly to the VOUT Pin using as short a trace as possible with
the connection inside the first bypass capacitor (see Fig. 2a).
Connect ceramic output capacitors directly across the VOUT and GND Pins with as wide a trace as
design rules allow (see Fig. 2a). Avoid the use of vias for these capacitors and avoid loops. Fig.2
shows the ceramic capacitors tied directly to the regulator output.
The input capacitors should be connected as close a possible to the VIN Pin.
Fig. 2a. Layer 1 conductor.
Ground plane below layer 1
Fig. 2b. Layer 1 silkscreen
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IRUH330118AK
IRUH330118AP
VSENSE
VOUT
VIN
Input
Undervoltage
detect
Rb
SHDN
Shutdown
& Over
Current
Latch
Disable
Thermal
Shutdown
-
Error
Amp
+
Latch
Timing
capacitor
VREF
GND
Fig. 3. Simplified Schematic Circuit
Maximum Output Current (A) with no derating at Maximum Dissipation
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
110
120
130
140
150
160
170
Mounting Surface Temperature (’C)
Fig. 4. Maximum Output Current versus Mounting Surface Temperaturewith no Derating at Maximum
Dissipation
6
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IRUH330118AK
IRUH330118AP
VOut
0.500%
0.250%
0.000%
-0.250%
-0.500%
ELDRS
TID
1
10
100
1000
10000 100000
Total Dose (Rad (Si))
Fig. 5. Change in Output Voltage vs. Total Ionizing Dose Radiation Exposure at Both High and Low Dose Rates
PSRR (Typical)
105
95
85
75
65
55
45
35
25
15
5
-5
0.1
1
10
100
1000
10000
Freq (KHz)
Recomended Setup without Part
Iout=100mA & 1.6A, 1.8Vout, 3.3Vin
Fig. 6. Typical Power Supply Ripple Rejection at 100mA and 1.6A using recommended layout
and capacitors. Results above 10KHz are influenced by testing setup and layout.
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IRUH330118AK
IRUH330118AP
Fig 7. Case Outline and Dimensions - 8-Lead Flat Pack (Lead Form Down)
Pin Assignment
Pin #
Pin Description
1
2
GND
GND
3
4
SHUTDOWN
V
SENSE
V
5
6
7
8
OUT
V
OUT
V
IN
VIN
Note:
1) All dimensions are in inches
Warning: This Product contains BeO
Fig 8. Case Outline and Dimensions - 8-Lead Flat Pack (Lead Trimmed)
Pin Assignment
Pin #
Pin Description
1
2
GND
GND
3
4
SHUTDOWN
V
SENSE
V
5
6
7
8
OUT
V
OUT
V
IN
VIN
Note:
1) All dimensions are in inches
Warning: This Product contains BeO
8
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IRUH330118AK
IRUH330118AP
Part Numbering Nomenclature
IR U H3 301 18 A K
Lead Form Options
Blank = Lead Form Down (Fig. 7)
B = Lead Form Up
Linear Regulator
U = Ultra Low Dropout Regulator
C = Lead Trimmed (Fig. 8)
Radiation Hardening
Blank = No Rad Tolerance
H3 = 300 Krads
Screening Level
P = Unscreened. 25 deg C
Electrical Test Not for Qualification
H = Class H per MIL-PRF-38534
K = Class K per MIL-PRF-38534
Device indicator
301 = 3 Amp Positive Regulator
Output Voltage
18 = 1.8V
25 = 2.5V
33 = 3.3V
Package Type
A = 8 Lead Flat Pack
A1 = Adjustable Optimized for 3.3 V Input
A2 = Adjustable Optimized for 5.0V Input
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 08/2010
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