ISO1H816G_技术文档

Datasheet, Version 2.0, July 2009

ISOFACE^TM

ISO1H816G

Coreless Transformer Isolated

Digital Output 8 Channel 1.2A

High-Side Switch

Power Management & Drives

N e v e r s t o p t h i n k i n g .

ISO1H816G

Revision History:

2009-07-28

Version 2.0

Previous Version:

V1.0

2.0

Final Datasheet

Edition 2009-07-28

Published by Infineon Technologies AG,

Am Campeon 1-12,

85579 Neubiberg, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

ISOFACE^TM

ISO1H816G

Coreless Transformer Isolated Digital

Output 8 Channel 1.2A High-Side Switch

Product Highlights

• Coreless transformer isolated data interface

• Galvanic isolation

• 8 High-side output switches 1.2A

• µC compatible 8-bit serial peripheral

• Isolated return path for DIAG signal

Features

Typical Application

•

Interface CMOS 3.3/5V operation compatible

Serial Interface

High common mode transient immunity

Short circuit protection

Maximum current internally limited

Overload protection

Overvoltage protection (including load dump)

Undervoltage shutdown with autorestart and

hysteresis

•

Isolated switch for industrial applications (PLC)

All types of resistive, inductive and capacitive loads

µC compatible power switch for 24V DC

applications

•

Driver for solenoid, relays and resistive loads

Description

•

Switching inductive loads

Common output disable pin

Thermal shutdown with restart

Thermal independence of seperate channels

Common diagnostic output for overtemperature

ESD protection

Loss of GNDbb and loss of V_bbprotection

Very low standby current

Reverse battery protection

The ISO1H816G is a galvanically isolated 8 bit data

interface in PG-DSO-36 package that provides 8 fully

protected high-side power switches that are able to

handle currents up to 1.2 A.

An serial µC compatible interface allows to connect the

IC directly to a µC system. The input interface is

designed to operate with 3.3/5V CMOS compatible

levels.

RoHS compliant

The data transfer from input to output side is realized by

the integrated Coreless Transformer Technology.

Typical Application

VCC

DIS

Vbb

VCC

CT

VCCP1.x

Control

Unit

CS

AD0

WR

SCLK

OUT0

DIAG

Control

&

Protectio

n Unit

SI

P0.0

OUT1

Serial

Interface

SO

for daisy chain

DIAG

OUT7

µC (i.e

C166)

GND

GNDCC

GNDbb

ISO1H812G

Type

On-state Resistance

Package

ISO1H816G

200mΩ

PG-DSO-36

Datasheet

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Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Pin Configuration and Functionality

1

Pin Configuration and Functionality

1.1

Pin Configuration

Vbb

Pin Symbol

Function

N.C.

VCC

DIS

1

2

3

4

5

6

7

36 OUT0

35 OUT0

34 OUT1

33 OUT1

32 OUT2

31 OUT2

30 OUT3

29 OUT3

28 OUT4

27 OUT4

26 OUT5

25 OUT5

24 OUT6

23 OUT6

22 OUT7

21 OUT7

20 N.C.

TAB

1

2

N.C.

VCC

DIS

Not connected

Positive 3.3/5V logic supply

Output disable

Chip select

CS

SCLK

SI

N.C.

SO

3

4

CS

5

SCLK

SI

Serial Clock

6

Serial Data input

Not connected

Serial Data Output

8

9

7

N.C.

SO

8

10

11

12

13

14

15

16

17

18

9

10

11

12

13

14

DIAG

GNDCC

N.C.

DIAG

Common diagnostic output for

overtemperature

TAB

Vbb

19 GNDbb

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

TAB

GNDCC Input logic ground

N.C.

Not connected

Figure 1

Power SO-36 (430mil)

.

GNDbb Output driver ground

N.C

Not connected

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

Vbb

High-side output of channel 7

High-side output of channel 6

High-side output of channel 5

High-side output of channel 4

High-side output of channel 3

High-side output of channel 2

High-side output of channel 1

High-side output of channel 0

Positive driver power supply voltage

Datasheet

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ISOFACE^TM

ISO1H816G

Pin Configuration and Functionality

1.2

Pin Functionality

GNDCC (Ground for VCC domain)

This pin acts as the ground reference for the input

interface that is supplied by VCC.

VCC (Positive 3.3/5V logic supply)

The VCC supplies the input interface that is

galvanically isolated from the output driver stage. The

input interface can be supplied with 5V.

GNDbb (Output driver ground domain)

This pin acts as the ground reference for the output

driver that is supplied by Vbb.

DIS (Output disable)

The high-side outputs OUT0...OUT7 can be

immediately switched off by means of the low active pin

DIS that is an asynchronous signal. The input registers

are also reset by the DIS signal. The output remains

switched off after low-high transient of DIS, till new data

is written into the input interface. Current Sink to

GNDCC

OUT0 ... OUT7 (High side output channel 0 ... 7)

The output high side channels are internally connected

to Vbb and controlled by the corresponding data input.

TAB (Vbb, Positive supply for output driver)

The heatslug is connected to the positive supply port of

the output interface.

CS (Chip select)

The system microcontroller selects the ISO1H816G by

means of the low active pin CS to activate the interface.

Current Source to VCC

SCLK (Serial shift clock)

SCLK (serial clock) is used to synchronize the data

transfer between the master and the ISO1H816G. Data

present at the SI pin are latched on the rising edge of

the serial clock input, while data at the SO pin is

updated after the falling edge of SCLK in serial mode.

Current Source to VCC

SI (Serial data input)

This pin is used to transfer data into the device. Data is

latched on the rising edge of the serial clock. Current

Sink to GNDCC

SO (Serial data output)

This pin is used when the serial interface is activated.

SO can be connected to a serial input of a further IC to

built a daisy-chain configuration. It is only actvated if CS

is in low state, otherwise this output is in high

impedance state.

DIAG (Common diagnostic output for

overtemperature)

The low active DIAG signal contains the OR-wired

information of the separated overtemperature detection

units for each channel.The output pin DIAG provides an

open drain functionality that. A current source is also

connected to the pin DIAG. In normal operation the

signal DIAG is high. When overtemperature or Vbb

below ON-Limit is detected the signal DIAG changes to

low.

Datasheet

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Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Blockdiagram

2

Blockdiagram

n o i t a l o I s

i c n a l v a G

Figure 2

Blockdiagram

Datasheet

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ISOFACE^TM

ISO1H816G

Functional Description

3

Functional Description

3.1

Introduction

3.3.2

Power Transistor Overvoltage

Protection

The ISOface ISO1H816G includes 8 high-side power

switches that are controlled by means of the integrated Each of the eight output stages has its own zener clamp

µC compatible SPI interface. The outputs that causes a voltage limitation at the power transistor

OUT0...OUT7 are controlled by the data of the serial when solenoid loads are switched off. V_ONis then

input SI. The IC can replace 8 optocouplers and the 8 clamped to 47V (min.).

high-side switches in conventional I/O-Applications as

Vbb

a galvanic isolation is implemented by means of the

integrated coreless transformer technology. The µC

compatible interfaces allow a direct connection to the

ports of a microcontroller without the need for other

components. Each of the 8 high-side power switches is

Vbb

Vz

V_ON

protected

against

short

to

Vbb,

overload,

overtemperature and against overvoltage by an active

zener clamp.

OUTx

GNDbb

The diagnostic logic on the power chip recognizes the

overtemperature information of each power transistor

The information is send via the internal coreless

transformer to the pin DIAG at the input interface.

Figure 3

Inductive and overvoltage output

clamp (each channel)

3.2

Power Supply

Energy is stored in the load inductance during an

inductive load switch-off.

The IC contains 2 galvanic isolated voltage domains

that are independent from each other. The input

interface is supplied at VCC and the output stage is

supplied at Vbb. The different voltage domains can be

switched on at different time. The output stage is only

enabled once the input stage enters a stable state.

2

E_L= 1 ⁄ 2 × L × I_L

E_bb

E_AS

E

Load

Vbb

3.3

Output Stage

Dx

OUTx

L

Each channel contains a high-side vertical power FET

that is protected by embedded protection functions.

E

V

GNDbb

L

bb

Z

L

The continuous current for each channel is 1.2A (all

channels ON).

E_R

R

L

3.3.1

Output Stage Control

Figure 4

Inductive load switch-off energy

dissipation (each channel)

Each output is independently controlled by an output

latch and a common reset line via the pin DIS that

disables all eight outputs and reset the latches. Serial

data input (SI) is read on the rising edge of the serial

clock SCLK. A logic high input data bit turns the

respective output channel ON, a logic low data bit turns

it OFF. CS must be low whilst shifting all the serial data

into the device. A low-to-high transition of CS transfers

the serial data input bits to the output buffer.

While demagnetizing the load inductance, the energy

dissipation in the DMOS is

E_AS= E_bb+ E_L– E_R= V_ON(CL)× i_L(t)dt

with an approximate solution for R_L> 0W:

I_L× L

---------------

2 × R_L

I_L× R_L









E_AS

=

× (V_bb+ V_ON(CL)) × ln 1 + ------------------------

V_ON(CL)

Datasheet

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ISOFACE^TM

ISO1H816G

Functional Description

3.3.3

Power Transistor Overcurrent

Protection

IN

The outputs are provided with a current limitation that

enters a repetitive switched mode after an initial peak

current has been exceeded. The initial peak short

circuit current limit is set to I_L(SCp)at T_j= 125°C. During

the repetitive mode short circuit current limit is set to

t

VOUT

I_L

Normal

operation

Output short to GND

I_L(SCp)

I_L(SCr). If this operation leads to an overtemperature

t

condition, a second protection level (T_j> 135°C) will

change the output into a low duty cycle PWM (selective

thermal shutdown with restart) to prevent critical chip

temperatures.

I_L(SCr)

DIAG

IN

t

VOUT

Figure 7

Short circuit in on-state, shut down

down by overtemperature, restart by

cooling

t

T

J

3.4

Common Diagnostic Output

The overtemperature detection information are OR-

wired in the common diagnostic output block. The

information is send via the integrated coreless

transformer to the input interface. The output stage at

pin DIAG has an open drain functionality combined with

a current source.

DIAG

Figure 5

Overtemperature detection

VCC

The following figures show the timing for a turn on into

short circuit and a short circuit in on-state. Heating up

of the chip may require several milliseconds,

depending on external conditions.

Common

Diagnostic

Output

100µA

CT

DIAG

IN

t

VOUT

Output short to GND

t

I_L

I_L(SCp)

I_L(SCr)

Figure 8

Common diagnostic output

DIAG

Figure 6

Turn on into short circuit, shut down by

overtemperature, restart by cooling

Datasheet

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ISOFACE^TM

ISO1H816G

Functional Description

SI - Serial input. Serial data bits are shifted in at this pin,

the most significant bit first. SI information is read in on

the rising edge of the SCLK. Input data is latched in the

shift register and then transferred to the control buffer

of the output stages.

3.5

Serial Interface

The ISO1H816G contains a serial interface that can be

directly controlled by the microcontroller output ports.

3.5.1

SPI Signal Description

SO - Serial output. SO is in a high impedance state until

the CS pin goes to a logic low state. The data of the

internal shift register are shifted out serially at this pin.

The most significant bit will appear at first. The further

bits will appear following the falling edge of SCLK.

CS - Chip select. The system microcontroller selects

the ISO1H816G by means of the CS pin. Whenever the

pin is in a logic low state, data can be transferred from

the µC.

CS High to low transition:

3.5.2

SPI Bus Concepts

3.5.2.1

Independent Individual Control

•Serial input data can be clocked in from then on

Each IC with a SPI is controlled individually and

independently by an SPI master, as in a directional

point-to-point communication.The port requirements

for this topology are the greatest, because for each

controlled IC an individual SPI at the µC is needed

•SO changes from high impendance state to logic high

or low state corresponding to the SO bit-state

CS Low to high transition:

(SCLK, CS, SI). All ICs can be

simultaneously with the full SPI bandwidth.

addressed

•Transfer of SI bits from shift register into output

buffers, if number of clock signals was an integer

multiple of 8

CLK

Tx a1

Tx a2

SCLK

CS

SPI 1

•SO changes from the SO bit-state to high impendance

state

Output lines

SI

SO

SPI - Interface

IC1

To avoid any false clocking the serial input pin SCLK

should be logic high state during high-to-low transition

of CS. When CS is in a logic high state, any signals at

the SCLK and SI pins are ignored and SO is forced into

a high impedance state. The integrated modulo counter

that counts the number of clocks avoids the take over

of invalid commands caused by a spike on the clock

line or wrong number of clock cycles. A command is

only taken over if after the low-to-high transition of the

CS signal the number of counted clock cycles is an

integer multiple of 8.

CLK

Tx n1

Tx n2

SCLK

CS

SPI n

Output lines

SI

SO

SPI - Interface

µC

ICn

SCLK - Serial clock. The system clock pin clocks the

internal shift register of the ISO1H816G. The serial

input (SI) accepts data into the input shift register on the

rising edge of SCLK while the serial output (SO) shifts

the output information out of the shift register on the

falling edge of the serial clock. It is essential that the

SCLK pin is in a logic high state whenever chip select

CS makes any transition. The number of clock pulses

will be counted during a chip select cycle. The received

data will only be accepted, if exactly an integer multiple

of 8 clock pulses were counted during CS is active.

Number of adressed ICs = n

Number of necessary control and data ports = 3 n

Individual ICs are adressed by the chip select

Figure 9

Individual independent control of each

IC with SPI

3.5.2.2

Daisy-chain Configuration

The connection of different ICs and a µC as shown in

Fig. 11 is called a daisy-chain. For this type of bus-

topology only one SPI interface of the µC for two or

Datasheet

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ISOFACE^TM

ISO1H816G

Functional Description

more ICs is needed. All ICs share the same clock and wether the transmitted data is valid or not. If four times

chip select port of the SPI master. That is all ICs are serial data coming from the internal registers is not

active and addressed simultaneously. The data out of accepted the output stages are switched off until the

the µC is connected to the SI of the first IC in the line. next valid data is received.

Each SO of an IC is connected to the SI of the next IC

in the line.

CLK

Tx a1

Tx a2

SCLK

CS

SI

SPI 1

Output lines

SO

SPI - Interface

IC1

SCLK

CS

Output lines

SI

SPI - Interface

µC

ICn

Number of adressed ICs = n

Number of necessary control and data ports = 3

All ICs are adressed by the common chip select

Figure 10 SPI bus all ICs in a “daisy chain”

configuration

The µC feeds to data bits into the SI of IC1 (first IC in

the chain). The bits coming from the SO of IC1 are

directly shifted into the SI of the next IC. As long as the

chip select is inactive (logic high) all the IC SPIs ignore

the clock (SCLK) and input signals (SI) and all outputs

(SO) are in tristate. As long as the chip select is active

the SPI register works as a simple shift register. With

each clock signal one input is shifted into the SPI

register (SI), each bit in the shift register moves one

position further within the register, and the last bit in the

SPI shift register is shifted out of SO. This continous as

long as the chip select is active (logic low) and clock

signals are applied. The data is then only taken over to

the output buffers of each IC when the CS signal

changes to high from low and recognized as valid data

by the internal modulo counter.

3.6

Transmission Failure Detection

There is a failure detection unit integrated to ensure

also a stable functionality during the integrated

coreless transformer transmission. This unit decides

Datasheet

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ISOFACE^TM

ISO1H816G

Functional Description

3.7

Serial Interface Timing

Chipselect active

CS

SCLK

n+7

n+6

n-1

n+5

n-2

n+4

n-3

n+3

n-4

n+2

n-5

n+1

n-6

n

SI

SO

n

n-7

Figure 11 Serial interface

t_p(SCLK)

t_CSH

t_CSS

CS

t_CSD

SCLK

t_SU

t_HD

SI

MSB In

LSB In

Figure 12 Serial input timing diagram

CS

SCLK

t_SODIS

t_VALID

SO

MSB Out

LSB Out

Figure 13 Serial output timing diagram

Datasheet

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ISOFACE^TM

ISO1H816G

Electrical Characteristics

4

Electrical Characteristics

Note:All voltages at pins 2to 14 are measured with respect to ground GNDCC (pin 15). All voltages at pin 20 to

pin 36 and TAB are measured with respect to ground GNDbb (pin 19). The voltage levels are valid if other

ratings are not violated. The two voltage domains V_CC,GND_CCand V_bb,GND_bbare internally galvanic

isolated.

4.1

Absolute Maximum Ratings

Note:Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of

the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 2

(VCC) and TAB (Vbb) is discharged before assembling the application circuit. Supply voltages higher than

V_bb(AZ)require an external current limit for the GNDbb pin, e.g. with a 15Ω resistor in GNDbb connection.

Operating at absolute maximum ratings can lead to a reduced lifetime.

Parameter

Symbol

Limit Values

Unit

at T_j= -40 ... 135°C, unless otherwise specified

min.

max.

6.5

Supply voltage input interface (VCC)

Supply voltage output interface (Vbb)

Continuos voltage at pin SI

V_CC

V_bb

-0.5

-1¹⁾

V

45

V_Dx

V_CS

V_WR

V_DIS

V_Dx

V_DIAG

I_L

-0.5

---

6.5

Continuos voltage at pin CS

6.5

Continuos voltage at pin SCLK

Continuos voltage at pin DIS

Continuos voltage at pin SO

6.5

Continuos voltage at pin DIAG

Load current (short-circuit current)

Reverse current through GNDbb¹⁾

6.5

self limited

A

I_GNDbb

-1.6

---

Operating Temperature

Storage Temperature

Power Dissipation²⁾

Inductive load switch-off energy dissipation³⁾single

pulse, T_j= 125°C, I_L= 1.2A

T_j

-25

-50

---

internal limited °C

150

T_stg

P_tot

3.3

W

J

E_AS

one channel active

all channel simultaneously active (each channel)

10

1

---

Load dump protection³⁾V_loadDump⁴⁾=V_A+ V_S

V_Loaddump

V

V_IN= low or high

t_d= 400ms, R_I= 2W, R_L= 27W, V_A= 13.5V

t_d= 350ms, R_I= 2W, R_L= 57W, V_A= 27V

---

90

117

Electrostatic discharge voltage (Human Body Model)

according to JESD22-A114-B

V_ESD

kV

A

2

Electrostatic discharge voltage (Charge Device Model) V_ESD

according to ESD STM5.3.1 - 1999

Continuos reverse drain current¹⁾³⁾, each channel

1

I_S

4

---

1) defined by P_tot

2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB

is vertical without blown air.

3) not subject to production test, specified by design

4) V_Loaddumpis setup without the DUT connected to the generator per ISO7637-1 and DIN40839

Datasheet

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ISOFACE^TM

ISO1H816G

Electrical Characteristics

4.2

Thermal Characteristics

Parameter

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC= 3.0...5.5V,

unless otherwise specified

min.

typ.

max.

Thermal resistance junction - case

Thermal resistance @ min. footprint

Thermal resistance @ 6cm² cooling area¹⁾

R_thJC

1.5

50

38

K/W

---

R_th(JA)

1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB

is vertical without blown air.

4.3

Load Switching Capabilities and Characteristics

Parameter

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC= 3.0...5.5V,

unless otherwise specified

min.

typ.

max.

On-state resistance, I_L= 0.5A, each channel

T_j= 25°C

R_ON

mΩ

150

270

75

200

320

100

50

---

T_j= 125°C

two parallel channels, T_j= 25°C:¹⁾

four parallel channels, T_j= 25°C:¹⁾

38

Nominal load current

Device on PCB 38K/W, T_a= 85°C, T_j< 125°C

one channel:¹⁾I_L(NOM)

1.4

2.2

4.4

A

two parallel channels:¹⁾

four parallel channels:¹⁾

2)

Turn-on time to 90% V_OUT

R_L= 47Ω, V_Dx= 0 to 5V

t_on

t_off

64

89

1

120 µs

170

---

1)

Turn-off time to 10% V_OUT

R_L= 47Ω, V_Dx= 5 to 0V

Slew rate on 10 to 30% V_OUT

dV/dt_on

-dV/dt_off

2

V/µs

R_L= 47Ω, V_bb= 15V

Slew rate off 70 to 40% V_OUT

1

R_L= 47Ω, V_bb= 15V

1) not subject to production test, specified by design

2) The turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless

transformer in normal operating mode. During a failure on the coreless transformer transmission turn-on or turn-off time

can increase by up to 50µs.

4.4

Operating Parameters

Parameter

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC

3.0...5.5V, unless otherwise specified

=

min.

typ.

max.

Common mode transient immunity¹⁾

Magnetic field immunity¹⁾

dV_ISO/dt

H_IM

-25

-

25

kV/µs DV_ISO= 500V

A/m IEC61000-4-8

100

Datasheet

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ISOFACE^TM

ISO1H816G

Electrical Characteristics

Voltage domain V_bbOperating voltage

V_bb

11

7

35

10.5

11

V

---

0.5

1

(Output interface)

Undervoltage shutdown

V_bb(under)

V_{bb(u_rst)}

∆V_bb(under)

I_bb(uvlo)

I_GNDL

Undervoltage restart

Undervoltage hysteresis

Undervoltage current

Operating current

---

2.5

14

mA

V_bb< 7V

10

All Channels

ON - no load

Leakage output current

I_L(off)

5

30

µA

V

---

(included in I_bb(off)

V_Dx= low, each channel

Voltage domain V_CCOperating voltage

)

V_CC

3.0

2.5

---

5.5

2.9

3

---

0.1

1

(Input interface)

Undervoltage shutdown

Undervoltage restart

Undervoltage hysteresis

Undervoltage current

Operating current

V_CC(under)

V_{CC(u_rst)}

∆V_CC(under)

I_CC(uvlo)

I_CC(on)

---

2

mA

V_cc< 2.5V

4.5

6

1) not subject to production test

Datasheet

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ISOFACE^TM

ISO1H816G

Electrical Characteristics

4.5

Output Protection Functions

Parameter¹⁾

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC=3.0...5.5V,

unless otherwise specified

min.

typ.

max.

Initial peak short circuit current limit, each channel I_L(SCp)

T_j= -25°C, V_bb= 30V, t_m= 700µs

T_j= 25°C

A

4.5

---

1.4

---

3.0

---

T_j= 125°C

two parallel channels:³⁾

twice the current of one channel

four times the current of one channel

four parallel channels:³⁾

Repetitive short circuit current limit³⁾

I_L(SCr)

T_j= T_jt(see timing diagrams)

each channel:

2.2

---

two parallel channels:³⁾

four parallel channels:³⁾

Output clamp (inductive load switch off)

V_ON(CL)

47

53

60

V

at V_OUT= V_bb- V_ON(CL)

Overvoltage protection

V_bb(AZ)

T_jt

47

135

---

10

---

Thermal overload trip temperature^{2) 3)}

Thermal hysteresis³⁾

°C

K

∆T_jt

1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet.

Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuos

repetitive operation.

2) Higher operating temperature at normal function for each channel available

3) not subject to production test, specified by design

4.6

Diagnostic Characteristics at pin DIAG

Parameter

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC=3.0...5.5V,

unless otherwise specified

min.

typ.

max.

Common diagnostic sink current

(overtemperature of any channel) T_j= 135°C

I_diagsink

5

mA V_DIAGON< 0.25 x

VCC

Common diagnostic source current

I_diagsource

100

µA

Datasheet

15

Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Electrical Characteristics

4.7

Input Interface

Parameter

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC= 3.0...5.5V,

unless otherwise specified

min.

typ.

max.

Input low state voltage

(SI, DIS, CS, SCLK)

V_IL

V_IH

-0.3

0.3 x

V_CC

V

---

Input high state voltage

(SI, DIS, CS, SCLK)

0.7 x

V_CC

V_CC+

---

0.3

Input voltage hysteresis

(SI, DIS, CS, SCLK)

V_IHys

V_OL

V_OH

I_Idown

-I_Iup

t_DIS

100

mV

Output low state voltage

(SO)

-0.3

0.25 x V

V_CC

C_L< 50pF,

R_L> 10kΩ

---

Output high state voltage

(SO)

0.75 x

V_CC

0.3

+

Input pull down current

(SI , DIS)

100

85

µA

Input pull up current

(CS, SCLK)

Output disable time (transition DIS to logic low)¹⁾²⁾

Normal operation

Turn-off time to 10% V_OUT

R_L= 47Ω

170 µs

---

Output disable time (transition DIS to logic low)¹⁾²⁾³⁾

Disturbed operation

t_DIS

230

---

Turn-off time to 10% V_OUT

R_L= 47Ω

1) The time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer.

2) If Pin DIS is set to low the outputs are set to low; after DIS set to high a new write cycle is necessary to set the output again.

3) The parameter is not subject to production test - verified by design/characterization

Datasheet

16

Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Electrical Characteristics

4.8

SPI Timing

Parameter

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC= 3.0...5.5V,

unless otherwise specified

min.

typ.

max.

Serial clock frequency

f_SCLK

t_p(SLCK)

t_CSS

DC

50

5

20

---

MHz

---

Serial clock period (1/fclk)

ns

CS Setup time (falling edge of CS to falling edge of

SCLK)

CS Hold time (rising edge of SCLK to rising edge

of CS)

t_CSH

t_CSD

t_SU

10

6

---

CS Disable time (CS high time between two

accesses)

Data setup time (required time SI to rising edge of

SCLK)

Data hold time (falling edge of SCLK to SI)

t_HD

6

SO Output valid time

CL = 50pF

t_VALID

20

---

SO Output disable time

t_SODIS

4.9

Reverse Voltage

Parameter

Symbol

Limit Values

Unit Test Condition

at T_j= -25 ... 125°C, V_bb=15...30V, V_CC= 3.0...5.5V,

unless otherwise specified

min.

typ.

max.

Reverse voltage¹⁾²⁾

-V_bb

V

R_GND= 0 Ω

R_GND= 150 Ω

1

45

---

Diode forward on voltage

-V_ON

IF = 1.25A, V_Dx= low, each channel

1.2

---

1) defined by P_tot

2) not subject to production test, specified by design

Datasheet

17

Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Electrical Characteristics

4.10

Isolation and Safety-Related Specification

Parameter

Value

Unit

V_AC

V

Conditions

1 - minute duration¹⁾

5s acc. DIN EN60664-1 ¹⁾

shortest distance through air.

shortest distance path along body.

Rated dielectric isolation voltage V_ISO

Short term temporary overvoltage

Minimum external air gap (clearance)

Minimum external tracking (creepage)

Minimum Internal Gap

500

1250

2.6

mm

2.6

0.01

Insulation distance through

insulation

1) not subject to production test, verified by characterization; Production Test with 1100V, 100ms duration

4.11

Reliability

For Qualification Report please contact your local Infineon Technologies office!

Datasheet

18

Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Electrical Characteristics

Datasheet

19

Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Electrical Characteristics

Datasheet

20

Version 2.0, 2009-07-28

ISOFACE^TM

ISO1H816G

Package Outlines

5

Package Outlines

1)

PG-DSO-36

±0.15

11

B

(Plastic Dual Small

Outline Package)

2.8

±0.1

1.1

±0.1

15.74

6.3

(Heatslug)

Heatslug

0.65

0.25 ^+0.13

0.1 C

(Mold)

±0.15

0.95

36x

0.25 A B C

M

±0.3

14.2

0.25 B

Bottom View

36

19

36

Index Marking

Heatslug

1

18

1

10

13.7 _-0.2

(Metal)

1 x 45˚

1)

±0.1

15.9

A

(Mold)

¹⁾Does not include plastic or metal protrusion of 0.15 max. per side

gps09181_1

Figure 14 PG-DSO-36

Datasheet

21

Version 2.0, 2009-07-28

Total Quality Management

Qualität hat für uns eine umfassende Quality takes on an all encompassing

Bedeutung. Wir wollen allen Ihren significance at Semiconductor Group.

Ansprüchen in der bestmöglichen For us it means living up to each and

Weise gerecht werden. Es geht uns every one of your demands in the best

also nicht nur um die Produktqualität – possible way. So we are not only

unsere

Anstrengungen

gelten concerned with product quality. We

gleichermaßen der Lieferqualität und direct our efforts equally at quality of

Logistik, dem Service und Support supply and logistics, service and

sowie allen sonstigen Beratungs- und support, as well as all the other ways in

Betreuungsleistungen.

which we advise and attend to you.

Part of this is the very special attitude of

our staff. Total Quality in thought and

deed, towards co-workers, suppliers

and you, our customer. Our guideline is

“do everything with zero defects”, in an

open manner that is demonstrated

beyond your immediate workplace, and

to constantly improve.

Dazu gehört eine

bestimmte

Geisteshaltung unserer Mitarbeiter.

Total Quality im Denken und Handeln

gegenüber Kollegen, Lieferanten und

Ihnen, unserem Kunden. Unsere

Leitlinie ist jede Aufgabe mit „Null

Fehlern“ zu lösen – in offener

Sichtweise auch über den eigenen

Arbeitsplatz hinaus – und uns ständig

zu verbessern.

Throughout the corporation we also

think in terms of Time Optimized

Processes (top), greater speed on our

part to give you that decisive

competitive edge.

Unternehmensweit orientieren wir uns

dabei auch an „top“ (Time Optimized

Processes), um Ihnen durch größere

Schnelligkeit den entscheidenden

Wettbewerbsvorsprung zu verschaffen.

Give us the chance to prove the best of

performance through the best of quality

– you will be convinced.

Geben Sie uns die Chance, hohe

Leistung durch umfassende Qualität zu

beweisen.

Wir werden Sie überzeugen.

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	ISO1H816G
厂家：	Infineon
描述：	Coreless Transformer Isolated Digital Output 8 Channel 1.2A High-Side Switch 空芯变压器隔离数字量输出通道8 1.2A高边开关变压器外围驱动器驱动程序和接口开关接口集成电路光电二极管 PC
文件：	总22页 (文件大小：1095K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISO1H816G [INFINEON]

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