ISO2H823V2.5_技术文档

ISOFACE™

ISO2H823V2.5

Galvanic Isolated 8 Channel High-Side Switch

Datasheet

Revision 2.0, 2015-02-12

Power Management & Multimarket

Edition 2015-02-12

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact the nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in

question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

ISOFACE™

ISO2H823V2.5

Revision History

Page or Item

Subjects (major changes since previous revision)

Revision 2.0, 2015-02-12

Trademarks of Infineon Technologies AG

AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,

CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,

EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,

ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,

POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,

ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,

thinQ!™, TRENCHSTOP™, TriCore™.

Other Trademarks

Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,

PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR

development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,

FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.

FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of

Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data

Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of

MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics

Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA

MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of

OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF

Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™

of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.

TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™

of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas

Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes

Zetex Limited.

Last Trademarks Update 2011-11-11

Datasheet

3

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1

2

2.1

2.1.1

2.1.2

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Pins of Power Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Pins of Serial and Parallel Logic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4

4.1

4.2

4.2.1

4.2.1.1

4.2.2

4.2.2.1

4.2.2.2

4.2.2.3

4.2.3

4.2.4

4.2.5

4.2.5.1

4.2.5.2

4.2.6

4.2.7

4.2.8

4.2.9

4.2.9.1

4.2.9.2

4.2.10

4.3

4.3.1

4.3.2

4.3.2.1

4.3.2.2

4.3.2.3

4.3.3

4.3.3.1

4.3.3.2

4.3.3.3

4.3.3.4

4.3.3.5

4.3.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Parallel Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Parallel Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Serial Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Daisy Chain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Cyclic Redundancy Check CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Common Error Indication Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Update of the Diagnostic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SYNC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SYNC-Signal for Drive-Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

SYNC-Signal for Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

ODIS Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

LEDGOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

OLOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

RESET (Hard and Soft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Resynchronization of CT-Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Output Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Protection Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Power Transistor Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Power Transistor Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Current Sense and Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Diagnostics in Inactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Diagnostics in Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Diagnostic Scenarios in Dependence of Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Global Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

LED Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LED Matrix on the Process Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LED Matrix on the uController Side (only in Serial Communication Mode) . . . . . . . . . . . . . . . . . 44

EMI-Robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3.4.1

4.3.4.2

4.4

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4

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

4.4.1

4.4.2

4.5

Burst Robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

RFCM-Robustness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.5.1

5

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Operating Conditions and Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Load Switching Capabilities and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Output Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Electrical Characteristics µController Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Isolation and Safety-Related Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6

µController Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.1

User Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7

Package : Outlines and Marking Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Datasheet

5

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

List of Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power PG-VQFN-70-2 (430 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Application with Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Application with Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Bus Configuration for Parallel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Timing by Parallel Read Access (e.g. GLERR Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Timing by Parallel Write Access (e.g. DRIVE Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Parallel Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10 Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11 Example SPI Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12 SPI Mode 0, MS0 = 0, MS1 = 0, Daisy Chain Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13 SPI Mode 1, MS0 = 1, MS1 = 0, Daisy Chain Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14 SPI Mode 2, MS0 = 0, MS1 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15 SPI Mode 3, MS0 = 1, MS1 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16 Connecting Two Devices for Daisy Chain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 17 Typical Timing Diagram of Daisy Chain Operation (Serial Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 18 SYNC Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19 Timing of Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 20 Examples of Application of Resynchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 21 Diagnostics Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 22 Start Up Procedure of the Power Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 23 LED Matrix connected to the Power Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 24 LED Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 25 LED Matrix connected to the uC-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 26 Burst-Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 27 RFCM-Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 28 Typ. On-State Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 29 Typ. On-State Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 30 Typical Initial Peak Short Circuit Current Limit vs T_j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 31 Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated. . . . . 61

Figure 32 Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated. . . . . 62

Figure 33 Maximum Allowable Inductive Switch Off Energy, Single Pulse for Each Channel . . . . . . . . . . . . 62

Figure 34 Typ. Transient Thermal Impedance 1s0p. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 35 Typ. Transient Thermal Impedance 2s2p no vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 36 Typ. Transient Thermal Impedance 2s2p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 37 Sticky Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 38 PG-VQFN-70-2 (Plastic (Green) Very Thin Profile Quad Flat Non Leaded Package) . . . . . . . . . . 80

Figure 39 Marking Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Datasheet

6

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

List of Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin Configuration for LED-Application on the uC-Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bits composing the ERR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Continuous Mode (GLCFG : FRZSC = 0), Disturbance (to Channel 0) Scenario . . . . . . . . . . . . . 30

Isochronous Mode (GLCFG : FRZSC = 1 (RESYN = 0)), Channel 0 Disturbed, Scenarios . . . . . 31

Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Filter Time in Inactive Mode for OLIx and SCVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Filter Time in Active Mode for OLAx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Occurence of Diagnostics during the Disturbance : Short-Circuit-to-VBB . . . . . . . . . . . . . . . . . . . 39

Occurence of Diagnostics during the Disturbance : Wirebreak . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Electrical Characteristics of the Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Load Switching Capabilities and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Output Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Setting at the Configuration Pin (CLKADJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Error Pins (ERR, CRCERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Logical Pins (RD, WR, ALE, MS0/1, CS, AD7: AD0, SCLK, SDO, SDI, SEL, SYNC, ODIS) . . . 54

SYNC-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

RESYNCH-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

ODIS, ALE/RST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Channel Specific Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Isolation and Safety-Related Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Register Access Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Diagnostics Registers for Channel 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 26

Table 27

Table 28

Table 29

Table 30

Datasheet

7

Revision 2.0, 2015-02-12

Galvanic Isolated 8 Channel High-Side Switch

ISO2H823V2.5

1

Overview

Infineon Technologies 2nd generation ISOFACE™ 8-channel high-side

driver IC ISO2H823V2.5 offers integrated 2.5kV galvanic isolation, thus

meets the IEC 61131-2 requirements for reinforced isolation.

Concurrently, the ISO2H823V2.5 sets a new standard for system-level

diagnostics. Each of the 8 channels is equipped with 5-fold diagnostic

monitoring capabilities: Open Load (Active Mode - Driver On and Inactive

Mode - Driver Off) , Short-to-Vbb, Overcurrent (= Short-to-GND),

Overtemperature.

With the ever increasing level of complexity and integration in industrial

control systems comprehensive diagnostic monitoring is highly valuable

in a vast range of industrial applications, both for preventive maintenance

as well as to shorten costly un-scheduled down-times

PG-VQFN-70-2

Product Highlights

•

2.5 kV Galvanic isolation integrated (UL508 & CSA22.2 certified)

Meets IEC 61131-2 requirements for reinforced isolation

8 - channel high-side switches of 0.6 A each

5 different types of diagnostic feedback for each channel

µController compatible 8-bit parallel/serial interface

12 mm x 12 mm PG-VQFN-70-2 package

•

Key Features

•

Interface 3.3V CMOS operation compatible

Parallel/Serial µC interface

High common mode transient immunity

Integrated Diagnostics:

– 5 different types for diagnostic feedback per output channel

– 5 types of diagnostic feedback on global level

Common output disable pin

•

Common error indication pin

Resynchronization to achieve a low-jitter switching on and off of high-side switches

Active output current limitation for short circuit protection

Reverse Output Voltage protection

Undervoltage shutdown with autorestart and hysteresis

Integrated clamping to switch inductive loads up to 150 mJ energy per channel

Thermal shutdown and diagnostics per channel with auto-restart

V

_BBrange from 11 V to 35 V designed for 24 V systems

Type

Package

ISO2H823V2.5

PG-VQFN-70-2

Datasheet

8

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Overview

•

ESD protection

RoHS compliant

Typical Application

•

Isolated switch for industrial applications:

PLC, distributed control systems, industial PCs, robotics, etc.

All types of resistive, inductive and capacitive loads

µController compatible power switch for 24 V DC applications

Driver for solenoid, relays and resistive loads

•

Description

The ISO2H823V2.5 is a galvanically isolated 8-bit data interface in PG-VQFN-70-2 package that provides 8 fully

protected high-side power switches that are able to handle currents up to 730 mA per channel.

An 8-bit parallel µController compatible interface or a serial SPI-interface allows to connect the IC directly to a

µController system. The input interface supports also a direct control mode for writing driver information and is

designed to operate with 3.3 V CMOS compatible levels.

The data transfer from input to output side is realized by the integrated Coreless Transformer Technology.

This product is the second generation of isolated 8 channel digital output device (ISO2H823V2.5) and provides a

robust integrated diagnosis for switches with low R_DSonas well as an upgraded µController interface.

uC_chip

power chip

VCC

VBB

only

VBB

in

IADJ

serial

mode,

shared

pins

Configuration

Register

OLADJ

I

n

t

e

r

OUT0

OUT1

OUT2

/ERR

Drive

Register

OUT3

OUT4

/ODIS

f

OUT5

OUT6

OUT7

µC

Control

Protection

Diagnostic Unit

a

c

e

SYNC

/CS

e.g.

XMCxxxx

parallel

or serial

interface

LEDx0

LEDx1

LEDx2

LEDy0

LEDy1

LEDy2

Diagnostic

Registers

Logic

CLKADJ

GND

ISO2H823V2

VDDIO

VCORE

GNDBB

Figure 1

Typical Application

Infineon Ordering Code :

SP001225470

Datasheet

9

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Pin Configuration and Functionality

2

Pin Configuration and Functionality

35 34 33

32 31 30 29 28 27 26 25 24 23

36

22

21

20

19

18

17

16

15

GNDBB

VBB

SEL

VCC

37

38

39

40

41

42

43

VBB

CLKADJ

GND

OUT1

VBB

/ODIS

SYNC

OUT2

/WR

ALE / RST

OUT3

VBB

14

13

12

11

10

9

44

45

46

47

48

49

50

51

52

53

/RD / MS0

MS1

GND

VBB

GND

OUT4

OUT5

VBB

/CS

AD0 / SDI

AD1

8

7

AD2

6

AD3

exposed pad to GND

OUT6

5

AD4 / /CRCERR

4

OUT6

54

55

56

57

AD 5 / SCLK

AD6

creepage

distance

exposed pad to GNDBB

3

VBB

AD7 / SDO

/ERR

2

1

n.c. = Not Connected

GNDBB

58 59 60

61 62 63 64 65 66 67 68 69 70

02/09/2015

PG-VQFN-70-2 - pinout_IFX.vsd

Figure 2

Power PG-VQFN-70-2 (430 mil)

Datasheet

10

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Pin Configuration and Functionality

Table 1

Pin Configuration

Pin Parallel Interface Mode

Serial Interface Mode

Symbol

Ctrl Type Function

Symbol

Ctrl Type Function

1)

2)

top side pins

1

2

GNDBB

VBB

A

Output Stage Ground

GNDBB

VBB

Output Stage Positive

Supply

3

VBB

A

Output Stage Positive

Supply

VBB

4

5

6

OUT6

VBB

A

Switch Output 6

OUT6

VBB

Output Stage Positive

Supply

7

OUT5

OUT4

VBB

A

Switch Output 5

Switch Output 4

OUT5

OUT4

VBB

8

9

10

11

Output Stage Positive

Supply

12

VBB

A

Output Stage Positive

Supply

VBB

13

14

15

16

17

OUT3

OUT2

VBB

A

Switch Output 3

Switch Output 2

OUT3

OUT2

VBB

Output Stage Positive

Supply

18

19

20

OUT1

VBB

A

Switch Output 1

OUT1

VBB

Output Stage Positive

Supply

21

VBB

A

Output Stage Positive

Supply

VBB

22

23

24

25

26

GNDBB

n.c.

Output Stage Ground

GNDBB

n.c.

not connected

OUT0

VBB

A

Switch Output 0

OUT0

VBB

Switch Output 0

Output Stage Positive

Supply, Supply of Reference

Voltages

27

GNDBB

A

Output Stage Ground

GNDBB

Datasheet

11

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Pin Configuration and Functionality

Table 1

Pin Configuration (cont’d)

Pin Parallel Interface Mode

Serial Interface Mode

Symbol

Ctrl Type Function

Symbol

Ctrl Type Function

1)

2)

28

29

30

31

32

OLADJ

IADJ

A

Open Load Adjust

OLADJ

IADJ

Current Reference Adjust

CT Blocking Capacitor

Digital Core Supply

VDDIO

VCORE

GNDBB

VDDIO

VCORE

GNDBB

Output Stage Ground

gap used for creepage distance

33

34

35

36

37

38

39

40

41

GND

SEL

A

Logic Ground

GND

A

I

PD

A

Serial / Parallel Mode Select SEL

Positive 3.3 V logic supply VCC

Clock Frequency Adjustment CLKADJ

VCC

CLKADJ

GND

ODIS

SYNC

A

Logic Ground

GND

I

PD

PU

Output Disable

ODIS

SYNC

Synchronize and Freeze

Diagnostics

42

43

WR

I

PU

PD

Data Write Input

n.c.

high impedance “Z”

ALE/RST I

Address Latch Enable /

Reset

RST

I

PD

Reset

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

RD

I

PU

Data Read Input

not connected

Logic Ground

Chip Select

MS0

MS1

GND

CS

I

PD

SPI Mode Select bit 0

SPI Mode Select bit 1

n.c.

GND

CS

A

I

PU

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ERR

GND

IO PPZ Addr-Data in/output bit0

IO PPZ Addr-Data in/output bit1

IO PPZ Addr-Data in/output bit2

IO PPZ Addr-Data in/output bit3

IO PPZ Addr-Data in/output bit4

IO PPZ Addr-Data in/output bit5

IO PPZ Addr-Data in/output bit6

IO PPZ Addr-Data in/output bit7

SDI

I

PD

SPI Data input

n.c.

high impedance “Z”

CRC Error output

SPI Shift Clock input

high impedance “Z”

n.c.

CRCERR

SCLK

n.c.

OD PU

I

PD

SDO

ERR

GND

O

PPZ SPI Data Output

OD PU

Fault indication

Logic Ground

A

gap used for creepage distance

Datasheet

12

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Pin Configuration and Functionality

Table 1

Pin Configuration (cont’d)

Pin Parallel Interface Mode

Serial Interface Mode

Symbol

Ctrl Type Function

Symbol

Ctrl Type Function

1)

2)

61

62

63

64

65

66

67

68

69

70

GNDBB

LEDX0

LEDX1

LEDX2

LEDY0

LEDY1

LEDY2

OUT7

A

Output Stage Ground

LED Output Row 0

LED Output Row 1

LED Output Row 2

LED Output Column 0

LED Output Column 1

LED Output Column 2

Switch Output 7

GNDBB

LEDX0

LEDX1

LEDX2

LEDY0

LEDY1

LEDY2

OUT7

Switch Output 7

OUT7

n.c.

not connected

n.c.

not connected

1) Direction of the digital pins : I = input, O = output, IO = Input/Output

2) Type of the pin: A = analog, OD = Open-Drain, PU = internal Pull-Up resistor, PD = internal Pull-Down resistor,

PPZ = Push-Pull pin with High-Impedance functionality

In case of serial mode six pins can be used to drive a LED-matrix on the uC-side (Table 2). For this purpose the

bit LEDON in register GLCFG has to be set to “1”.

Table 2

Pin Configuration for LED-Application on the uC-Side

Pin Serial Interface Mode

Symbol

Ctrl Type Function

top side pins

55

52

51

42

43

50

AD6

OD

LEDR0

LEDR1

LEDR2

LEDC0

LEDC1

LEDC2

AD3

AD2

WR

ALE/RST

AD1

Datasheet

13

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Pin Configuration and Functionality

2.1

Pin Functionality

This section describes the pins of the µController Interface as well as the Process Interface.

2.1.1

Pins of Power Interface

VBB (Positive supply 11-35 V output stage)

V_BBsupplies the output stage. An external circuitry for reverse polarity protection is required (see Electrical

Characteristics).

A ceramic capacitor of minimum 2.2 µF must be connected between VBB and GNDBB.

GNDBB (Ground for VBB domain)

This pin acts as the ground reference for the output stage that is supplied by V_BB.

OUT0... OUT7 (Output channel 0 ... 7)

Due to EMI-requirements (Radio-Frequency-Common-Mode and burst-application)

a

capacitor of

min.10 nF (+10%, recommended value 12 nF + 10%) for each output pin has to be connected to GNDBB.

LEDX0... LEDX2 (LED Row output channel 0 ... 2)

Low side switches

LEDY0... LEDY2 (LED Column output channel 0 ... 2)

High side drivers

IADJ (Current Adjust)

Reference current input, must be connected to GNDBB through a reference resistor of typ. 6.81 KΩ (E96 series).

The DC-level V_IADJis 1.215 V.

OLADJ (Open Load Adjust)

The current for the Open load detection can be adjusted by connecting a resistor between this pin and GNDBB

(from the E96 series : 25 kΩ - 2.3 kΩ).The DC-level V_OLADJis 1.215 V.

VDDIO (3.3 V Supply Blocking Capacitor)

A 1 µF ceramic capacitor must be connected between VDDIO and GNDBB.

VCORE (Blocking Capacitor for 1.5 V Digital Core)

A 470 nF ceramic capacitor must be connected between VCORE and GNDBB.

2.1.2

Pins of Serial and Parallel Logic Interface

Some pins are common for both interface types, some others are specific for the parallel or serial access.

VCC (Positive 3.3 V logic supply)

V_CCsupplies the output interface that is electrically isolated from the output power stage. The interface can be

supplied with 3.3 V. A ceramic capacitor of minimum 2.2 µF must be connected between VCC and GND.

GND (Ground for VCC domain)

This pin acts as the ground reference for the uC-interface that is supplied by V_CC.

CLKADJ (Clock Adjust)

A high precision resistor of 10 KΩ has to be connected between CLKADJ and GND. The DC-level V_CLKADJis 0.5 V.

ERR (Fault Indication)

The low active ERR signal contains the OR-wired diagnostic information depending on choosen serial or parallel

mode (VBB undervoltage or missing voltage detection, the internal data transmission failure detection unit and the

fault(s) of the output switch).The output pin ERR provides an open drain functionality.This pin has an internal Pull-

Up resistor. In normal operation the signal ERR is high.

Datasheet

14

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Pin Configuration and Functionality

ODIS (Output Disable)

The low active ODIS signal immediately switches off the output channels OUT0-OUT7. This pin has an internal

Pull-Down resistor. In normal operation the signal ODIS is high. Setting ODIS to Low clears the DRIVE register as

well. The minimum width of the ODIS signal is 5 µs.

SEL (Serial or Parallel Mode Select)

When this pin is in a logic Low state, the IC operates in Parallel Mode. For Serial Mode operation the pin has to

be pulled into logic High state. During Start Up the IC is operating in Parallel Mode. This pin has an internal Pull-

Down resistor and a 200 ns blanking time¹⁾.

SYNC

In isochronous mode (clock-sync-mode) the transfer of the latched output data register into the output-stages is

controlled by the SYNC signal. When the SYNC-signal is in low state, the output-stage won’t be updated any

longer, the last value is frozen. With the rising edge of SYNC the information of the latched output data registers

will be transferred to the output stages. It can be choosen by a configuration bit whether all the channel diagnostic

bits will be latched into the DIAG channel register every data cycle or only when the SYNC-signal is in high state.

In the last case when the SYNC-signal is in low state, the DIAG channel register wouldn’t be updated any longer,

the last value would be frozen. SYNC is also used for resynchronization of the data transmission with the target

to achieve a low jitter. This pin has an internal Pull-Up resistor and a 20 ns blanking time¹⁾.

CS (Chip Select)

When this pin is in a logic Low state, the IC interface is enabled and data can be transferred. This pin has an

internal Pull-Up resistor and a 20 ns blanking time¹⁾.

When the CS pin is held Low whereas the ALE pin is High for at least 100 µs, the device is reset.

The following pins are provided in the parallel interface mode

AD7:AD0 (AddressData input / output bit7 ... bit0)

The pins AD0 .. AD7 are the bidirectional input / outputs for data write and read. Depending on the state of the

ALE pin and the AD7 pin, register addresses or data can be transferred between the internal registers and e.g.

the micro-controller. By connecting CS and WR and ALE/RST pins to GND and RD to VCC, the parallel direct

mode is activated.

WR (Write )

By pulling this pin down, a write transaction is initiated on the AddressData bus and the data has to be valid on

the rising edge of WR. The AD7-bit of the register address has to be set to ‘1’. This pin has an internal Pull-Up

resistor and a 20 ns blanking time¹⁾.

RD (Read )

By pulling this pin down, a read transaction is initiated on the AddressData bus and the data becomes valid on the

rising edge of RD. The AD7-bit of the register address has to be set to ‘0’. This pin has an internal Pull-Up resistor

and a 20 ns blanking time¹⁾.

ALE (Address Latch Enable)/RST

The pin ALE is used to select between address (ALE is in a logic High state) or data (ALE is in a logic Low state).

Furthermore, a read or write transaction can be selected with the RD and WR pin. When ALE is pulled high,

address is transferred and latched over the bit AD0 to AD7. During the time interval where ALE = High RD or WR

has to be pulled to High. During the Low State of ALE all transactions hit the same address. This pin has an internal

Pull-Down resistor and a 20 ns blanking time¹⁾. For the reset-function see comment under the item: CS.

1) the signal must be stable for the duration of the blanking time before it is accepted as valid

Datasheet

15

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Pin Configuration and Functionality

The following pins are provided in the serial interface mode

MS0, MS1 (Serial Mode Select)

By driving these pins to Logic High or Low the Serial Interface Mode (number of bits - 8, 16, 24 - to be transferred,

CRC) can be selected. These pins have both an internal Pull-Down resistor and a 200 ns blanking time¹⁾.

SCLK (Serial Interface Shift Clock)

Input data are sampled with rising edge and output data are updated with the falling edge of this input clock signal.

This pin has an internal Pull-Down resistor and a 20 ns blanking time¹⁾.

SDI (Serial Interface Input Data)

SDI is put into a dedicated FIFO (clocked by SCLK) to program the DRIVE register and the internal address and

the write data. This pin has an internal Pull-Down resistor and a 20 ns blanking time¹⁾.

SDO (Serial Interface Data Output)

SDO provides the serial output data bits

CRCERR (CRC Error Output)

This pin is in a logic Low state when CRC errors or Shift-Clock errors are detected internally. This pin has an open

drain functionality and an internal Pull-Up resistor.

Datasheet

16

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Block Diagram

3

Block Diagram

The IC is divided into an uC_chip and into a power chip due to the galvanical isolation.The uC_chip contains the

uC-interface and the power chip the power switches.

uC_chip

power chip

SEL /ODIS

/ERR

VCC CLKADJ

VDDIO VCORE IADJ

VBB OLADJ VBB (x8)

/CS

AD0/SDI

AD1

DRV

DIAG

OSC

VCORE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

VDDIO

3.3V

BIAS

VREF

SPI

UVLO

BIAS

DRV

DIAG

OSC

BIAS

P

A

D

S

AD2

DRV

DIAG

RX TX CTRL

Timers

AD3

DRV

DIAG

AD4/

CRCERR

&

RX TX

CTRL

Registers &

Access Control

DRV

DIAG

IO

AD5/SCLK

AD6

C

R

T

L

DRV

DIAG

DIAG CTRL

Registers

AD7 / SDO

PARALLEL

LOGIC

DRV

DIAG

/WR

/RD

LED

Matrix

LED

Matrix

DRV

DIAG

Control

Unit

ALE

CHANNELS

LOGIC

AD1 /

ALE/RST /

/WR

LEDY2:0

MS1:0

GND

(x8)

LEDX2:0

GNDBB (x5)

SYNC

AD2 /

AD3 /

AD6

*)

Overall _Block _Diagram ._ISO2H823

*) : shared in serial mode

Figure 3

Block Diagram

Datasheet

17

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Block Diagram

uC_chip

power chip

VDDIO

PMU

OSC

3.3 V

1.5 V

VCORE

VBB

RXTX

CTRL

GNDBB

RXTX

CTRL

RST

IADJ

OLADJ

VCC

DRIVE Reg

Command

I

n

t

e

r

f

a

c

e

Drive Control &

Diagnostics

OUT0

Con-

.

Registers

.

/ERR

figuration

/ODIS

Registers

SYNC

/CS

….

OUTx

.

SEL

µC

.

Diagnostic_0

….

Drive Control &

Diagnostics

e.g.

XMC4xxx

OUT7

AD0,…,AD7,

/RD, /WR

L

o

g

i

Diagnostic_7

c

LEDx0

LEDx1

LEDx2

LEDy0

LEDy1

LEDy2

Error-

Registers

ALE/RST

CLKADJ

LED Matrix

RESYNCH

OSC

GND

ISO2H823V2

Figure 4

Application with Parallel Interface

uC_chip

power chip

VDDIO

AD6/LEDR0

only

PMU

3.3 V

1.5 V

AD3/LEDR1

in

OSC

VCORE

VBB

AD2/LEDR2

serial

/WR/LEDC0

LED Matrix

mode,

shared

pins

ALE/RST/LEDC1

AD1/LEDC2

GNDBB

use LED

exor

RST-

RXTX

CTRL

RST

RXTX

CTRL

IADJ

function

OLADJ

VCC

DRIVE Reg

I

n

t

e

r

Drive Control &

Diagnostics

Command

OUT0

Con-

.

Registers

.

/ERR

figuration

/ODIS

SYNC

/CS

Registers

f

a

c

e

….

OUTx

.

SEL

µC

.

Diagnostic_0

….

Drive Control &

Diagnostics

e.g.

XMCxxxx

OUT7

SDI

L

o

g

i

SDO

SCLK

Diagnostic_7

c

LEDx0

LEDx1

LEDx2

LEDy0

LEDy1

LEDy2

/CRCERR

MS0,MS1

CLKADJ

Error-

Registers

LED Matrix

RESYNCH

OSC

GND

ISO2H823V2

Figure 5

Application with Serial Interface

Datasheet

18

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ISOFACE™

ISO2H823V2.5

Functional Description

4

Functional Description

4.1

Introduction

The IC contains 2 galvanic isolated voltage domains that are independent from each other. The input interface

(µC-chip) is supplied at V_CCand the output stage (power chip) is supplied at V_BB. The different voltage domains

can be switched on at different time. The output stage is only enabled once the input stage enters a stable state.

The power chip generates out of V_BBtwo internal voltages V_DDIO= 3.3 V (+ 10 %) and V_CORE= 1.5 V (+ 10%)

which have to be buffered externally.

The ISOFACE ISO2H823V2.5 includes 8 high-side power switches that are controlled by means of the integrated

parallel/serial interface. The interface is 8-bit µController compatible. Furthermore a direct control mode can be

selected that allows the direct control of the outputs OUT0 … OUT7 (power chip) by means of the inputs AD0 …

AD7 (µC-chip) without any additional logic signal. The IC can replace 8 optocouplers and the 8 high-side switches

in conventional I/O-Applications as a galvanic isolation is implemented by means of the integrated coreless

transformer technology. The µController compatible interface allows a direct connection to the ports of a

microcontroller without the need for other components. Each of the 8 high-side power switches is protected against

overload, overtemperature and against overvoltage by an active zener clamp.

4.2

Microcontroller Interface

The microcontroller interface can be configured as a parallel or serial interface via the SEL pin.

4.2.1

Parallel Interface Mode

The ISO2H823V2.5 device contains a parallel interface that can be selected by pulling the SEL Pin to logic Low

state. The interface can be directly controlled by the µController output ports (see Figure 6). The output pins

AD7:AD0 are in state “Z” as long as CS=1, RD=1 and WR=1.

VCC

/CS

ALE

/WR

/RD

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

SEL

parallel _interface_iso2h823. vsd

Figure 6

Bus Configuration for Parallel Mode

Datasheet

19

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ISOFACE™

ISO2H823V2.5

Functional Description

The timing requirements for the parallel interface are shown in Figure 7 (Read), Figure 8 (Write) and Table 23.

/CS

t_CSD

t_{RD_su}

ALE

t_{ALE_high}

t_{RD_hd}

t_RDlow

t_RDhigh

t_{CS_ALE}

/RD

t_clrrdy

t_float

t_{AD_su}t_{AD_hd}

t_ADout

GLERR address (04h)

GLERR data

AD[7:0]

GLERR

00h

rd_timing_ifx - uc _parallel

Figure 7

Timing by Parallel Read Access (e.g. GLERR Register)

For a reading access to internal registers the MSB of the address register has to be set to “0”.

/CS

t_CSD

t_{WR_su}

ALE

t_{ALE_high}

t_WRlow

t_WRhigh

t_{WR_hd}

t_{CS_ALE}

/WR

t_lat

t_{AD_su}t_{AD_hd}

AD[7:0]

DRIVE address (80h)

DRIVE data (0Fh)

DRIVE data (0Ah)

0Fh

00h

DRIVE

00h

0Fh

OUT[7:0]

wr_timing_ifx - uc _parallel

Figure 8

Timing by Parallel Write Access (e.g. DRIVE Register)

For a writing access to internal registers the MSB of the address register has to be set to “1”.

Datasheet

20

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ISOFACE™

ISO2H823V2.5

Functional Description

4.2.1.1

Parallel Direct Mode

The parallel interface can be also used in a direct mode that allows direct changes of the output OUT0...OUT7 by

means of the corresponding inputs D0-D7 without additional logic signals. To activate the parallel direct mode CS,

WR and ALE pins have to be wired to ground and RD has to be wired to V_CCas shown in the Figure 9. Although

the diagnostics cannot be read in this operation mode, the faults as specified in Table 3 are still reported at the

ERR pin (volatile).

VCC

/CS

ALE

/WR

/RD

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

SEL

parallel _interface_direct_iso2h823.vsd

Figure 9

Parallel Direct Mode

The direct mode is intended to be an additional parallel mode which is invoked directly after reset. In this case

internal settings have already been realized (f.e. MSB of the address register is set to “1” ).

Datasheet

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ISOFACE™

ISO2H823V2.5

Functional Description

4.2.2

Serial Interface Mode

The ISO2H823V2.5 device contains a serial interface that can be activated by pulling the SEL pin to logic High

state. The interface can be directly controlled by the µController output ports. The output pin SDO is in state “Z”

as long as CS=1. Otherwise, the bits at the SDI input are sampled with the rising edge of SCLK and registered

into the input FIFO buffer of length dependent on the selected SPI-mode (8, 16, 24 bits, Figure 12, Figure 13,

Figure 14, Figure 15). With every falling edge of SCLK the bits to be read are provided serially to the pin SDO.

The timing requirements for the serial interface are shown in Figure 10 and in Table 24.

t_{SCLK_su}

inactive

/CS

active

t_CSD

t_SCLK

receive

SCLK

edge

transmit

edge

t_SUt_HD

t_CSH

SDI

MSB

LSB

t_{SCLK_valid}

LSB

t_{CS_valid}

MSB

t_float

SDO

timing_def - uc _spi

Figure 10 Serial Bus Timing

Several SPI topologies are supported: pure bus topology, daisy chain and any combinations (Figure 11). Of

course independent individual control with a dedicated SPI controller interfaces for each slave IC is possible, as

well.

SCLK

SDO

SCLK

MISO

SCLK

SDO

SDI

SCLK

MISO

SCLK

SDO

SCLK

MISO

SCLK

MOSI

A

B

C

D

A

B

C

D

A

B

C

D

A

B

C

D

SDI

/CS

SDI

/CS

SDI

/CS

MOSI

/CS

SCLK

SDO

SCLK

SDO

SDI

SCLK

SDO

SDI

/CS

SDI

/CS

SDI

/CS

MCU

or

ASIC

MCU

or

ASIC

MCU

or

ASIC

MCU

or

ASIC

SCLK

SDO

SCLK

SDO

SDI

SCLK

SDO

SDI

/CS

SDI

/CS

SCLK

SDO

SCLK

SDO

SDI

SCLK

SDO

SDI

/CS

SDI

/CS

SDI

/CS

spi_ topologies3.vsd

Figure 11 Example SPI Topologies

Datasheet

22

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Functional Description

4.2.2.1

SPI Modes

Four different SPI-modes can be distinguished (Figure 12 - Figure 15).

/CS

SCLK

MSB

LSB

DR0

DR7

DR6 DR5

DR4

DR3

DR2

DR1

SDI

Channel-Value (Drive Information )

MSB

LSB

CD7

CD6

CD5

CD4

CD3

CD2 CD1

CD0

SDO

Collective Diagnosis

uc_spi _mode0.vsd

Figure 12 SPI Mode 0, MS0 = 0, MS1 = 0, Daisy Chain Supported

/CS

SCLK

Bit15

MSB

Bit8

Bit7

Bit0

LSB

MSB

DR7

DR6 DR5

DR4 DR3

DR2 DR1

DR0

0

C4.

C3

C2

C1

C0

SDI

Channel-Values (Drive Information )

Checksum

SDO

CD7 CD6

CD5

CD4

CD3 CD2

CD1 CD0

UV

MV

CF

C4.

C3

C2

C1

C0

Collective Diagnosis

Diagnosis / Checksum

uc_spi_mode1.vsd

Figure 13 SPI Mode 1, MS0 = 1, MS1 = 0, Daisy Chain Supported

Datasheet

23

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Functional Description

/CS

SCLK

Bit15

MSB

Bit8

Bit7

Bit0

LSB

MSB

LSB

READ

R

A6

A5

A4

A3

A2

A1

A0

d.c.

D1

d.c.

SDI

Read=0

Register-Address (R/W)

Value : dont care

SDO

CD7 CD6

CD5

CD4

CD3

CD2

CD1 CD0

D7

D6

D5

D4

D3

D2

D0

Collective Diagnosis

Value (Read)

WRITE

Bit15

MSB

Bit8

Bit7

Bit0

LSB

MSB

LSB

W

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDI

Write=1

Register-Address (R/W)

Value (Write)

SDO

CD7 CD6

CD5

CD4

CD3 CD2 CD1

CD0

d.c.

Collective Diagnosis

uc_spi_mode2.vsd

Figure 14 SPI Mode 2, MS0 = 0, MS1 = 1

/CS

SCLK

Bit23

MSB

R

Bit16 Bit15

Bit8

Bit7

Bit0

READ

LSB

A0

MSB

0

LSB

0

MSB

0

LSB

A6

A5

A4

A3

A2

A1

0

C4

C3

C2

C1

C0

SDI

Read=0

Register -Address (R/W)

Value „Zero“ for CRC

Checksum

SDO

CD7 CD6

CD5

CD4

CD3

CD2 CD1 CD0

D7

D6

D5

D4

D3

D2

D1

D0

UV

MV

CF

C4

C3

C0

Collective Diagnosis

Value (Read )

Checksum / Diagnosis

WRITE

Bit23

MSB

Bit16 Bit15

Bit8

Bit7

Bit0

LSB

A0

MSB

D7

LSB

MSB

LSB

W

A6

A5

A4

A3

A2

A1

D6

D5

D4

D3

D2

D1

D0

0

C4

C3

C2

C1

C0

SDI

Write=1

Register -Address (R/W)

Value (Write)

Checksum

SDO

CD7 CD6

CD5

CD4

CD3

CD2 CD1 CD0

d.c.

UV

MV

CF

C4

C3

C2

C0

Collective Diagnosis

Checksum / Diagnosis

uc_spi_mode3.vsd

Figure 15 SPI Mode 3, MS0 = 1, MS1 = 1

Datasheet

24

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Functional Description

4.2.2.2

Daisy Chain Mode

Up to 4 devices can be connected together as shown in the Figure 16 to operate in the daisy chain mode. Serial

modes 0 and 1 can be operated in daisy chain mode. In this case, the SDO output of one device is directly

connected to the SDI input of the next device. The SPI chain has to be connected to the µC or Bus ASIC (MOSI,

MISO and common SCLK and CS signals). If the received SCLK pulses are not fulfilling the modulo(8)-condition

the CRCERR pin will be activated.

In the serial mode 1 the CRC-generation has to be reset after 16 SCLK-cycles. At the rising edge of CS each

connected daisy-chain-device checks its related 16 bit-stream concerning CRC-consistency.

MISO

SDO

Device A

SDI

SCLK

/CS

SDO

Device B

MOSI

SCLK

/CS

SDI

SCLK

/CS

daisy _connect - uc_spi

Figure 16 Connecting Two Devices for Daisy Chain Mode

The data shifted in the first device SDI input is shifted out at the SDO output after the first byte for the serial mode 0

(after the second byte for the mode 1) while CS remains Low as shown in the Figure 17.

/CS

SCLK

MOSI

=SDI_B

DR7_A

DR6_A

DR5_A

CD5_B

CD5_A

DR4_A

DR3_A

CD3_B

DR2_A

CD2_B

CD2_A

DR1_A

CD1_B

CD1_A

DR0_A

DR7_B

DR7_A

CD7_B

DR6_B

DR5_B

DR4_B

DR3_B

DR2_B

DR1_B

DR0_B

DRIVE A

DRIVE B

SDO_B

=SDI_A

CD7_B

CD6_B

CD4_B

CD0_B

DR6_A

DR5_A

DR4_A

DR3_A

DR2_A

DR1_A

DR0_A

COLDIAG B

DRIVE A

MISO

CD7_A

CD6_A

CD4_A

CD3_A

CD0_A

CD6_B

CD5_B

CD4_B

CD3_B

CD2_B

CD1_B

CD0_B

=SDO_A

COLDIAG A

COLDIAG B

daisy_mode0_timing - uc_spi

SDO_A

SDI_A

SDO_B

SDI_B

MISO

MOSI

Device A

Device B

Figure 17 Typical Timing Diagram of Daisy Chain Operation (Serial Mode 0)

Datasheet 25

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Functional Description

4.2.2.3

Cyclic Redundancy Check CRC

To detect errors inside SPI data transmission two SPI-Modes are provided with integrated Cyclic Redundancy

Check.

The 5-Bit-CRC checksum will be calculated with the polynom X⁵+X⁴+X²+1. The bit length used for the calculation

is 11 bits for SPI-mode 1 and 19 bits for SPI-mode 3. The internal CRC-working register is loaded with “11111”

before start of the CRC-calculation.

The SPI-mode 1 supports only the write procedure for the DRIVE register (SPI-mode 1, MS1, MS0 = 01). Eight

bits of drive-information plus 3 dummy bits and the related CRC-information (5 bits based on the fed-in 11 bits)

are delivered to the CRC-engine. At the same time the COLDIAG-information in combination with the UV,MV,CF-

bits and the related CRC-information (based on these 11bits: COLDIAG, UV,MV,CF) are fed out of SDO. The bit

stream format is shown in Figure 13.

SPI-mode 3 provides register based access to the ISO2H823V2.5 with implemented CRC. The bit stream for a

write access to a register consists of the register address (8 bits), register data (8 bits), 3 dummy bits and the CRC

signature (5 bits) as shown in Figure 15. The total bitstream is fed into the CRC-input engines and processed

according to the underlying CRC-algorithm serially. At the same time the COLDIAG-information in combination

with the UV,MV,CF-bits and the related CRC-information (based on these 19 bits: COLDIAG, 8 dummy

bits,UV,MV,CF) are fed out of SDO.

The bit stream for a read access to a register consists of the register address (8 bits), 11 dummy bits and the CRC

signature (5 bits) as shown in Figure 15.The total bitstream is fed into the CRC-input engines and processed

according to the underlying CRC-algorithm serially. At the same time the COLDIAG-information, register data in

combination with the UV,MV,CF-bits and the related CRC-information (based on these 19 bits: COLDIAG,8 bits

register data, UV,MV,CF) are fed out of SDO.

After processing the 24 in-bits (including the CRC-signature) the result of the CRC-algorithm processing has to be

zero. In the case of another result different from zero the delivered signature is not consistent with the delivered

bit stream. This will be indicated by driving the CRCERR Pin to Low.

In both cases (SPI-mode 1 and SPI-mode 3) the status of the CRCERR pin is evaluated not at the end of the bit

sequence but with rising edge of CS. The procedure is consistent with the daisy-chain application where each

partner of the daisy chain checks its own contribution with the rising edge of CS when it is confirmed that the chain

is completely filled.

CRCERR reflects both the modulo-8-condition of the number of SCLK-signals and the correctness of the CRC-

signature. Both kinds of information are evaluated only during CS is Low and reported with the rising edge of CS.

Therefore it is assured that non-active ICs (CS = High) does not report a CRCERR = Low signal in case of toggling

of SCLK.

The signal CRCERR has an internal pull-up-resistor of 50 kΩ. When releasing CRCERR the internal pull-up

resistor determines the rise time, which is about 3 µs. It is possible to reduce the rise time to around 1 µs by adding

an external pull-up resistor of 10kΩ at the CRCERR pin.

Datasheet

26

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Functional Description

4.2.3

Common Error Indication Output

The dedicated ERR pin signalizes a common fault. This low-active pin has an open drain functionality with a pull-

up resistor.

Depending on the µController-interface mode in use, several internal status signals are OR-wired to drive the ERR

pin:

•

In direct mode, the OTC flag (LEDGx-bit-field of CT-transmission, OR-wired, volatile) and the volatile W4P-

information are routed to the ERR pin.

•

The output stage undervoltage (UV) and missing voltage (MV) of the power-chip which are transmitted via the

integrated coreless transformer are provided at the ERR pin.

•

The internal data transmission error (TE) over the galvanic isolation is available as well at the ERR pin.

The signal Wait-for-Power chip (W4P) is also provided. It detects that a continuous transmission error over a

longer time has occurred e.g. when the process side is not supplied properly and that no diagnostic data are

received on the µController-interface side.

•

The common fault error signal (CF) is routed out to the ERR pin in parallel mode. This signal is the OR-

combination of the COLDIAG register bits (sticky).

CF is not routed out to the ERR pin in any serial mode. In serial modes 1 and 3 the CF-bit is contained in the

serial telegram

The Table 3 provides the overview of the signals provided at the ERR pin and the behaviour of the bits used. The

prefix “S” specifies the bits as sticky.

During UVLO, all status signals and register bits are reset. The flags UV, MV, TE and W4P have a reset value of

1, so that by default these errors are active. As a consequence after power-up the ERR pin is by default driven

Low. The ERR pin returns to High logic level once all the signals OR-wired at this pin are Low i.e. once all the fault

conditions are not detected anymore and the bits have been cleared. This behaviour requires the external

controller to read the GLERR and INTERR to “clear” the ERR pin (except in parallel direct mode where the error

bit is simply OTC of type: volatile bit generated by oring the volatile gated-LEDGx-information of each channel and

W4P ). In some operation modes the update and the clearing of the status bits are done automatically after every

access (serial mode 0 and 1). For the other operation modes, the error bits need to be read with direct addressing

to be updated and cleared (parallel mode and serial modes 2,3).

The ERR signal differs between serial modes and parallel modes since in serial modes 1 and 3 the CF bit is

already shifted out when CRC is used. The serial or parallel mode is selected with the SEL signal whereas the

serial submodes are controlled with the SPI_MODE 2-bit signal.

Table 3

Bits composing the ERR signal

Status Bits Serial Communication

Parallel Communication

Mode-0

Mode-1

Mode-2

Mode-3

Single

Access

Repeated

Read

Direct Mode

SUV

SMV

CF

X

STE

SW4P

OTC

X

X¹⁾

X

1) Bit is volatile in direct mode

Datasheet

27

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ISOFACE™

ISO2H823V2.5

Functional Description

Upon reset most of the bits used in the ERR generation are reset to High, the ERR pin is pulled down on startup

and will remain Low as long as the external controller does not clear the corresponding bits (and as long as the

fault exists).

4.2.4

Update of the Diagnostic Registers

The following list describes the handling of appearing and disappearing failures and therefore the diagnostics.

•

Appearing diagnostic/failure: appearing diagnostics are stored internally within sticky registers and are OR-ed

into the register COLDIAG (except LEDGx). Therefore the appearing diagnostic/failure bit can be seen

immediately. After reading COLDIAG the diagnostic bits are transferred from the internal sticky registers to

DIAG0,...,DIAG7 from which these can be read now in detail.

•

Disappearing diagnostic/failure : the diagnostic bits are stored internally as sticky bits and therefore also (ored)

in COLDIAG. In the case the source for the diagnostic bits has disappeared the diagnostic bits are still

available internally and in COLDIAG until the user has read COLDIAG. Therefore the diagnostic bits never

disappear with vanishing of the source for setting the bits alone. Both conditions have to be fulfilled: vanishing

of the source of the occurence and reading of COLDIAG.

•

In the case the isochronous mode for the channel diagnostic values is activated with the bit FRZSC in register

GLCFG (see Chapter 4.2.5.2) the diagnostic bits are transferred from the internal sticky registers to

DIAG0,...,DIAG7 with each edge of the SYNC-signal.

Datasheet

28

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ISOFACE™

ISO2H823V2.5

Functional Description

4.2.5

SYNC Operation

The Isochronous Mode enables the synchronization of several devices (e.g. to provide 32 channels 4 devices are

grouped in parallel). In this way the update of all the output channels as well as their diagnostics can be

synchronized and held such that the Bus ASIC or microcontroller can program a new control word of the output

channels and read the diagnostics status. In continuous mode, each device with its own built-in oscillator is

updated independently.

The Isochronous Mode is controlled by the SYNC pin and independent of the selected serial or parallel interface

(with the SEL pin). It concerns only the update of user registers in the system.

4.2.5.1

SYNC-Signal for Drive-Signals

Figure 18 explains in detail the mechanism for SYNC = High, SYNC = Low and the rising and falling edges of

SYNC for transferring the drive-information from the uC-Chip to the Power Chip.

Programmed

DRIVE[X]

SYNC-

signal

to Power Chip

transferred

DRIVE[X]-

information

OUT[x]

continuous mode

isochronous mode

(SYNC is in high state)

(SYNC is in low state)

Page -2 - uc _isochronous _mode

Figure 18 SYNC Operation Timing

SYNC = High, Normal Mode:

The DRIVE-register can be written with new data and the contents of it is also transferred to the power chip.

SYNC = Low, Isochronous-Mode:

In isochronous mode the user can write the DRIVE-register but this value will not be transferred to the Power Chip.

Therefore the driver configuration (activation of drivers in the Power Chip) is frozen. In Figure 18 it can be clearly

seen that the toggling of the DRIVE[x]-information (SPI-data-cycle) at the right side had not been transferred to

the process side (see oval area in Figure 18).

4.2.5.2

SYNC-Signal for Diagnostics

Independent from the level of the SYNC-signal always the same reading-sequence of the diagnostics shall be

obeyed : read COLDIAG, check which channel x (in the following examples of Table 4 and Table 5 : channel 0)

shows the setting of diagnostic bits and read the related DIAG0,...,DIAG7 for checking in detail which diagnostic

Datasheet

29

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Functional Description

has been reported. Reading of COLDIAG first assures that the DIAG0,...,DIAG7-registers are loaded from the

internal sticky registers.

SYNC = High, Continuous Mode:

When the signal SYNC is High (default), the continuous mode is selected and the diagnostic registers

DIAG0,....DIAG7 are always updated after read access to COLDIAG.

Table 4 shows the typical scenario where an external disturbance (openload or short-circuit-to VBB) cause the

setting of the diagnostic registers DIAG0,...,DIAG7 (here DIAG0) and the collective diagnostic register COLDIAG.

After vanishing of the disturbance and reading of COLDIAG the internal diagnostic registers are reset. The SYNC-

waveform is sketched in red (in Table 4 for the continuous mode any waveform is allowed), the disturbance in light

shaded grey (in this example strictly time limited) and the possible read-access in dark grey.

Table 4

Continuous Mode (GLCFG : FRZSC = 0), Disturbance (to Channel 0) Scenario

Waveform permanently “High”

of SYNC

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx”1”xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

or any waveform of SYNC is allowed when GLCFG:FRZSC = 0

........”0”.....

scenario #

1

disturbance

1

read results

COLDIAG

DIAG0

read=yes

0x01

0xvalue

read=yes

0x00

2

disturbance

2

read results

COLDIAG

DIAG0

read=yes

0x01

0xvalue

read=yes

0x01

0xvalue

read=yes

0x00

SYNC = Low, Isochronous-Mode:

The isochronous mode for the channel diagnostic values is activated with the bit FRZSC in register GLCFG. If

FRZSC = 1 (RESYN = 0) the isochronous mode for diagnostics is enabled.

When SYNC is Low, the DIAG0-7 and COLDIAG (including CF) are not updated anymore (frozen). At the falling

edge of SYNC the information of the internal sticky registers is transferred to DIAG0,...,DIAG7. During SYNC =

High the information of the internal sticky registers has been mirrored and ored to COLDIAG. When isochronous

mode is activated the DIAG0,...,DIAG7-registers and COLDIAG freeze the diagnostic data. But the internal sticky

registers collect the diagnostic information independently from SYNC. With rising edge of SYNC the

DIAG0,...,DIAG7 registers and COLDIAG are updated on base of the contents of the internal sticky registers.

Table 5 shows some scenarios where an external disturbance (openload or short-circuit-to VBB) cause the setting

of the diagnostic registers DIAG0,...,DIAG7 (here DIAG0) and the collective diagnostic register COLDIAG. In all

scenarios the same procedure is sketched where a disturbance occurs and the diagnostic registers are read in the

following. The SYNC-waveform is sketched in red (in Table 5 for the isochronous mode with low and high periods),

the disturbance in light shaded grey (in this example strictly time limited at different timestamps) and the possible

read-access in dark grey. In Table 5 the occurence of the disturbance relative to the edges of the SYNC-signal is

altered. Read procedures can occur during the phase of SYNC = 0 or SYNC = 1. Dependent on the occurence of

the disturbance relative to the SYNC-edges and the read-process the diagnostic values have been already set in

COLDIAG and DIAG0,...,DIAG7 or the old values have been frozen. In the second case the new values will be

updated in COLDIAG and DIAG0,...,DIAG7 with the next rising edge of SYNC and can be read with the next read-

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Functional Description

cycle. Due to the sticky registers no diagnostic value is lost. After vanishing of the disturbance and reading the

diagnostic values are reset.

Entries in COLDIAG can be reset during SYNC = Low after a reading procedure when the disturbance had been

registered before the falling edge of SYNC and is therefore securely delivered. But DIAG0,...,DIAG7 remains

unaffected from this reading procedure.

Table 5

Isochronous Mode (GLCFG : FRZSC = 1 (RESYN = 0)), Channel 0 Disturbed, Scenarios

Waveform xxxx x

x xxxxxxxxx”1”xxxxxxxx

x High

x

x xxx”1”xx

x High

x

of SYNC

High x

x

x xxxxxxx”0”xxxxxxx

x xxx”0”xx x

Low

scenario #

1

disturbance

1

read results

COLDIAG

DIAG0

read=yes

0x01

0xvalue

read=yes

0x00

2

disturbance

2

read results

COLDIAG

DIAG0

read=yes =yes

read=yes

0x00

0x01

0x00

0xvalue 0x

val

3

....disturbance..........

3

read=yes

0x00

read=yes read=yes

read results

COLDIAG

DIAG0

0x01

0x00

0xvalue 0x00

4

.......disturbance............

4

read results

COLDIAG

DIAG0

read=yes

0x00

read=yes read=yes

0x01

0x00

0xvalue 0x00

5

disturbance

5

read results

COLDIAG

DIAG0

read=yes

0x01

0xvalue

read=yes

0x00

6

....disturbance..........

6

read results

COLDIAG

DIAG0

read=yes

0x00

read=yes

0x01

0xvalue

read=yes

0x00

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Table 5

Isochronous Mode (GLCFG : FRZSC = 1 (RESYN = 0)), Channel 0 Disturbed, Scenarios

Waveform xxxx x

x xxxxxxxxx”1”xxxxxxxx

x High

x

x xxx”1”xx

x High

x

of SYNC

High x

x

x xxxxxxx”0”xxxxxxx

Low

x xxx”0”xx x

Low

7

.......disturbance.........

7

read results

COLDIAG

DIAG0

read=yes

0x00

read=yes

0x01

0xvalue

read=yes

0x00

4.2.6

ODIS Output Disable

The low active ODIS signal immediately switches off the output channels OUT0-OUT7. This pin has an internal

Pull-Down resistor. In normal operation the signal ODIS is High. Setting ODIS to Low clears the registers as well.

The minimum width of the ODIS signal is 5 µs.

4.2.7

LEDGOFF

The gated-LED-signal LEDGx, x=0,...,7 is per default reported in the diagnostic registers DIAG0,...,DIAG7 (not

ored in the COLDIAG-register). LEDGx is updated with a long time constant every 100ms. Therefore the bit

LEDGOFF in GLCFG offers the possibility to suppress the reporting in the diagnostic registers DIAG0,...,DIAG7.

4.2.8

OLOFF

The bit OLOFF in GLCFG offers the possibility to suppress the reporting of OLIx, OLAx in the diagnostic registers

DIAG0,...,DIAG7.

4.2.9

RESET (Hard and Soft)

4.2.9.1

Hardware Reset

The external hardware reset can be enabled or disabled by the bit RSTOFF in the register GLCFG, by default the

external hardware reset function is enabled. The external hardware reset forces the logic asynchronous reset for

the uC_chip (acts like a power-on-reset), all register are loaded with the default values. It is triggered when the

signal ALE is set High whereas the CS signal is set Low for at least 100 µs. Once an internal timer reaches the

end value of 100 µs then the hardware reset condition is fulfilled and “latched”. At the point where one of the

signals ALE and CS returns to its default value, the reset is processed. With resetting the DRIVE-register and

restarting the CT-transmission the output switches are shut down.

4.2.9.2

Soft Reset

The soft reset for the uC_chip is triggered by the bit SWRST (self clearing after performing the soft reset) in the

register GLCFG. If the soft reset is triggered the DRIVE, INTERR, GLERR, DIAG0,...,DIAG7, COLDIAG,

DIAGCFG register are set to their reset values synchronously. In addition the internal flags are cleared. The CT-

transmission is restarted. The actual transmission cycle is not disturbed. With resetting the DRIVE-register and

restarting the CT-transmission the output switches are shut down.

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4.2.10

Resynchronization of CT-Transmission

During the CT-transmission the drive-information DRIVE for 8 power switches is sent from the uc-Chip to the

Power-Chip. Subsequently one of the diagnostic informations (status-information, OTx, OLIx, OLAx, OCLx,

SCVx or LEDGx-information for the 8 power switches) is sent back. The duration of a CT-time slot with

transmission of drive - information and back-transmission of one of the diagnostic information lasts about

5 us + 20 %. (internal operating frequency : 10 MHz, resistor at pin CLKADJ : 10 kΩ). When the user programs

the drive register a timing uncertainty arises when the specific programed switch is activated or deactivated in the

power chip. The data of the drive register can be transferred to the power chip only in the next free CT-time slot.

The goal of resynchronization is to limit the timing uncertainty due to transmission and retransmission to a value

below + 1.5 us but with a fixed latency of minimum 7.0 us . For triggering the transmission the signal SYNC is used

when GLCFG:RESYN = 1. A timing difference between switching on and off of the power transistors exists which

is already included in the timing uncertainty value above. Switching off a power transistor is delayed by up of 0.5 us

max relative to the SYNC-rising edge compared to switching on a power transistor.

Requirements on RESYNCHRONIZATION-Timing :

GLCFG:RESYN = 1

7.0 us min

SYNC

maximum time duration to finish current CT-slot 5 us

(determined by internal transmission and retransmission)

2.0 us

safety margin

…...

uC_chip

power -chip

DRIVE

Diagnostics

uC_chip

power -chip

next CT-slot

Figure 19 Timing of Resynchronization

Transmission without Resynchronization:

•

GLCFG:RESYN = 0 or 1

signal SYNC = 1

write the drive information into DRIVE

the contents of DRIVE is transferred via the CT to the power-chip

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Transmission with Resynchronization:

•

signal SYNC = 1

GLCFG:RESYN = 1

write the drive information into DRIVE_RESYNCH

signal SYNC = 0

the duration of the signal SYNC = 0 (minimum 7.0 us) determines the time for resynchronization and the time

until the next CT-transfer

•

In the meantime the pending transmission and retransmission has been finished and the contents of

DRIVE_RESYNCH has been transferred to DRIVE

set signal SYNC = 1, the CT-transfer is started from DRIVE with the rising edge of SYNC

Without any negative pulses on SYNC the CT-transfer is operated permanentely from DRIVE; the negative pulses

on SYNC are solely used for resynchronization, the isochronous mode for drive-information and for diagnostics is

inactive when GLCFG:RESYN is set to “1”.

Information for the DRIVE_RESYNCH-register can be written long before the resynchronzation trigger with falling

and rising edge of SYNC.

The user has to obey the timing requirements of the SYNC-signal. For a duration longer than 300 us + 20% the

watchdog in the power chip disables the output drivers. For a shorter duration of the SYNC-signal than

recommended the resynchronization is not guaranteed and the normal transmission fed by the register DRIVE can

be performed.

Figure 20 shows 2 different applications of resynchronization. The timing gap between two synchronizations can

be as low as 1 us. In this way the customer can decide between single synchronization steps and permanent

synchronized transmission with the drawback of reduced CTthrough put (time for waiting of new transmission).

Resynchronization of CT-Transmission

Scenario 1 : 2 resynchronization -steps after several transmissions

several transmissions and retransmissions

transmission

gap

trans.

gap

DRIVE

…...

restart

Diagnostics

SYNC

Diagnostics

restart

finish actual CT-slot and wait

transmission

after

tresynch

transmission

after

tresynch

t_resynch

SYNC

Scenario 2 : permanent resynchronization

transmission

gap

DRIVE

trans.

gap

restart

Diagnostics

restart

finish actual CT-slot and wait

transmission

after

tresynch

transmission

after

tresynch

t_resynch

(min. 7.0 us)

SYNC

t_resynch

SYNC

t_{resynch_gap}

(min.1 us)

Figure 20 Examples of Application of Resynchronization

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Functional Description

Application hint : It is not possible to select GLCFG:RESYN = 1 and isochronous mode of drive information or/and

isochronous mode of diagnostics at the same time. That means resynchronization and isochronous mode of driver

information and diagnostics at the same time is not possible. With GLCFG:RESYN = 1 edges on SYNC are used

solely for resynchronization.

4.3

Output Stage

Each channel contains a high-side power FET that is protected by embedded protection functions. The continuous

current for each channel is 600 mA nominal, which depends on the cooling conditions and the total power

dissipation.

4.3.1

Output Stage Control

Each output is independently controlled by an output latch and a common reset line via the pin ODIS that disables

all eight outputs and resets the latches.

4.3.2

Protection Functionality

4.3.2.1

Power Transistor Overvoltage Protection

Each of the eight output stages has it’s own zener clamp that causes a voltage limitation at the power transistor

when solenoid loads are switched off. V_ONCLis then clamped to 52 V (typ.).

4.3.2.2

Power Transistor Overload Protection

The outputs are provided with a linear current limitation, which regulates the output current to the current limit value

in case of overload. The electrical operation point does not lead to a shutdown.

The excess power dissipation in the power transistor during current limitation will lead to a rapid increase of the

junction temperature. When the junction temperature exceeds 150 °C (typ.) the output will switch off and will

switch on again when the junction temperature has cooled down by a temperature hysteresis of 15 K (typ.).

Therefore during overload a thermal on-off toggling may occur.

The thermal hysteresis is reset during inactive mode. Therefore when switching to the active mode the power

transistor is first switched on if the junction temperature is below 150 °C.

4.3.2.3

Current Sense and Limitation

To achieve an excellent accuracy for the current limitation and current referred diagnostic (OCLx) an external

reference resistor is used. The resistor must be connected between the pins IADJ (as close as possible) and

GNDBB. The nominal resistor value is 6.81 kΩ (E96; current drawn out of IADJ typ.178 µA) , the tolerance should

be within 2% to meet an overall current limit tolerance from 0.73 A to 1.3 A.

Operation with other resistor values than 6.8 kΩ ±5% is not allowed and may lead to insufficient short circuit

protection.

To offer open load diagnostics in active mode, a part of the power transistor is driven down when the drain-source-

voltage drops below a certain limit (low load condition). The voltage drop across the remaining part is used to

evaluate an open load diagnostic.

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4.3.3

Diagnostic Functions

For each of the output stages 5 different types of diagnostics are available. Table 6 specifies the diagnostics.

Some of the diagnostics are available only in active mode, others only in inactive mode. The diagnostics OLIx,

OLAx, SCVx can be prolonged within the complementary mode. Overtemperature in inactive mode is not reported

(set to zero).

Table 6

Item

Diagnostic

Diagnostic Type

Overtemperature

Inactive Mode

Active Mode

OTx

no

yes (OTx Active)

OLIx

Open Load/Wire Break, “inactive” yes

no

OLAx

OCLx

Open Load/Wire Break, “active”

no

yes

Current Sense,

Overload Detection

SCVx

Short Circuit to V_BB

yes

not distinguishable from OLAx

VBB

VBB Monitoring

GLERR

UV

Under Voltage Detection

Missing Voltage Detection

Reset Voltage

MV

CF

Output Driver Control Unit

Driver

Protection Unit

COLDIAG

OUTx

IADJ

Zener Clamping

(Demag. of Induct. Loads)

Temperature Sensor

Current Limitation

Diagnostic

Unit

DIAGx

OCL

Overload Detection

OT

Over Temperature Detection

OLADJ

OLA

SCV

OLI

Open Load Active Detection

Short to VBB Detection

Open Load Inactive Detection

DIAGCFG

Diagnostics_Overview_ISO2H823V.vsd

Figure 21 Diagnostics Overview

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The diagnostics OLIx, SCVx are reported in inactive mode and OLAx is reported in active mode. When the

duration of the disturbance was not sufficient to guarantee a 6 ms blanking/filtering time these diagnostics are at

least reported when switching from one mode into the other mode. The diagnostics OLIx, OLAx and SCVx,OLAx

appear in pairs one component for the inactive mode and one component for the active mode with a delay for the

filtering. In order not to allow reporting gaps the diagnostics are prolonged until the complementay part is occurring

or until a time out counter has expired (f.e. the diagnostic OLIx (SCVx) is prolonged also during the active time

period until the filter delivers a reliable OLAx- (OLAx-) diagnostics and vice versa).

4.3.3.1

Diagnostics in Inactive Mode

When the output is in inactive mode a diagnostic current is fed to the output. If the load is connected and the load

resistance is less than 12 kꢀ, the output voltage will be 300 mV or less.

If no load is connected a voltage drop of 7 V is present at the output. A voltage in the range of 5.5 V up to 9.2 V

at the output OUTx is detected and reported as open load inactive (OLIx) after filtering.

If the output is shorted to V_BBthe output voltage will be close to V_BBlevel even in inactive mode, this depends upon

the type of the short circuit. A voltage level above 9.2 V at the output is detected and reported as short circuit to

V_BB(SCVx) after filtering.

The window comparator for OLIx (5.5 V - 9.2 V) is realized with the analog level comparators for 5.5 V and 9.2 V

and the digital filters for OLIx and SCVx. After filtering SCVx has the priority against OLIx. By means of the digital

filters EMI-contributions shall be filtered before deciding about OLIx or SCVx.

If a capacitive load with a long RC time constant is connected to the ISO2H823V2.5 (like a 12 kꢀ resistor through

a long cable with 100 nF capacitance) when switching off, the output voltage sequently passes through the

windows of short to VBB detection and broken wire detection. During a blanking time of 6 ms (typ.) the diagnostic

signals are ignored to avoid false triggering of diagnostic registers.

If the corresponding channel is switched on again before the end of the blanking time (6 ms) , the state of the

diagnostic signals present before switching on is transferred to the diagnostic registers, bypassing the blanking

window of 6 ms and filtered instead with a filtering time of 100 us, 0.5 ms, 1 ms depending on the switching

frequency.

Table 7

Filter Time in Inactive Mode for OLIx and SCVx

Duration of inactive time t_OFFbefore switching

0 ms < t_OFF< 1.5 ms

Filter time

100 us

1.5 ms < t_OFF< 3 ms

0.5 ms

3 ms < t_OFF< 6 ms

1 ms

t

_OFF> 6 ms

6 ms (OLIx), 2 ms (SCVx)

For the largest SCVx-filter a filter-length of 2.0 ms is choosen but a setting of SCVx is only possible after the

blanking window of 6 ms. No single channel over temperature diagnostics is given during inactive mode to avoid

false triggering when switching inductive loads.

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4.3.3.2

Diagnostics in Active Mode

If during active mode operation the remaining voltage drop of a low load condition is compared to the voltage drop

across a reference transistor biased with a reference current. The reference current can be set by the value of a

resistor connected between OLADJ and GNDBB defining the threshold for open load diagnostics. The resulting

open load threshold is inversely proportional to the connected resistor (25 kꢀ - 2.3 kꢀ, E96 series; current out of

the OLADJ-pin 48.6 µA - 528 µA) and can be set within 0.5 mA to 5 mA.

Like the diagnostics in inactive mode the open load diagnostics in active mode (OLAx) is ignored during a 6 ms

blanking window after switching on. If the channel is switched off before the end of the blanking window the current

state of the open load diagnostics is transferred to the diagnostic registers, bypassing the blanking window of 6

ms and filtered instead with a filtering time of 100 µs, 0.5 ms or 1.0 ms (depending on the switching frequency).

The over load diagnostic (OCLx) occurs generally if the output stage limits the load current. Therefore the

diagnostic threshold is equal to the current limiting value. An overload may and a short to GNDBB will probably

lead to a thermal shutdown. The shutdown is indicated separately by the diagnostics OTx. The standard filter time

for overload (OCLx) and overtemperature (OTx) is 50 us (for a thermal shutdown).

Table 8

Filter Time in Active Mode for OLAx

Duration of active time t_ONbefore switching

0 ms < t_ON< 1.5 ms

Filter time

100 us

0.5 ms

1 ms

1.5 ms < t_ON< 3 ms

3 ms < t_ON< 6 ms

t

_ON> 6 ms

6 ms

Some loads like incandescent lamps or DC motors show an inrush current, which is normal and should not trigger

an overload diagnostic. In some cases even a transient thermal shutdown can not be avoided but an OTx-

message is avoided for the time duration of running up f.e. a cold lamp (max. 200 ms). In this case and only for

this short time duration the current limiting threshold can be set to 1.5 A and the temperature threshold to 200°C

by the internal finite state machine.

The ISO2H823V2.5 adapts filtering of over load and thermal shutdown diagnostics as well as shutdown

temperature and current limit level by evaluating the previous turn off time and the load resistance.

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4.3.3.3

Diagnostic Scenarios in Dependence of Switching Frequency

The Table 9 explains the occurence of diagnostics dependent on the switching frequencies for the disturbance

“Short-Circuit-to-VBB”.

Table 9

Occurence of Diagnostics during the Disturbance : Short-Circuit-to-VBB

Stable Switching Frequency : f

Reported

Unwanted Diagnostics at

Diagnostic

Onset of ............................or at Resolving of

SCVx-Disturbance

permanently “low” : f <= 62,5 Hz

SCVx, OLAx

OLIx ¹⁾

permanently “intermediate”

62,5 Hz < f < 2 kHz

SCVx, OLAx OLIx ²⁾

permanently “high”

f >= 2 kHz

SCVx, OLAx OLIx ²⁾

Transitions in the Switching

Frequency : f

permanently “low”

--> permanently “high”

f <= 62,5 Hz --> f >= 2 kHz

SCVx, OLAx OLIx ^{1) 2)}: depends on the time of onset and resolving of

SCVx-disturbance

permanently “high”

--> permanently “low”

f >= 2 kHz --> f <= 62,5 Hz

SCVx, OLAx OLIx ^{1) 2)}: depends on the time of onset and resolving of

SCVx-disturbance

1) In Table 9 an additional OLIx-signal can be generated when 1. the SCVx-disturbance has been resolved in the inactive

phase and 2. the inactive phase is longer than 8 ms (f < 62,5 Hz) and 3. the SCVx-disturbance has been existing for >= 6

ms in the inactive phase. The occurence of the additional OLIx-signal depends on the relative duration of the inactive mode

and the SCVx-disturbance. It disappears at last after 4 ms or with continued switching of the power transistor. As

the user himself has caused the additional OLIx-signal by resolving the SCVx-disturbance the user can ignore this signal

for the next 4 ms or can continue switching the power transistor.

2) Depending on the onset of the SCVx-disturbance in scenarios with high or intermediate switching frequency one time an

unwanted OLIx-reporting can occur which vanishes during further switching. As in the upper case ¹⁾the user can

ignore it as in the sequel the correct signaling occurs.

The Table 10 explains the occurence of diagnostics dependent on the switching frequencies for the disturbance

“Openload”.

Prerequisite : an external capacitor of C = 10 nF (minimum value) for enhancing the EMI-robustness is attached

to the output. VBB = 24 V.

In Table 10 the additional SCVx-diagnostic reflects the transition from active to inactive mode when the external

C (EMI-robustness) has to be decharged via a high ohmic internal resistor. During the decharging process the

output voltage is in the region of reporting SCVx.

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Table 10

Occurence of Diagnostics during the Disturbance : Wirebreak

Stable Switching Frequency : f

Reported

Comment

Diagnostic

permanently “low” : f <= 50Hz

OLIx, OLAx,

SCVx

additionally SCVx¹⁾

instead of OLIx : SCVx²⁾

permanently “intermediate”

50 Hz < f < 2 kHz

SCVx, OLAx

permanently “high”

f >= 2 kHz

Transitions in the Switching

Frequency : f

permanently “low”

--> permanently “high”

f <= 50 Hz --> f >= 2 kHz

OLIx, OLAx,

SCVx

--->

additionally SCVx¹⁾

SCVx, OLAx

permanently “high”

--> permanently “low”

f >= 2 kHz --> f <= 50 Hz

SCVx, OLAx

---->

OLIx, OLAx,

SCVx

1) additionally SCVx reported, diagnostic due to decharging of the external C (EMI-robustness)

2) instead of OLIx is SCVx reported,diagnostic due to decharging of the external C (EMI-robustness)

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4.3.3.4

Global Diagnostics

The global diagnostics include:

•

UV: undervoltage supply condition when VBB is below 16 V with 0.5 V hysteresis,

MV : missing voltage supply condition when VBB is below 13 V with 0.5 V hysteresis,

OTP: global over temperature (chip temperature outside the switch area triggers above 125 °C), the global

over temperature does not lead to thermal shutdown,

•

ALLOFF: all drivers in the power chip are disabled (by DRIVE-programming, ODIS-setting or temperature

shutdown of all channels),

LAMP: the load of one of the drivers behaves like a cold lamp

4.3.3.5

Power Supply

The startup procedure of the power chip is explained in Figure 22.

V_VBB

Voltage

V_VBBuvoff

V_VBBuvon

V_UV

V_VBBuvhys

V_VBBmvoff

V_VBBmvon

V_MV

V_VBBmvhys

V_VBBon

V_VBBoff

V_RESET

V_VBBhys

Time

RST

MV

UV

por_uv_mv_events .vsd

Figure 22 Start Up Procedure of the Power Chip

During UVLO, all registers of the power chip are reset to their reset values as specified in the register description

(Chapter 6). As a result, the flags TE, UV as well as MV are High and the ERR pin is Low (error condition).

Immediately after the reset is released, the chip is first configured by “reading“ the logic level of the SEL, MS1,

MS0 - pins. The IC powers up as a parallel device i.e. the AD0-7 pins are high-impedance until the IC configuration

is over.

The supply voltage VBB is monitored during operation by two internal comparators (with typ. 2 ms blanking time)

detecting:

•

VBB Undervoltage: If the voltage drops below the UV threshold, the UV-bit in the GLERR register is set High.

The IC operates normally.

•

VBB Missing Voltage: If the voltage further drops below the MV threshold, lower than the previous threshold,

the MV-bit in the GLERR register is set, the Power Side of the IC is turned off when reaching the VReset-

threshold whereas the Micro-Controller Side remains active.

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Note: The driver stage is self protected in overload condition: the internal switches will be turned off as long as the

overcurrent condition is detected and the IC will automatically restart once the overload condition

disappears.

Important: Since the UV and MV (as well as the TE) bits used for generating the ERR signal are preset to High

during UVLO, the ERR pin is Low after power up. Therefore the ERR requires to be explicitly cleared after power

up. At least one read access to the GLERR and INTERR registers or one default read access in certain access-

modes (see Chapter 4.2.3) is needed to update those status bits and thus release the ERR pin.

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4.3.4

LED Matrix

The driving signal for the LED-matrix is the drive-signal of the register DRIVE gated with the signal LEDGx of the

registers DIAG0,...,DIAG7. This signal is generated in the power chip and transferred via the CT-interface to the

uC-Chip. For suppressing a thermic toggling visible on the LED-matrix LEDGx disables the related LED for at least

100ms when an overtemperature (OTx) or overcurrent condition (OCLx) has occurred.

4.3.4.1

LED Matrix on the Process Side

Eight LEDs arranged in a 3x3 matrix can be driven through the outputs LEDx0 to LEDx2 and LEDy0 to LEDy2 of

the Power Chip. Each output channel has a corresponding status LED in the matrix showing the actual status of

the channel. When the LED lights up, the corresponding channel is in the active mode and has no thermal

shutdown and no overcurrent condition.

Series resistors must be inserted in each column line LEDy0...LEDy2 to set the LED current. The driving level on

the column lines is the V_BBvoltage level. The row lines are driven alternately with 1/3 duty cycle at 1000 Hz. The

resulting average current for each LED is 1/3*(V_BBminus diode forward voltage)/series resistance.

If the diode matrix is used at all, all 8 LEDs must be connected for correct function of the matrix.

LEDy2

LEDy1

LEDy0

S0

S1

S2

S3

S4

S5

S6

S7

LEDx0

LEDx1

LEDx2

Figure 23 LED Matrix connected to the Power Chip

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ISO2H823V2.5

Functional Description

Figure 24 LED Pulse Diagram

If no LEDs are used at all it is possible (by reasons of EMI) to connect all column signals LEDY0,..,2 together and

all row-signals LEDx0,..,2 together but a connection among columns and rows is not allowed. In the case of

paralleling of channels it is possible to substitute the unused LEDs by resistors which have the only function to

dissipate the current which is delivered in case the not existing diode is accessed. If no limiting element is used

(f.e. resistor) the voltage at the LEDs of the non-activated rows can rise up to VBB if the non-existing element is

activated (the related row activated and the corresponding column activated).

4.3.4.2

LED Matrix on the uController Side (only in Serial Communication Mode)

For the driving signals on the uController-side the following pins are used for the column signals : AD1 / LEDC2,

ALE/RST / LEDC1, WR / LEDC0 and for the row-signals : AD2 / LEDR2, AD3 / LEDR1, AD6 / LEDR0. For enabling

the LED-function on the uC-Chip side the bit LEDON in the GLCFG-register has to be set. LED-operation is only

possible in the serial communication mode. If LEDON = 1 the hardware reset function is disabled.

As in the case for the LED on the power chipside a 3x3 matrix can be driven. Each output channel has a

corresponding status LED in the matrix showing the actual status of the channel. When the LED lights up, the

corresponding channel is in the active mode and has no thermal shutdown and no overcurrent condition. The 9.th

LED is connected with the ERR-signal.

Series resistors must be inserted in each column line LEDC0...LEDC2 to set the LED current. The driving level on

the column lines is the V_CCvoltage level. The row lines are driven alternately with 1/3 duty cycle at 1000 Hz. The

resulting average current for each LED is 1/3*(V_CCminus diode forward voltage)/series resistance.

If the diode matrix is used (LEDON = 1) , all 9 LEDs must be connected for correct function of the matrix.

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ISO2H823V2.5

Functional Description

AD1 / LEDC2

ALE/RST / LEDC1

/WR / LEDC0

S0

S1

S2

S3

S4

S5

S6

AD6 / LEDR0

AD3 / LEDR1

S7

ERR

AD2 / LEDR2

Figure 25 LED Matrix connected to the uC-Chip

In the case of paralleling of channels it is possible to substitute the unused LEDs by resistors which have the only

function to dissipate the current which is delivered in case the not existing diode is accessed.

The minimum value of the VCC-voltage is 2.75 V. But this low voltage will limit the choice of the used LEDs (in the

worst case only LEDs with a lower forward voltage of around 2.2 V are possible).

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ISO2H823V2.5

Functional Description

4.4

EMI-Robustness

Care has been taken to increase the Burst- and RFCM-robustness according to the standardization requirements

referenced in

•

DIN EN 61131-2 (Programmable Controllers , Part 2 : Equipment Requirements and Tests)

IEC 61000 -4-4 (Testing and measurement techniques - electrical fast transient/burst immunity test)

IEC 61000 -4-6 (Testing and measurement techniques - immunity to conducted disturbances, induced by

radio-frequency fields)

respectively.

As the standardization document DIN EN 61131-2 gives a system-requirement we can give only recomendations

for the application with ISO2H823V2.5 for improvement the EMI-robustness. Exact values have to be evaluated

with the total system including external components and PCB-layout and wiring.

For Burst- and RFCM-robustness we consider only the driver-pins OUTx and VBB as these pins are exposed to

external disturbances. Other pins of ISO2H823V2.5 are encapsulated within the housing of the control equipment

(f.e. PLC).

The influence of HF-signals is eliminated internally with assistance of the external capacitor of min.10 nF (+ 10%)

at the output OUTx of each power transistor. To increase the safety margin if higher test voltages are applied it is

possible to increase the capacitor up to 12 nF + 10 %.The purpose is to suppress frequency contributions of the

external disturbance greater than 2 MHz.

Investigations have been done with an external load of a high value of 12 kꢀ. Other critical loads consisting of a

high inductive value combined by a high resistive value (f.e. 0.8 H, 1.4 kꢀ) have been also examined.

4.4.1

Burst Robustness

Figure 26 shows the test circuitry for applying burst pulses. The fat drawn equipment symbolizes the burst-

generator and the coupling of burst pulses to the OUTx-pins and/or to the VBB-pin (see the different coupling

network for OUTx, VBB as specified in IEC 61000).

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ISO2H823V2.5

Functional Description

Burst-Application

VBB

each OUT or VBB is

loaded separately with

burst pulses

IADJ

2.2 uF

OLADJ

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

Control

Protection

Diagnostic Unit

100 pF

10 nF

C

10 nF

min.

*)

C

10 nF

min.

*)

50 Ohm

load

12

kOhm

load

12

kOhm

+

-

+

-

C_{system_earth}

22 nF

=

ISO2H823V2

Power Chip

VDDIO

VCORE

GNDBB

System_GND

Earth

*) : for enhancement of EMI-robustness,

recommended value 12 nF

C_{system_earth}on application board for separation

of System_GND and Earth

Figure 26 Burst-Application

For burst-disturbance the standard foresees 2 repetition frequencies : 5 kHz and 100 kHz. For the repetition

frequency of 5 kHz the target is to achieve a burst-robustness of min .+ 2500 V within the system with external

elements. For a repetition frequency of 100 kHz it is much harder a give an estimation without the knowledge of

external elements. For this case no statement is given here.

4.4.2

RFCM-Robustness

Figure 27 shows the test circuitry for applying RFCM frequencies. The fat drawn equipment symbolizes the HF-

generator and the coupling of HF frequencies to the OUTx-pins and/or to the VBB-pin (the drawn coupling network

shall symbolize an effective impedance of 150 ꢀ regardless of the frequency as specified in IEC 61000). The HF-

disturbance is an 80%-amplitude modulated signal with the carrier frequency of 10 kHz - 80 MHz and the

modulation frequency of 1 kHz.

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ISO2H823V2.5

Functional Description

RFCM / HF-Bestromung

VBB

each OUTx or VBB is

loaded separately

with HF signals

IADJ

2.2 uF

OLADJ

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

*) : for enhancement of EMI-robustness,

recommended value 12 nF

Control

Protection

Diagnostic Unit

|Z| =

150 Ohm

load =

12

kOhm

C

10 nF

min.

*)

C

10 nF

min.

*)

C_{system_earth}

= 22 nF

ISO2H823V2

Power Chip

VDDIO

VCORE

GNDBB

System_GND

Earth

V_{HF_peak_peak}

0 V

carrier frequency : 10 kHz – 80 MHz,

modulation frequency : 1 kHz

amplitude modulation with 80%

1 ms

Figure 27 RFCM-Application

The 80 % amplitude modulated signal is shown in Figure 27 in the lower half. With external elements on the user-

PCB-board it is targeted to achieve a RFCM-robustness against the defined HF-signals of V_{HF_peak_peak}= + 25 V.

4.5

Application Hints

4.5.1

Layout Recommendations

The reference resistor for CLKADJ must be placed close to the pin 38 CLKADJ and pin 39 GND. Decoupling

capacitors should be close to VCC terminal pin 37 and directly connected to the GND plane on the PCB.

GND and GNDBB must be totally isolated in the PCB layout. A separation distance of min. 3.2mm is

recommended.

The reference resistors for OLADJ, IADJ must be placed close to their terminals of the ISO2H823V2.5 and the

connection to the referring ground plane should be as short as possible. The capacitors for V_COREand V_DDIOmust

be placed close the pins and directly connected to the GNDBB plane.

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ISO2H823V2.5

Electrical Characteristics

5

Electrical Characteristics

Note:All voltages at pins 1 to 32 as well as 61 to 70 are measured with respect to GNDBB. All voltages at pins 33

to 60 are measured with respect to GND. The voltage levels are valid if other ratings are not violated. The

two voltage domains V_CCand V_BBare internally galvanic isolated.

Note:All Typical Values are defined by T_j= 25°C, V_BB= 24 V, V_CC= 3.3V.

Note:Electrical Values are defined in the range T_j= -40 ... 125°C, V_BB= 11...35 V, V_CC= 2.75...3.6 V, unless

otherwise specified, Table 13 to Table 26.

5.1

Absolute Maximum Ratings

(at T_j= -40 … 135 °C, unless otherwise specified)

Note:Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of

the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin

37 (V_CC) is discharged before assembling the application circuit. Operating at absolute maximum ratings can

lead to a reduced lifetime.

Absolute maximum ratings are not subject to production test.

Table 11

Absolute Maximum Ratings

Symbol

Parameter

Values

Unit Note / Test Condition

Min.

-0.5

-1¹⁾

Typ.

Max.

3.6

Supply voltage input interface

Supply voltage output interface

V_CC

–

V

–

V_BB

V_Dx

45

Continuous voltage at data inputs

(AD0 … AD7)

-0.5

3.6

Continuous voltage at pin CS

Continuous voltage at pin ALE

Continuous voltage at pin RD

Continuous voltage at pin WR

Continuous voltage at pin SYNC

Continuous voltage at pin ODIS

Continuous voltage at pin ERR

Continuous voltage at pin SEL

Continuous voltage at pin MSx

V_CS

-0.5

–

3.6

1.65

3.6

V_BB

V

–

V_ALE

V_RD

V_WR

V_SYNC

V_ODIS

V_ERR

V_SEL

V_MSx

Continuous voltage at pin CLKADJ V_CLKADJ

Continuous voltage at pin VCORE V_VCORE

Continuous voltage at pin VDDIO

Continuous voltage at pin IADJ

Continuous voltage at pin OLADJ

Continuous voltage at pin OUTx

Continuous voltage at pin LEDXx

Continuous voltage at pin LEDYx

V_VDDIO

V_IADJ

V_OLADJ

V_OUTx

V_LEDXx

V_LEDYx

V

_BB-55

-0.5

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ISO2H823V2.5

Electrical Characteristics

Table 11

Absolute Maximum Ratings (cont’d)

Parameter

Symbol

Values

Typ.

–

Unit Note / Test Condition

Min.

Max.

Load current (short-circuit current) I_L

–

Self

A

–

limited

LED matrix driver current

I_LED

-20

-40

20

mA

Peak current each LED

Static operation

Static operating temperature

T_{j stat}

Internal °C

limited

Peak junction temperature

Periodic temperature cycling

T_{j per}

T_js

–

175

200

75

°C

K

Periodic duty cycle <1%

Non periodic

∆T_jper

f = 2 Hz

Transient thermal impedance all 8 Z_th

channels

0.375

3.5

–

K/W 12 ms sawtooth pulse, all

channels equally loaded

Transient thermal impedance single Z_th

channel

–

K/W 50 ms sawtooth pulse 1

channel loaded

Storage Temperature

Power Dissipation²⁾

T_stg

P_tot

E_AS

-50

–

150

1.5

°C

W

–

Inductive load switch-off energy

dissipation for each channel, single

pulse³⁾, all channels are switching

simultaneously, T_j=125°C, I_L= 0.6 A

150

mJ

Electrostatic discharge voltage

(Human Body Model)

according to JESD22-A114

V_ESD

–

2

kV

–

Electrostatic discharge voltage

(Charge Device Model)

according to JESD22-C101

1) Defined by P_tot.

V_ESD

0.5

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 mm Cu, 2 × 35 mm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

3) Single pulse means that the thermal recovery time is sufficient so that an increase of the chip temperature is avoided or at

least limited (depends on the thermal connection of chip with PCB-board, Figure 34- Figure 36 ) .

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ISO2H823V2.5

Electrical Characteristics

5.2

Operating Conditions and Power Supply

For proper operation of the device, absolute maximum rating (Table 11) and the parameter ranges in Table 12

must not be violated. Exceeding the limits of operating condition parameters may result in device malfunction or

spec violations. The power supply pins V_BBand V_CChave the characteristics given in Table 14.

Table 12

Operating Range

Parameter

Symbol

Values

Unit

Note /

Test Condition

Min.

2.75

11

Typ.

–

Max.

3.6

35

Supply Voltage Logic V_CC

Supply Voltage Power V_BB

Ambient Temperature

V_VCC

V_VBB

V

Related to GND

Related to GNDBB

–

V

T_A

-40

-25

30

–

85

°C

Junction Temperature

T_J

–

150

125

25

°C

Package Temperature

T_pack

–

°C

Exposed Pad

1)

Common Mode Transient

Magnetic Field Immunity

Bias Resistor for Current Limit

Bias Resistor for Open Load

Bias Resistor for CLKADJ

dV_ISO//dt

|HIM|

R_IADJ

R_OLADJ

R_CLKADJ

–

kV/µs

A/m

kꢀ

–

IEC61000-4-8¹⁾

C_IADJ< 25 pF

6.46

2.3

9.9

6.81

–

7.14

25

C_OLADJ< 25 pF

10

10.1

E96-resistor, C_CLKADJ

< 25 pF

1) Not subject to production test, specified by design.

Table 13

Thermal Characteristics

Parameter

Symbol

Values

Typ.

–

Unit

Note /

Test Condition

Min.

Max.

Thermal resistance junction -

case top¹⁾

R_{thJC_Top}

R_{thJC_Bot}

–

10.5

K/W

Measured on top side

Thermal resistance junction -

case bottom¹⁾

–

0.5

–

Thermal resistance junction - pin¹⁾R_thJP

Thermal resistance ²⁾¹⁾

R_th(JA)

–

26

–

K/W

23

–

1) Not subject to production test, specified by design.

2) Specified R_thJAvalue is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product

(Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 mm Cu, 2 × 35 mm

Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

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ISO2H823V2.5

Electrical Characteristics

Table 14

Electrical Characteristics of the Power Supply Pins

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Min.

–

Max.

9.35

–

V

_BBUVLO startup threshold

_BBUVLO shutdown threshold

_BBUVLO Hysteresis

V_VBBon

8.9

7.9

1

V

–

V_VBBoff

7.5

–

V_VBBhys

V_VBBmvoff

–

_BBmissing voltage OFF (MV)

–

13.3

14.0

threshold

_BBmissing voltage ON (MV)

threshold

_BBundervoltage OFF (UV)

threshold

_BBundervoltage ON (UV)

V

V_VBBmvon

V_VBBuvoff

V_VBBuvon

T_VBBfil

12.1

–

12.8

16.2

15.7

2

–

V

–

V

17.0

–

V

14.9

–

V

threshold

Glitch filters for V_BBmissing

–

ms

voltage and undervoltage¹⁾

Undervoltage Current for V_BB

Quiescent Current V_BB

I_VBBuv

I_VBBq

–

1.7

9

–

mA

V

_VBB< 7.0 V

_VBB= 24 V, all

channels inactive,

V

–

_CC= 0 V

Voltage Level of VDDIO

Voltage Level of VCORE

Startup Delay (time between

V_VDDIO

V_VCORE

t_VXXon

–

3.3

1.5

0.3

–

V

_VBB= 24 V

V

ms

V

_BBon/V_CConand first active

mode)¹⁾

V

_CCUVLO startup threshold

_CCUVLO shutdown threshold²⁾V_VCCon

V_VCCoff

–

2.75

–

V

–

2.5

0.01

–

V

–

_CCUVLO threshold hysteresis

V_VCChys

I_VCCq

I_VCC

–

V

–

Quiescent Current V_CC

1.2

5.8

-

–

mA

V

_VCC= 2.4 V

_VCC= 3.6 V

_VCC= 3.3 V

_VCC= 2.75 V

Current V_CCwithout SPI-Activity

–

8.5

8

I_VCC

–

I_VCC

–

-

7

1) Not subject to production test, specified by design.

2) Note that the specified operation of the IC requires V_VCCas given in Table 12

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Electrical Characteristics

5.3

Load Switching Capabilities and Characteristics

Table 15

Load Switching Capabilities and Characteristics

Parameter

Symbol

Values

Typ.

Unit Note / Test Condition

Min.

Max.

On-state resistance

R_ON

–

210

250

mꢀ

I_L= 0.6 A

T_j= 125 °C

VBB = 24 V, Each channel

Leakage output current (included in I_L(off)

I_BB(off)

–

35

30

µA

µs

V_ADx= low, each channel,

x = 0,...,7, VBB = 24 V

)

1)

Turn-on time to 90% V_OUT

t_on

R_L= 48 ꢀ, V_ADx= 0 to 3.3V,

V

_BB= 24 V

R_L= 48 ꢀ, V_ADx= 3.3 to 0V,

_BB= 24 V

1)

Turn-off time to 10% V_OUT

t_off

V

Slew rate V_OUT

dV/dt_on

–

2

–

V/µs R_L= 48 ꢀ, V_BB= 24 V

-dV/dt_off

V/µs R_L= 48 ꢀ, V_BB= 24 V

1) The turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless

transformer in normal operating mode. During a transmission error on the coreless transformer transmission turn-on or

turn-off time can increase by up to 20 µs.

5.4

Output Protection Functions

Table 16

Output Protection Functions ¹⁾

Symbol

Parameter

Values

Unit Note / Test Condition

Min.

0.73

0.7

Typ.

1

Max.

1.3

Overload current limit

Short circuit current

I_OCL

I_SCL

A

V

_BB- V_out= 1 V

_BB- V_out= 28.8 V²⁾

1

1.4

Output clamp (inductive load switch V_ON(CL)

off)³⁾at V_OUT= V_BB- V_ON(CL)

45

52

60

I_ON(CL)= 50 mA

Thermal overload trip temperature⁴⁾T_jt

135

–

150

15

–

°C

K

–

Thermal hysteresis⁴⁾

∆T_jt

1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet.

Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous

repetitive operation.

2) Thermal effects when T_jswitch>>T_case

3) If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest V_ON(CL)

.

4) Not subject to production test, specified by design.

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Electrical Characteristics

5.5

Electrical Characteristics µController Interface

For the Parallel Mode see Table 17, Table 19, Table 23 and Table 25

For the Serial Mode see Table 17, Table 19, Table 24 and Table 25

Timing characteristics refer to C_L< 50 pF and R_L> 10 kꢀ

Table 17

Setting at the Configuration Pin (CLKADJ)

Parameter

Symbol

Min.

Values

Typ.

0.5

Unit

Note /

Test Condition

Max.

CLKADJ Pin Regulated Voltage

V_CLKADJreg

–

V

–

Table 18

Error Pins (ERR, CRCERR)

Parameter

Symbol

Values

Unit

Note /

Test Condition

Min.

Typ.

–

Max.

0.25 V_CC

–

Error Voltage (ERR, CRCERR=0) V_{ERR_CRCERR}

–

V

I_{ERR_CRCERR}= 5 mA¹⁾

–

Error Pin Pull-Up Resistance

(ERR, CRCERR = 1)

R_{ERR_CRCERR}

50

kꢀ

pu

Maximum Switching Frequency

(ERR, CRCERR)²⁾

f_SW

–

200

–

kHz

10 kꢀ external Pull-

Up Resistor

1) Spikes on CRCERR due to f.e. cross coupling between SCLK and CRCERR are not expected to violate this figure

V_{ERR_CRCERR}, because cross coupling pulses are very small (10 nsec), V_{ERR_CRCERR}is evaluated after the rising edge of CS

(and not during any edges of SCLK) and with a lower I_{ERR_CRCERR}(f.e. 1 mA) V_{ERR_CRCERR}is also lowered (in the example

by a factor of 5).

2) Not subject to production test, specified by design; worst case is the reading in serial mode 2 with a frequency of 500 kHz

CRCERR can toggle with 500 kHz

Table 19

Logical Pins (RD, WR, ALE, MS0/1, CS, AD7: AD0, SCLK, SDO, SDI, SEL, SYNC, ODIS)

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Min.

Max.

Input Voltage High Level

Input Voltage Low Level

Input Voltage Hysteresis

Output Voltage High Level

Output Voltage Low Level

Output Voltage High Level

V_IH

0.7·V_VCC

-0.3¹⁾

–

V

_VCC+0.3

V

–

V_IL

–

0.3·V_VCC

V

–

V_Ihys

V_OH

V_OL

V_OH

–

100

–

mV

V

–

0.75·V_VCC

1·V_VCC

I_OH= 5 mA²⁾

0

-

–

0.25·V_VCC

V

I_OL= 5 mA

2.65

-

V

V_VCC= 2.75V, I_OH=

1mA³⁾

Output Voltage Low Level

V_OL

-

0.1

-

V

V_VCC= 2.75V - 3.6V,

I_OL= 1mA

1) Not subject to production test, specified by design.

2) Maximum source / sink current: I_OHmax= I_OLmin= 5 mA; external load C_L< 50 pF, R_L> 10 kꢀ

3) Same argumentation as for Digital Input Isoface : typical values over temperature derived for I_OH= 5 mA and I_OL= 5 mA.

Extrapolation to I_OH= 1mA and I_OL= 1mA to possible. Voltage drop scales with a factor of 1/5 with the change of 5 mA to

1 mA. Not subject to production test.

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Electrical Characteristics

Table 20

SYNC-Timing

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Min.

Max.

1)

Minimum time interval for µC-

Read-Access after falling edge of

SYNC-signal

t_syncmin

400

500

ns

1)

Minimum width of SYNC-signal

SYNC-period

t_syncw

200

500

400

ns

t_syncper

Minimum time interval for Direct- t_h

Write-Access after falling edge of

SYNC-signal (to ensure that the

new data are not CT-transmitted

during SYNC = low)

500

1) not subject of production test, specified by design

Table 21

RESYNCH-Timing

Parameter

Symbol

Values

Unit

Note /

Test Condition

Min.

Typ.

Max.

1)

Minimum width of SYNC-low-

phase during resynchronization

t_resynch

7.0

--

240

us

1)

Minimum time interval between

two resynchronization processes

(minimum width of SYNC-high-

phase)

t_{resync_gap}1.0

1)

Timing jitter of transmission of

drive-data over CT

t_{resynch_jitter}-0.75

--

0.75

us

1) not subject of production test, specified by design

Table 22

Interface Timing Parameters

Symbol

Parameter

Values

Unit

Note /

Test Condition

Min.

Typ.

Max.

1)

CS Disable time (CS high time

between two read accesses on

different registers)

t_CSD

400

ns

1)

Read-Period for two read

accesses on the same register

(especially for COLDIAG, GLERR,

INTERR)

t_{RD_PER}

2000

400

ns

1)

CS Disable time (CS high time

between a write access and a read t_{CSD_WRRD}

access for reading back the written

value)

1) not subject of production test, specified by design

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Electrical Characteristics

Table 23

Parallel Interface

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Min.

Max.

Input Pull Up Resistance

(RD, WR, CS)

R_PU

–

50

–

kꢀ

–

Input Pull Down Resistance (ALE) R_PD

–

50

–

kꢀ

ns

–

CS setup time related to ALE

t_{CS_ALE}

14

200

ALE high duration (for

addressing)

t_{ALE_high}

t_WRlow

t_WRhigh

f_RD

WR Low duration

(for Write Data)

100

ns

WR High duration

(for Write Data)

100

ns

Read Request Frequency

0.033¹⁾

400

–

2.5

MHz

ns

repeated read access

during CS = 0

Read Request Period (1/fRD)

t_RD

30000²⁾

repeated read access

during CS = 0

RD Low duration (by Read)

AD7:AD0 Output disable time

AD0-7 Output Valid (by Read)

RD setup time

t_RDlow

t_float

200

20

ns

80

t_ADout

t_{RD_su}

t_{WR_su}

t_{RD_hd}

t_{WR_hd}

180

50

20

WR setup time

RD hold time

WR hold time

3)

WR latency time

t_lat

300

4)

RD Pad to COLDIAG, GLERR

and INTERR Registers Update

(Bits Clearing)

t_clrrdy

AD0-7 Data bus setup time

AD0-7 Data bus hold time

t_{AD_su}

t_{AD_hd}

20

60

ns

us

Time for CS = WR = ALE = 0, RD t_direct

30

= 1 until direct mode is entered

1) Minimum value to guarantee that the direct control mode is not entered, see also t_RDand t_direct

2) After 30 us the interface may enter the direct control mode, see also t_direct

3) not subject to production test, t_latdetermined by internal synchronization cycles (internal clock 10 MHz) and propagation

over CT (5 us)

4) not subject to production test, t_clrrdydetermined by internal synchronization cycles (internal clock 10 MHz)

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Electrical Characteristics

Table 24

Serial Interface

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Min.

Max.

Input Pull Up Resistance (CS)

R_PU

R_PD

–

50

–

kꢀ

–

Input Pull Down Resistance

(SCLK, SDI)

Serial Clock Frequency

Serial Clock Period (1/fSCLK)

Serial Clock High Period

Serial Clock Low Period

f_SCLK

0.06

166

83

–

6

–

MHz

ns

–

t_SCLK

t_SCLKH

t_SCLKL

ns

83

ns

CS Hold time (rising edge of SCLK t_CSH

100

ns

to rising edge of CS)

Data setup time (required time SDI t_SU

to rising edge of SCLK)

20

ns

Data hold time (rising edge of

SCLK to SDI)

t_HD

CS falling edge to SDO output

valid time

t_{CS_valid}

t_{SCLK_su}

150

CS falling edge to first rising

SCLK edge

200

SCLK falling edge to SDO output t_{SCLK_valid}

valid time

80

90

Minimum SDO Output disable time t_float

ns

New serial mode activation time t_{MS_rdy}

(MS0/MS1 change to earliest

400

noµControlleraccess

allowed during the

change¹⁾(CS = 1)

interface access)

1) not subject to production test, specified by design

Table 25

ODIS, ALE/RST Timing

Parameter

Symbol

Values

Typ.

Unit

Note /

Test Condition

Min.

Max.

Input Pull Up Resistance

(ODIS)

R_PU

–

50

–

kꢀ

–

Minimum width of ODIS-signal

t_ODISW

t_RSTW

5

–

µs

–

Minimal Duration for triggering

Reset

100

–

ALE/RST = V_CCand

CS = GND

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Electrical Characteristics

5.6

Diagnostics

Table 26

Channel Specific Diagnostics

Symbol

Parameter

Values

Typ.

1

Unit Note / Test Condition

Min.

0.73

0.1

Max.

1.3

Overload threshold

ITH_OCL

ITH_OLA1

ITH_OLA2

ITH_OLA3

I_OLI

A

R

_IADJ= 6.81 kꢀ

_OLADJ= 24,3 kꢀ

_OLADJ= 3.48 kꢀ

Active open load threshold

Inactive bypass current

Inactive open load voltage

0.35

2.4

0.55

2.9

mA

µA

V

1.8

0.9

1.4

1.9

I

_OLADJ= 200 µA¹⁾

10.0

5.75

5

21

32

Including switch leakage

V_OLI

6.7

7.8

–

Inactive open load detection, On-

threshold

VTH_OLI

5.4

5.75

V

Inactive short to V_BBdetection, On- VTH_SCV

threshold

8.4

–

9.2

0.5

10

–

V

take care when V_VBB

=

V

_VBBmin= 11 V for stability

of VBB (good buffering)

Overload filtering normal mode²⁾

t_{FILT_OCL}

ms

for the thermal shutdown

other value 50 us

Overload filtering cold lamp mode²⁾t_{FILT_COL}

–

200

6

–

ms

–

Active open load blanking²⁾

Inactive open load blanking²⁾

Inactive short to V_BBblanking²⁾

t_{blank_OLA}

t_{blank_OLI}

t_{blank_SCV}

blanking time = filter

length, other values

100us,0.5ms, 1.0ms³⁾

–

6

–

ms

blanking time = filter

length, values

100us,0.5ms, 1.0ms

the blanking time for SCV

is 6 ms but the internal

filterlength is 2 ms , other

values 100us, 0.5ms,

1.0ms

LEDy matrix driver on resistance

LEDx matrix driver on resistance

R_{ON_LEDy}

R_{ON_LEDx}

–

70

30

ꢀ

Load current 10 mA, VBB

= 24V

Load current 30

mA,VBB=24V

1) A current of 200 µA is forced out of the OLADJ Pin, this is equivalent to an nominal R_OLADJof 6 kꢀ.

R_OLADJ= V_OLADJ/ I_OLADJ= 1.2 V / 200 µA

2) all timing values defined and checked by design; test in production: structural test by SCAN-pattern plus test of internal

oscillator frequency (24 MHz + 17,5 %)

3) other values 100us, 0.5ms, 1.0ms are dynamically adapted to the switching frequency of the user

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Electrical Characteristics

5.7

Isolation and Safety-Related Specification

Measured from input terminals to output terminals, unless otherwise specified

Table 27

Isolation and Safety-Related Specification

Parameter

Symbol

Min.

Values

Typ.

---

Unit Note / Test Condition

Max.

Rated dielectric isolation voltage¹⁾V_ISO

2500

4250

–

VAC 1 - minute duration²⁾

Vpk 1s

Short term temporary overvoltage

V_IOTM

---

Minimum external air gap

(clearance)

3.5

mm Shortest distance through

air

Minimum external tracking

(creepage)

–

3.5

–

mm Shortest distance path

along body

Minimum Internal Gap

0.01

mm Isolation distance through

insulation

1) The dielectric withstand voltage class (Nennisolationsklasse) is : 500 V.

2) The parameter is not subject to production test, verified by characterization.

Approvals

UL508, CSA C22.2 NO. 14

Certificate Number: 20090514-E329661

5.8

Reliability

For Qualification Report please contact your local Infineon Technologies office!

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Electrical Characteristics

5.9

Typical Performance Characteristics

Figure 28 Typ. On-State Resistance

_ON= f(T_j), I_L= 0.6A, V_BB= 24V, V_in= high

R

Figure 29 Typ. On-State Resistance

_ON= f(V_BB), I_L= 0.6 A, I_L= 0.1 A, V_in= high

R

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Electrical Characteristics

Figure 30 Typical Initial Peak Short Circuit Current Limit vs T_j

I

_L(SCp)= f(T_j), V_BB= 24 V, output switched on with a short circuit present at the output

12

10

8

L[H]

6

4

2

0

0,100

0,200

0,300

0,400

0,500

0,600

0,700

I_L[A]

Figure 31 Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated

L = f(I_L), T_jstart= 125 °C, V_BB= 24 V, R_L= 48 ꢀ, all channels are switching simultaneously

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Electrical Characteristics

9

8

7

6

5

4

3

2

1

0

L[H]

0,100

0,200

0,300

0,400

0,500

0,600

0,700

I_L[A]

Figure 32 Maximum Allowable Load Inductance for a Single Switch Off of Each Channel, Calculated

L = f(I_L), T_jstart= 125 °C, V_BB= 24 V, R_L= 0 ꢀ, all channels are switching simultaneously

0,45

0,4

0,35

0,3

0,25

E_AS[J]

0,2

0,15

0,1

0,05

0

0,100

0,200

0,300

0,400

0,500

0,600

0,700

I_L[A]

Figure 33 Maximum Allowable Inductive Switch Off Energy, Single Pulse for Each Channel

_AS= f(I_L), T_jstart= 125 °C, V_BB= 24 V, all channels are switching simultaneously

E

Single pulse means that the thermal recovery time is sufficient so that an increase of the chip temperature is

avoided or at least limited (depends on the thermal connection of chip with PCB-board, Figure 34 -Figure 36) .

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Electrical Characteristics

D = 0.5

D = 0.2

D = 0.1

D = 0.05

D = 0.02

D = 0.01

D = 0

Figure 34 Typ. Transient Thermal Impedance 1s0p

_thJA= f(t_p) , Parameter: D = t_p/T

Z

Product simulated on a 76.2 x 114.3 x 1.5 mm 1s0p board according JEDEC JESD 51-3.

D = 0.5

D = 0.2

D = 0.1

D = 0.05

D = 0.02

D = 0.01

D = 0

Figure 35 Typ. Transient Thermal Impedance 2s2p no vias

Z_thJA= f(t_p) , Parameter: D = t_p/T

Product simulated on a 76.2 x 114.3 x 1.5 mm 2s2p board without thermal vias used in the exposed pad area

according JEDEC JESD 51-5,7.

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Electrical Characteristics

D = 0.5

D = 0.2

D = 0.1

D = 0.05

D = 0.02

D = 0.01

D = 0

Figure 36 Typ. Transient Thermal Impedance 2s2p

_thJA= f(t_p), Parameter: D = t_p/T

Z

Product simulated on a 76.2 x 114.3 x 1.5 mm 2s2p board with thermal vias connected to the first inner copper

layer in the exposed pad area according JEDEC JESD 51-5,7.

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µController Interface Registers

6

µController Interface Registers

This section presents the user registers.

Access Conventions

Table 28

Register Access Definition

Symbol

Type

Description

Read

r

The bit can be read

Read only, updated by hardware

Write

h

w

The bit is updated by the device itself (for instance: sticky bit)

The bit can be written

Presentation

The User Registers are 8-bit wide and can be accessed over either the serial or the parallel interface. The

Table 29 lists the registers of the chip. The address is 8-bit whereby the MSB is used to indicate whether it is a

write access (MSB=1) or Read access (MSB=0). The address is even i.e. the LSB is ignored (for addressing). The

default selected register is the DRIVE register for write access.

Table 29

Register Short Name

µController Interface Registers, User Registers

Register Overview

Register Long Name

Offset Address Page Number

DRIVE

Output Driver Register (rw)

00_H

66

69

71

72

74

75

76

78

DRIVE_RESYNCH

COLDIAG

GLERR

DIAGCFG

DIAG0

Output Driver Register for Resynchronization (rw) 1C_H

Collective Diagnostics Register (rh)

Global Error Register (rh)

02_H

04_H

Channel Diagnostics Configuration Register (rw) 06_H

Diagnostics Register for Channel-0 (rh)

Diagnostics Register for Channel-1 (rh)

Diagnostics Register for Channel-2 (rh)

Diagnostics Register for Channel-3 (rh)

Diagnostics Register for Channel-4 (rh)

Diagnostics Register for Channel-5 (rh)

Diagnostics Register for Channel-6 (rh)

Diagnostics Register for Channel-7 (rh)

Internal Error Register (rh)

08_H

0A_H

0C_H

0E_H

10_H

12_H

14_H

16_H

18_H

1A_H

DIAG1

DIAG2

DIAG3

DIAG4

DIAG5

DIAG6

DIAG7

INTERR

GLCFG

Global Configuration Register (rwh)

The registers are addressed wordwise.

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µController Interface Registers

6.1

User Registers

These registers can be accessed via the serial or parallel interface. The default selected register is the DRIVE

register for write access.

Update of the Diagnostics Registers

The different faults monitored at each output channel are filtered with blanking time units. They are then stored in

registers and sent over the Coreless Transformer to the µController-Interface chip with an update rate of 35 µs.

On the µController-Interface side, the diagnostics are stored in an intermediate register bank to be processed as

sticky bits: once a fault is detected (and received) the corresponding bit is set and remains set even if the fault

disappears. The bit can only be cleared once the fault is not detected anymore and a clear was requested by a

serial or parallel access (see Figure 37).

Original

diagnostic

Clear

strobe

Sticky bit

Registers - sticky_bit_def

Figure 37 Sticky Bit Operation

Output Driver Register

This register contains the command for the 8 output channels. When the pin ODIS is High, the output channels

are controlled as set by this register. When the ODIS is Low, the output channels are immediately turned off and

the contents of the DRIVE register is cleared.

DRIVE

Offset

00_H

Reset Value

00_H

Output Driver Register (rw)

7

6

5

4

3

2

1

0

SW7

rw

SW6

rw

SW5

rw

SW4

rw

SW3

rw

SW2

rw

SW1

rw

SW0

rw

Field

Bits

Type Description

SW7

SW6

7

rw

Output Driver Control for Channel 7

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

6

Output Driver Control for Channel 6

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

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µController Interface Registers

Field

Bits

Type Description

Output Driver Control for Channel 5

This bit field controls the state of the output driver.

SW5

5

rw

0_B

1_B

The channel output is inactive.

The channel output is driven.

SW4

SW3

SW2

SW1

SW0

4

3

2

1

0

Output Driver Control for Channel 4

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Control for Channel 3

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Control for Channel 2

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Control for Channel 1

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Control for Channel 0

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Register for Resynchronization

This register contains the command for the 8 output channels for resynchronization. It has to be written in case a

resynchronization of the CT-transmission is desired. Then the contents of DRIVE_RESYNCH is used for the CT-

transmission instead of the contents of DRIVE.

DRIVE_RESYNCH

Offset

1C_H

Reset Value

00_H

Output Driver Register (rw)

7

6

5

4

3

2

1

0

RW7

rw

RW6

rw

RW5

rw

RW4

rw

RW3

rw

RW2

rw

RW1

rw

RW0

rw

Field

Bits

Type Description

RW7

7

rw

Output Driver Resynchronization Control for Channel 7

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

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µController Interface Registers

Field

Bits

Type Description

Output Driver Resynchronization Control for Channel 6

This bit field controls the state of the output driver.

RW6

6

rw

0_B

1_B

The channel output is inactive.

The channel output is driven.

RW5

RW4

RW3

RW2

RW1

RW0

5

4

3

2

1

0

Output Driver Resynchronization Control for Channel 5

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Resynchronization Control for Channel 4

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Resynchronization Control for Channel 3

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Resynchronization Control for Channel 2

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Resynchronization Control for Channel 1

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

Output Driver Resynchronization Control for Channel 0

This bit field controls the state of the output driver.

0_B

1_B

The channel output is inactive.

The channel output is driven.

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µController Interface Registers

Collective Diagnostics Register

This register contains the overall diagnostics for each of the 8 output channels. Each channel-bit corresponds to

the OR-combination of the SCVx, OCLx, OLIx, OLAx and OTx-bits of the enabled diagnostic function. This

register contains the state of the channel diagnostics. On read access the internal diagnostics data is cleared and

the DIAG0,...,DIAG7 registers are updated (see Update of the Diagnostics Registers). In serial modes 0 and 1

the update of the DIAG0,...,DIAG7 is generated automatically after every access whereas in serial modes 2 and

3 as well as in parallel mode the DIAG0,...,DIAG7 registers are updated after each direct access to the COLDIAG

register.

COLDIAG

Offset

02_H

Reset Value

00_H

Collective Diagnostics Register (rh)

7

CH7

rh

6

CH6

rh

5

CH5

rh

4

CH4

rh

3

CH3

rh

2

CH2

rh

1

CH1

rh

0

CH0

rh

Field

Bits

Type Description

Overall Diagnostics for Channel 7

This bit field indicates the overall diagnostics.

CH7

CH6

CH5

CH4

CH3

CH2

CH1

7

rh

0_B

1_B

No fault is detected.

At least one failure is detected.

6

5

4

3

2

1

Overall Diagnostics for Channel 6

This bit field indicates the overall diagnostics.

0_B

1_B

No fault is detected.

At least one failure is detected.

Overall Diagnostics for Channel 5

This bit field indicates the overall diagnostics.

0_B

1_B

No fault is detected.

At least one failure is detected.

Overall Diagnostics for Channel 4

This bit field indicates the overall diagnostics.

0_B

1_B

No fault is detected.

At least one failure is detected.

Overall Diagnostics for Channel 3

This bit field indicates the overall diagnostics.

0_B

1_B

No fault is detected.

At least one failure is detected.

Overall Diagnostics for Channel 2

This bit field indicates the overall diagnostics.

0_B

1_B

No fault is detected.

At least one failure is detected.

Overall Diagnostics for Channel 1

This bit field indicates the overall diagnostics.

0_B

1_B

No fault is detected.

At least one failure is detected.

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µController Interface Registers

Field

Bits

Type Description

rh Overall Diagnostics for Channel 0

This bit field indicates the overall diagnostics.

CH0

0

0_B

1_B

No fault is detected.

At least one failure is detected.

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µController Interface Registers

Global Error Register

This register contains the overall status of the IC parameters monitored during system operation. The bits are

routed to the ERR pin as well (see Table 3). The UV and MV bits are reset to High during UVLO. In some operation

modes, the register needs to be read to clear these bits and release the ERR pin (see “Update of GLERR,

INTERR-Reg”). The CF-bit is the OR-combination of COLDIAG bits.

GLERR

Offset

04_H

Reset Value

16_H

Global Error Register (rh)

7

6

5

4

3

RES

r

2

1

0

Vers_3

Vers_2

Vers_1

Vers_0

UV

rh

MV

rh

CF

rh

r

Field

Bits

7

Type Description

Vers_3

Vers_2

Vers_1

Vers_0

RES

r

Actual :”0”

Actual :”1”

Actual :”0”

Reserved

6

5

4

3

Returns 0 when read.

UV

MV

CF

2

1

0

rh

VBB Undervoltage

This bit field indicates if an undervoltage condition has been detected at VBB.

0_B

1_B

No undervoltage detected.

Undervoltage detected.

VBB Missingvoltage

This bit field indicates if a missingvoltage condition has been detected at VBB.

0_B

1_B

No missingvoltage detected.

Missingvoltage detected.

Common Diagnostics Fault

This bit field is the OR-combination of all bits of the COLDIAG register.

0_B

1_B

No fault is detected.

At least one failure is detected.

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µController Interface Registers

Channel Diagnostics Configuration Register

This register enables the diagnostics for each channel and selects whether the channel collective diagnostic bit is

updated in the COLDIAG register (and as a consequence in the CF-bit field of the GLERR register and at the ERR

pin).

DIAGCFG

Offset

06_H

Reset Value

FF_H

Channel Diagnostics Configuration Register

(rw)

7

DIAGEN7

rw

6

DIAGEN6

rw

5

DIAGEN5

rw

4

3

DIAGEN3

rw

2

DIAGEN2

rw

1

DIAGEN1

rw

0

DIAGEN0

rw

DIAGEN4

rw

Field

Bits

Type Description

Enables Diagnostics for Channel 7

This bit field enables all the channel diagnostics.

DIAGEN7

DIAGEN6

DIAGEN5

DIAGEN4

DIAGEN3

DIAGEN2

DIAGEN1

7

rw

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

6

5

4

3

2

1

Enables Diagnostics for Channel 6

This bit field enables all the channel diagnostics.

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

Enables Diagnostics for Channel 5

This bit field enables all the channel diagnostics.

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

Enables Diagnostics for Channel 4

This bit field enables all the channel diagnostics.

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

Enables Diagnostics for Channel 3

This bit field enables all the channel diagnostics.

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

Enables Diagnostics for Channel 2

This bit field enables all the channel diagnostics.

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

Enables Diagnostics for Channel 1

This bit field enables all the channel diagnostics.

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

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µController Interface Registers

Field

Bits

Type Description

rw Enables Diagnostics for Channel 0

This bit field enables all the channel diagnostics.

DIAGEN0

0

0_B

1_B

All the channel diagnostics are disabled.

The channel diagnostics are enabled and updated in the COLDIAG register.

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µController Interface Registers

Diagnostics Registers for Channel-x

These registers contain the individual diagnostics bits. The bit field LEDGx is not used in the COLDIAG register

(and as a consequence in the CF-bit and at the ERR pin). All bits are sticky (see Update of the Diagnostics

Registers). The diagnostics are enabled with the DIAGCFG register.

DIAG0

Offset

08_H

Reset Value

00_H

Diagnostics Register for Channel-0 (rh)

7

RES

r

6

RES

r

5

LEDGx

rh

4

SCVx

rh

3

OCLx

rh

2

OLAx

rh

1

OLIx

rh

0

OTx

rh

Field

Bits

Type Description

RES

7

r

Reserved

returns 0 if read.

RES

6

5

r

Reserved

returns 0 if read.

LEDGx

rh

Gated LED Drive Information of Channel x (Active Mode only)

This bit field indicates that the led of this channel is gated due to overcurrent or

over-temperature conditions.

0 : led not gated

1 : led gated

SCVx

OCLx

4

3

rh

Short Circuit to VBB at Channel x (Inactive Mode only)

This bit field indicates that a short circuit to VBB has been detected.

0_B

1_B

No short circuit to VBB detected.

A short circuit to VBB has been detected.

Overcurrent at Channel x (Active Mode only)

This bit field indicates that an overload condition has been detected and that the

current is being limited.

0_B

1_B

No overcurrent detected.

An overcurrent has been detected and limited.

OLAx

OLIx

OTx

2

1

rh

Open Load / Wire Break at Channel x (Active Mode)

This bit field indicates that an open load condition has been detected.

0_B

1_B

No open load detected.

An open load condition has been detected.

Open Load / Wire Break at Channel x (Inactive Mode)

This bit field indicates that an open load condition has been detected.

0_B

1_B

No open load detected.

An open load condition has been detected.

0

Over-temperature at Channel x (Active Mode Only)

This bit field indicates that an over-temperature condition has been detected.

0_B

1_B

No over-temperature detected.

An over-temperature has been detected.

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µController Interface Registers

Other Channel Diagnostics Registers

The other channel diagnostics registers in the table below have the same layout as DIAG0.

Their names and offset addresses are listed below:

Table 30

Diagnostics Registers for Channel 1-7

Register Short Name

DIAG1

Register Long Name

Offset Address Reset Value

Diagnostics Register for Channel-1 (rh)

Diagnostics Register for Channel-2 (rh)

Diagnostics Register for Channel-3 (rh)

Diagnostics Register for Channel-4 (rh)

Diagnostics Register for Channel-5 (rh)

Diagnostics Register for Channel-6 (rh)

Diagnostics Register for Channel-7 (rh)

0A_H

0C_H

0E_H

10_H

12_H

14_H

16_H

00_H

DIAG2

DIAG3

DIAG4

DIAG5

DIAG6

DIAG7

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ISO2H823V2.5

µController Interface Registers

Internal Error Register

This register contains the status of internal errors monitored for safe IC operation. The TE, W4P, ALLOFF bits are

sticky and routed out to the ERR pin (according to the Table 3). The bits OTP and LAMP are volatile i.e. are

updated every 35 µs. Sticky bits are cleared every time the INTERR register is accessed or by every serial access

in mode 0 and 1.

INTERR

Offset

18_H

Reset Value

07_H

Internal Error Register (rh)

7

RES

r

6

OTC

rh

5

RES

r

4

OTP

rh

3

LAMP

rh

2

ALLOFF

rh

1

W4P

rh

0

TE

rh

Field

Bits

Type Description

RES

7

r

Reserved

returns 0 if read.

OTC

6

rh

Overtemperature Common (Volatile)

This bit field indicates that an overtemperature or overcurrent condition of at least

one of the channels has been detected. Ored LEDGx-values.

0_B

1_B

No overtemperature or overcurrent has been detected.

An overtemperature or overcurrent condition has been detected.

RES

OTP

5

4

r

Reserved

returns 0 if read.

rh

Overtemperature Package (Volatile)

This bit field indicates that an overtemperature of the package has been detected.

0_B

1_B

No package overtemperature detected.

An overtemperature in the package has been detected.

LAMP

3

2

rh

Cold Lamp Detected (Volatile)

This bit field indicates that at least a cold lamp behaviour has been detected at one

output channel.

0_B

1_B

No cold lamp behaviour detected.

At least one load at the output channels behaves as a cold lamp.

ALLOFF

All Outputs Channels are Switched Off (Sticky)

This bit field indicates that all the output channels have been switched off due to

an internal error, an over-temperature, the ODIS pin or the data of the DRIVE

(feedback from Power Chip).

0_B

1_B

The ouput channels are enabled and controlled by the DRIVE register.

The ouptut channels are switched off.

W4P

1

rh

Wait for Power Chip (Sticky)

This bit field indicates that the Power Chip is correctly supplied and ready for

operation.

0_B

1_B

Power Chip is ready.

Power Chip is not ready because of insufficient voltage or long transmission

error.

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µController Interface Registers

Field

Bits

Type Description

rh Transmission Error (Sticky)

TE

0

This bit field indicates a transmission error over the galvanic isolation detected

either from the Process Side or from the µController-Interface

0_B

1_B

No transmission error is detected.

Transmission error has occured.

Datasheet

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µController Interface Registers

Global Configuration Register

This register configures some extended functionalities of the chip.

GLCFG

Offset

1A_H

Reset Value

00_H

Global Configuration Register (rwh)

7

FRZSC

rw

6

RESYN

rw

5

RSTOFF

rw

4

LEDON

rw

3

2

LEDGOFF

rw

1

OLOFF

rw

0

RES

rw

SWRST

rwh

Field

Bits

Type Description

FRZSC

7

rw

Selection of Isochronous Mode for Diagnostics

This bit field enables the isochronous mode for diagnostics. The entry is totally

ignored when RESYN = 1.

0_B

1_B

Diagnostics are treated independently of SYNC-level

Diagnostics are frozen with falling edge of SYNC and released with rising

edge. During SYNC = 0 DIAG0,..,DIAG7 and COLDIAG are not updated. But

read bits in COLDIAG can be reset.

RESYN

6

rw

Resynchronization of CT-Transmission

This bit field enables the resychronization of CT-transmission.

0_B

1_B

functionality of SYNC is as defined by bit FRZSC.

SYNC-pin is used for resynchronization of CT-transmission

Note: It is not possible to select RESYN = 1 and to use isochronous mode

for drive signals or/and diagnostics at the same time. That means

resynchronization and isochronous mode of driver information and

diagnostics at the same time is not possible. Edges on SYNC are used

solely for resynchronization. In the following the driver information can

be only transferred when SYNC = 1 when RESYN is set to “1”. A

negative pulse on SYNC initializes the resynchronization.

RSTOFF

LEDON

5

4

rw

HW Reset of ALE Pin Disabled

This bit field disables the external reset.

0_B

1_B

The HW reset at the ALE pin is enabled (default).

The HW reset is disabled.

LED Matrix Enabled

This bit field enables the LED Matrix in serial mode. In this case the HW reset

cannot be used (activation of HW Reset is ignored).

0_B

1_B

The LED matrix is disabled (default).

The LED matrix is enabled in serial mode.

RES

3

2

rw

Reserved

Must be set to “0”

LEDGOFF

LEDG Report Disabled

This bit field disables the report of the LEDGx-information.

0_B

1_B

The LEDGx diagnostic is enabled (default).

The LEDGx diagnostic is disabled and not reported in the DIAG0,..,DIAG7

registers.

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ISO2H823V2.5

µController Interface Registers

Field

Bits

Type Description

OLOFF

1

rw

Open-Load Diagnostic Disabled

This bit field disables the monitoring of the Open-Load diagnostic OLAx and OLIx.

0_B

1_B

The Open-Load diagnostic is enabled and updated in the DIAG0,..,DIAG7

registers (default).

The Open-Load diagnostic is disabled and do not appear in the

DIAG0,..,DIAG7 registers.

SWRST

0

rwh

Soft Reset

This bit field triggers the clear of the user registers and restarts the CT

transmission. After setting the soft reset, this bit field will clear itself.

0_B

1_B

No reset is generated.

A clear of the user registers is generated.

Datasheet

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ISO2H823V2.5

Package : Outlines and Marking Pattern

7

Package : Outlines and Marking Pattern

Figure 38 PG-VQFN-70-2 (Plastic (Green) Very Thin Profile Quad Flat Non Leaded Package)

Datasheet

80

Revision 2.0, 2015-02-12

ISOFACE™

ISO2H823V2.5

Package : Outlines and Marking Pattern

Information of Marking Pattern:

Infineon

ISOFACE ^TM

ISO2H823V2.5

Lotnumber

Datecode

Figure 39 Marking Pattern

For further information on alternative packages, please visit our website:

http://www.infineon.com/packages.

Dimensions in mm

Datasheet

81

Revision 2.0, 2015-02-12

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	ISO2H823V2.5
厂家：	Infineon
描述：	Galvanic Isolated 8 Channel High-Side Switch
文件：	总82页 (文件大小：2257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISO2H823V2.5 [INFINEON]

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