ITS4090Q-EP-D [INFINEON]
The ITS4090Q-EP-D is a 90mΩ Quad Channel Smart Hi;
| 型号： | ITS4090Q-EP-D |
| 厂家： | 
Infineon |
| 描述： | The ITS4090Q-EP-D is a 90mΩ Quad Channel Smart Hi |
| 文件： | 总42页 (文件大小：1362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Industrial PROFET™
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
1
Overview
Features
•
Quad channel Smart High-Side Power Switch with integrated protection
and diagnosis
•
•
•
•
•
•
•
•
•
•
•
Maximum RDS(ON) 90 mΩ per channel at Tj = 25°C
Nominal output current capability up to 750 mA
Low and accurate current limitation: 1.5 A (± 20 %)
Extended supply voltage range up to 45 V
All control inputs 24 V capable and support direct interface to optocouplers
All control inputs 3.3 V and 5 V logic level compatible
4 kV electrostatic discharge protection (ESD)
Optimized electromagnetic compatibility
Very small, thermally enhanced TSDSO-14 package
Device robustness validated by extended qualification according to JEDEC standard “JESD47J”
Green product (RoHS compliant)
Potential applications
•
•
•
•
•
Digital output modules (PLC applications, factory automation)
Industrial peripheral switches and power distribution
Switching resistive, inductive and capacitive loads in harsh industrial environments
Replacement for electromechanical relays, fuses and discrete circuits
Most suitable for loads that require a precise current limit
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC JESD47J.
Data Sheet
1
Rev. 1.0
2018-06-14
www.infineon.com/industrial-profet
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Overview
Description
The ITS4090Q-EP-D is a 90 mΩ Quad Channel Smart High-Side Power Switch providing integrated protection
functions and a diagnosis feedback. With four channels capable of currents of more than 500 mA each, very
low typical RDS(ON) values of 140 mΩ at Tj = 125°C and the small PG-TSDSO-14 exposed pad package it
combines high flexibility with minimum space requirements. The exposed pad of the thermally enhanced PG-
TSDSO-14 package allows a very efficient heat transfer from the device to inner layers of the PCB by means of
thermal vias. The power transistors are built by N-channel vertical power MOSFETs (DMOS) with charge pump.
The ITS4090Q-EP-D is specifically designed to switch resistive, inductive or capacitive loads in harsh industrial
environments. The ITS4090Q-EP-D is equipped with essential protection features that make it extremely
robust. Diagnostic information can be read out via the STATUS output (ST). The four channel device can be
controlled with four separate input pins. Due to their high voltage capability the input pins can be directly
interfaced to optocouplers without additional external components.
Diagnostic Functions
•
•
•
•
Short circuit to ground (overload) indication
Overtemperature switch off indication
Stable diagnostic signal during short circuit and overtemperature shutdown
Intelligent channel fault detection system
Protection Functions
•
•
•
•
•
•
Stable behavior during undervoltage
Overtemperature protection with restart after cooling down phase
Overload- and short circuit protection
Reverse polarity / inverse current protection with external components
Overvoltage protection with external components
Loss of ground protection
The qualification of this product is based on JEDEC JESD47J and may reference existing qualification results
of similar products. Such referring is justified by the structural similarity of the products. The product is not
qualified and manufactured according to the requirements of Infineon Technologies with regard to
automotive and/or transportation applications. Infineon Technologies administrates a comprehensive
quality management system according to the latest version of the ISO9001 and IATF 16949.
The most updated certificates of the ISO9001 and IATF 16949 are available at
www.infineon.com/cms/en/product/technology/quality/
Type
Package
Marking
ITS4090Q-EP-D
PG-TSDSO-14
ITS4090Q
Data Sheet
2
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment PG-TSDSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions PG-TSDSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Voltage and Current Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance Characteristics Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
5
Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output ON-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Turn ON/OFF Characteristics with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Inverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics: Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical Performance Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.5
5.6
6
6.1
6.2
6.2.1
6.3
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Loss of Ground Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Temperature Limitation in the Power DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Electrical Characteristics: Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical Performance Characteristics Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4
6.4.1
6.4.2
6.5
6.6
7
Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Electrical Characteristics: Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Channel Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical Performance Characteristics Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1
7.2
7.3
8
8.1
8.2
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Data Sheet
3
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
8.3
8.4
Electrical Characteristics: Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical Performance Characteristics Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
9.1
9.2
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10
11
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Sheet
4
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Block Diagram
2
Block Diagram
ITS4090Q-EP-D
VS
Voltage Sensor
Bias
Over
Temperature
Gate control
Driver
Logic
&
Charge Pump
3
IN1
ESD
Protection
Over Current
Switch Limit
Clamp for
Inductive Loads
14
OUT1
Channel 1
VS
4
IN2
Control and Protection Circuitry
Equivalent to Channel 1
5
6
12
10
8
ST
OUT2
OUT3
OUT4
Channel 2
VS
IN3
Control and Protection Circuitry
Equivalent to Channel 1
Channel 3
VS
7
IN4
Control and Protection Circuitry
Equivalent to Channel 1
Channel 4
PG-TSDSO-14
2
GND
Figure 1
Block Diagram: ITS4090Q-EP-D
Data Sheet
5
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment PG-TSDSO-14
1
2
3
4
5
6
7
14
13
12
11
10
9
TM
GND
IN1
OUT1
N.C.
OUT2
N.C.
IN2
ST
OUT3
N.C.
IN3
IN4
8
OUT4
Figure 2
Pin Configuration PG-TSDSO-14
3.2
Pin Definitions and Functions PG-TSDSO-14
Pin
1
Symbol Function
TM
Test Mode Entry; must be connected to device GND (pin 2) via resistor 1)
2
GND
IN1
IN2
ST
Ground pin
3
INput channel 1; Input signal for channel 1 activation, Active “High”
INput channel 2; Input signal for channel 2 activation, Active “High”
4
5
STatus Feedback; Active “Low”, connect with external pull-up resistor to
“High”
6
IN3
INput channel 3; Input signal for channel 3 activation, Active “High”
INput channel 4; Input signal for channel 4 activation, Active “High”
OUTput 4; Protected high side power output channel 4
OUTput 3; Protected high side power output channel 3
OUTput 2; Protected high side power output channel 2
OUTput 1; Protected high side power output channel 1
Not Connected
7
IN4
8
OUT4
OUT3
OUT2
OUT1
N.C.
VS
10
12
14
9,11,13
Exposed Pad
Voltage Supply
1) To ensure proper functionality of the device the TM pin must be connected to device ground. In order to protect the
pin furthermore in case of reverse polarity conditions or ground shifts the TM pin needs to be connected with a serial
resistor to device ground. The recommended value for this resistor is 2.2 kΩ.
Data Sheet
6
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Pin Configuration
3.3
Voltage and Current Definitions
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
IS
VS
IOUT1
IIN1
IN1
IN2
ST
OUT1
OUT2
IOUT2
IIN2
IST
ITS4090Q-EP-D
IOUT3
IIN3
IN3
IN4
OUT 3
OUT 4
IOUT4
IIN4
GND
IGND
Figure 3
Voltage and Current Definitions
Data Sheet
7
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings 1)
Tj = -40°C to 150°C, positive current flowing into pin; (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
Supply Voltages
Supply voltage
VS
-0.3 –
45
28
V
V
–
P_4.1.1
P_4.1.3
Reverse polarity voltage
-VS(REV)
0
–
2) t < 2 min
TA = 25°C
RL ≥ 25 Ω
ZGND = 150 Ω Power Resistor
Supply voltage for short
circuit protection
VS(SC)
0
–
36
V
–
P_4.1.4
Input Pins
Voltage at INPUT pins
Current through INPUT pins
STATUS Pin
VIN
IIN
-0.3 –
-2
45
2
V
VS > VIN
–
P_4.1.5
P_4.1.6
–
mA
Voltage at ST pin
VST
IST
-0.3 –
45
2
V
VS > VST
–
P_4.1.7
P_4.1.8
Current through ST pin
Power Stage
-2
–
mA
Power dissipation (DC)
PTOT
–
–
–
–
1.8
W
3) TA = 85°C
Tj < 150°C
P_4.1.10
P_4.1.11
Maximum energy dissipation EAS
Single pulse (one channel)
410 mJ IL = 0.5 A
Tj = 150°C
VS = 28 V
Voltage at power transistor
Currents
VDS
–
–
–
65
V
–
P_4.1.12
Current through ground pin
I GND
I GND
-20
20
–
mA
–
P_4.1.13
P_4.1.21
Temporary reverse current
through ground pin to VS
-200 –
mA t < 2 min
Temperatures
Junction temperature
Storage temperature
ESD Susceptibility
ESD susceptibility (all pins)
Tj
-40
-55
–
–
150 °C
150 °C
–
–
P_4.1.14
P_4.1.15
TSTG
VESD_HBM -2
–
–
2
4
kV HBM4)
kV HBM4)
P_4.1.16
P_4.1.17
ESD susceptibility OUT Pin vs. VESD_HBM -4
GND and VS connected
Data Sheet
8
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
Table 1
Tj = -40°C to 150°C, positive current flowing into pin; (unless otherwise specified)
Absolute Maximum Ratings 1) (cont’d)
Parameter
Symbol
Values
Unit Note or Test Condition
Number
Min. Typ. Max.
ESD susceptibility
VESD_CDM -500 –
VESD_CDM -750 –
500
750
V
V
CDM5)
CDM5)
P_4.1.18
P_4.1.19
ESD susceptibility pin
(corner pins)
1) Not subject to production test; specified by design.
2) Reverse polarity protection can only be achieved in combination with external components: to limit the current
through the GND-path a 150 Ω power resistor needs to be placed between GND-pin and ground. An alternative
solution is to use a reverse current diode in the GND-path to realize reverse polarity protection. In this case placing a
resistor in the range of ≥ 27 Ω in series to the diode is recommended to improve at the same time the overvoltage
capability in case of overvoltage pulses on VS.
3) This parameter serves as reference for the thermal budget: it illustrates the power dissipation that can be handled
by the device in an application under the given boundary conditions before exceeding the maximum rating of Tj
when assuming a RthJA value for a thermally well dimensioned PCB connection like given in the JEDEC case P_4.3.3
in Chapter 4.4. As RthJA depends strongly on the applied PCB and layout of any individual application the actual
achievable values of PTOT can either be lower or higher depending on the given application.
4) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001(1.5 kΩ, 100 pF).
5) ESD susceptibility, Charged Device Model “CDM” JEDEC JESD22-C101.
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions
are not designed for continuous repetitive operation.
Data Sheet
9
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Tj = -40°C to 150°C; (unless otherwise specified)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Nominal operating voltage
Extended operating voltage
VS(NOM)
VS(EOP)
8
5
24
–
36
45
V
V
VS > VIN
1) VS > VIN
P_4.2.1
P_4.2.2
IOUT = 500 mA
VDS < 0.5 V
Minimum functional supply voltage
during power-up
VS(OP)_MIN
–
3
4.3
5
V
V
VS > VIN
P_4.2.3
P_4.2.4
IOUT = 0 A to
VDS < 0.5 V
(VS rising;
powering up)
Undervoltage shutdown
VS(UV)
3.5 4.1
VS > VIN
from VDS < 0.5 V
to IOUT = 0 A
(VS dropping
from functional
range)
1)
Undervoltage shutdown hysteresis
VS(UV)_HYS
IGND_1
–
–
850
2
–
mV
–
P_4.2.5
P_4.2.6
Operating current
One channel active
2.8 mA VS = VIN = 24 V
Device in RDS(ON)
Operating current
All channels active (Tj ≤ 25°C)
IGND_4
IGND_4_150
Tj
–
5.2 6.8 mA VS = VIN = 24 V
Device in RDS(ON)
P_4.2.9
P_4.2.7
P_4.2.8
Tj ≤ 25°C
Operating current
All channels active (Tj = 150°C)
–
4.8 6.0 mA VS = VIN = 24 V
Device in RDS(ON)
Tj = 150°C
Junction Temperature
-40
–
150 °C
–
1) Not subject to production test; specified by design.
Note:
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Data Sheet
10
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4.3
Typical Performance Characteristics Operating Current
Typical Performance Characteristics
Operating Current IGND versus
Junction Temperature Tj
Operating Current IGND versus
Supply VoltageVS
7
7
1 channel active
VS = 24 V
Tj = 25 °C
2 channels active
3 channels active
4 channels active
6
5
4
3
2
1
6
5
4
3
2
1 channel active
1
0
2 channels active
3 channels active
4 channels active
0
−50
0
50
100
150
0
10
20
30
40
Tj [°C]
VS [V]
Data Sheet
11
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4.4
Thermal Resistance
Table 3
Thermal Resistance 1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Junction to exposed pad soldering point RthJC
–
–
–
–
–
–
–
–
–
–
K/W –
P_4.3.1
P_4.3.3
P_4.3.4
P_4.3.5
P_4.3.6
1
2)
Junction to ambient
All channels active
RthJA_2s2pvia
K/W
–
–
–
–
36
119
54
44
3)
Junction to ambient
All channels active
RthJA_1s0p
K/W
4)
Junction to ambient
All channels active
RthJA_1s0p_300mm
RthJA_1s0p_600mm
K/W
5)
Junction to ambient
All channels active
K/W
1) Not subject to production test; specified by design.
2) Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip
+ package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, footprint;
The product (chip + package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 1 × 70 µm Cu.
4) Specified RthJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, 300 mm;
The product (chip + package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 1 × 70 µm Cu.
5) Specified RthJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, 600 mm;
The product (chip + package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 1 × 70 µm Cu.
1000
Thermal Impedance (one channel active; PDISSIPATION = 0.065W)
100
10
1
0,1
Rth-JA (footprint only)
0,01
Rth-JA (1s0p_300mm)
0,001
Rth-JA (1s0p_600mm)
0,0001
Rth-JA (2s2p-via)
0,00001
1,00E-09
1,00E-07
1,00E-05
time [s]
1,00E-03
1,00E-01
Figure 4
Thermal Impedance (short time scale; one channel active)
Data Sheet
12
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
140
Thermal Impedance (one channel active; PDISSIPATION = 0.065W)
120
100
80
60
40
20
0
Rth-JA (footprint only)
Rth-JA (1s0p_300mm)
Rth-JA (1s0p_600mm)
Rth-JA (2s2p-via)
1,00E-05
1,00E-03
1,00E-01
time [s]
1,00E+01
1,00E+03
Figure 5
Thermal Impedance (long time scale; one channel active)
Data Sheet
13
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5
Power Stage
The power stages are built using an N-channel vertical power MOSFET (DMOS) with charge pump.
5.1
Output ON-state Resistance
The ON-state resistance RDS(ON) of the power stage depends on supply voltage as well as on junction
temperature Tj. Figure 6 shows the influence of temperature on the typical ON-state resistance. The behavior
of the power stage in reverse polarity condition is described in Chapter 6.3.
180
160
140
120
100
80
60
40
20
0
−50
0
50
100
150
T [°C]
j
Figure 6
Typical ON-state Resistance
5.2
Turn ON/OFF Characteristics with Resistive Load
A “High” signal at the input pin (see Chapter 8) causes the power DMOS to switch ON with a dedicated slope,
which is optimized in terms of EMC emission.
Figure 7 shows the typical timing when switching a resistive load.
IN
VIN_H
VIN_L
t
VOUT
dV/dt ON
dV/dt OFF
tON
90% VS
70% VS
tOFF_delay
30% VS
10% VS
tON_delay
tOFF
t
Switching times.vsd
Figure 7
Switching a Resistive Load Timing
Data Sheet
14
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5.3
Inductive Load
5.3.1
Output Clamping
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device by
avalanche due to high voltage drop over the power stage a voltage clamp mechanism ZDS(AZ) is implemented
that limits negative output voltage to a certain level (VS - VDS(AZ)). The clamping mechanism allows in addition
a fast demagnetization of inductive loads because during the phase of active clamping the power is dissipated
to a great extent rapidly inside the switch. On the other hand the power dissipated inside the switch while
switching off inductive loads can cause considerable stress to the device. Therefore the maximum allowed
energy at a given current (and by this also the inductance) is limited. In Figure 8 and Figure 9 the basic
principle of active clamping as well as simplified waveforms when switching off inductive loads are illustrated.
ITS4090Q-EP-D
VS
VS
VDS
Bias
ZDS(AZ)
Driver
Logic
INx
OUTx
IL
L, RL
VÎN
GND
VOUT
ZGND
Figure 8
Output Clamp
IN
t
VOUT
VS
t
VS-VDS(AZ)
IL
t
Switching an inductance.vsd
Figure 9
Switching an Inductive Load Timing
Data Sheet
15
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5.3.2
Maximum Load Inductance
During demagnetization of inductive loads, the following energy must be dissipated by the ITS4090Q-EP-D.
This energy can be calculated by help of the following equation:
VS – VDS(AZ)
--------------------------------
RL
RL × IL
L
RL
⎛
⎞
⎠
------
E = VDS(AZ)
×
×
× ln 1 –
+ IL
(5.1)
--------------------------------
VS – VDS(AZ)
⎝
Following equation gets simplified under the assumption of RL = 0 Ω:
VS
1
2
2
⎛
⎞
⎠
--
E = × L × I × 1 –
(5.2)
--------------------------------
VS – VDS(AZ)
⎝
The energy, which may be converted into heat, is limited by the thermal design of the component. See
Figure 10 for the maximum allowed energy dissipation as a function of the load current for a singular pulse
event on one channel.
450
400
350
300
250
200
150
100
50
0
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
ILoad [A]
Figure 10 Maximum Energy Dissipation Single Pulse for a Single Channel (Tj = 150°C, VS = 28 V)
5.4
Inverse Current Capability
In case of inverse current, meaning a voltage VINV at the OUTput higher than the supply voltage VS, a current
IINV will flow from output to VS pin via the body diode of the power transistor (please refer to Figure 11).
Channels that are active (ON-state) by the time when the inverse current condition appears will remain active
and their output stage will follow the state of the corresponding IN pin, which means that the channel can be
switched off during inverse current condition. Channels that are inactive (OFF-state) by the time when the
inverse current condition appears will remain inactive regardless of the state of the corresponding IN pin. If
during an inverse current condition the IN-pin of a channel is set from “Low” to “High” in order to activate the
channel, the output stage of the channel is kept OFF until the inverse current disappears. For all cases the
current IINV should not be higher than IL(INV). Please note that during inverse current condition the protection
functions of concerned channels are not available.
Data Sheet
16
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
VS
ITS4090Q-EP-D
Bias
Gate
INx
Driver
VINV
Inv.
Comp
Device
Logic
OUTx
IL(INV)
GND
ZGND
Figure 11 Inverse Current Circuitry
IL(INV)
Inverse Current Event
t
VIN
t
Channel
State
„ON“
„OFF“
„ON“
„OFF“
t
Figure 12 Inverse Current event: channel in OFF-state (channel remains off for duration of inverse
current event)
Data Sheet
17
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
IL(INV)
Inverse Current Event
t
t
VIN
Channel
State
„ON“
„OFF“
„ON“
„OFF“
„OFF“
t
Figure 13 Inverse Current event: channel in ON-state (output not influenced but can be switched off)
5.5
Electrical Characteristics: Power Stage
Table 4
Electrical Characteristics: Power Stage
VS = 8 V to 36 V, Tj = -40°C to 150°C (unless otherwise specified).
Typical values are given at VS = 24 V, Tj = 25°C
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
ON-state resistance per
channel (Tj = 25°C)
RDS(ON)
–
90
mΩ
mΩ
mΩ
ILx = 0.5 A
P_5.5.18
VIN = 4.5 V
Tj = 25°C
2)
ON-state resistance per
channel (Tj = 125°C)
RDS(ON)_125
–
–
140
–
–
I
= 0.5 A
P_5.5.19
P_5.5.1
Lx
VIN = 4.5 V
Tj = 125°C
ON-state resistance per
channel (Tj = 150°C)
RDS(ON)_150
180
ILx= 0.5 A
VIN = 4.5 V
Tj = 150°C
Nominal load current
per channel
IL(NOM)1
VDS(AZ)
–
–
750
75
mA
V
1) 2) Tj < 150°C
P_5.5.2
P_5.5.5
Drain to source clamping
voltage
65
70
IDS = 5 mA
VDS(AZ) = [VS - VOUT]
2)
Output leakage current per
channel
IL(OFF)
–
–
–
0.1
1
0.5
5
µA
µA
A
V floating
P_5.5.6
P_5.5.4
P_5.5.7
IN
VOUT = 0 V
Tj ≤ 85°C
Output leakage current per
channel
IL(OFF)_150
VIN floating
VOUT = 0 V
Tj = 150°C
2) 3) VS < VOUTX
t < 2 min
Inverse current capability
IL(INV)
2.2
–
Data Sheet
18
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Table 4
Electrical Characteristics: Power Stage (cont’d)
VS = 8 V to 36 V, Tj = -40°C to 150°C (unless otherwise specified).
Typical values are given at VS = 24 V, Tj = 25°C
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Slew rate (switch on)
30% to 70% of VS
ΔV/ΔtON
–
1.75
–
V/µs RL = 47 Ω
P_5.5.8
VS = 24 V
Slew rate (switch off)
70% to 30% of VS
-ΔV/ΔtOFF
–
1.75
25
25
0
–
V/µs RL = 47 Ω
P_5.5.9
VS = 24 V
Turn-ON time to VOUT = 90% VS tON
–
75
75
40
45
45
µs
µs
µs
µs
µs
RL = 47 Ω
VS = 24 V
P_5.5.11
P_5.5.12
P_5.5.13
P_5.5.14
P_5.5.15
Turn-OFF time to VOUT = 10% tOFF
VS
–
RL = 47 Ω
VS = 24 V
Turn-ON / OFF matching
tOFF - tON
ΔtSW
-40
–
RL = 47 Ω
VS = 24 V
Turn-ON time to VOUT = 10% tON_delay
VS
13
13
RL = 47 Ω
VS = 24 V
Turn-OFF time to VOUT = 90% tOFF_delay
VS
–
RL = 47 Ω
VS = 24 V
1) This parameter describes the nominal load capability per channel from an electrical point of view respecting a
maximum Tj ≤ 150°C. Please note that depending on the individual thermal design of a real application (and a
potentially insufficient thermal budget resulting hereof) additional restrictions for IL(NOM) may occur for pure thermal
reasons in order not to exceed the maximum allowed junction temperature Tj = 150°C. The latter needs to be
considered especially for cases where all four channels are operating simultaneously under high load conditions and
at high ambient temperature TAMB. For further details about potential derating of the nominal load current due to
thermal restrictions please refer to “Thermal Considerations” on Page 38.
2) Not subject to production test; specified by design.
3) Please note that during inverse current condition the protection features are not operational.
Data Sheet
19
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5.6
Typical Performance Characteristics Power Stage
Typical Performance Characteristics
ON-State Resistance RDSON versus
Junction Temperature Tj
Leakage Current per channel IL(OFF) versus
Junction Temperature Tj
180
2
VS = 24 V
1.8
VS = 24 V; ILoad = 0.5A
160
1.6
1.4
1.2
1
140
120
100
80
0.8
0.6
0.4
0.2
0
60
40
20
0
−50
0
50
100
150
−50
0
50
100
150
Tj [°C]
Tj [°C]
Output Clamp Voltage VDS(AZ) versus
Junction Temperature Tj
75
74
73
72
71
70
69
68
67
66
65
CH 1
CH 2
CH 3
CH 4
−50
0
50
100
150
Tj [°C]
Data Sheet
20
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Turn-ON time tON to VOUT = 90% versus
Junction Temperature Tj
Turn-OFF time tOFF to VOUT = 90% versus
Junction Temperature Tj
70
70
ILoad = 10mA
ILoad = 10mA
ILoad = 0.5A
ILoad = 0.8A
VS = 24V
VS = 24V
ILoad = 0.5A
ILoad = 0.8A
60
50
40
30
20
10
0
60
50
40
30
20
10
0
−50
0
50
100
150
−50
0
50
100
150
Tj [°C]
Tj [°C]
Turn-ON delay time tON_delay to VOUT = 10% versus
Junction Temperature Tj
Turn-OFF time delay tOFF_delay to VOUT = 10% versus
Junction Temperature Tj
50
50
VS = 24V
VS = 24V
ILoad = 10mA
ILoad = 0.5A
ILoad = 0.8A
ILoad = 10mA
ILoad = 0.5A
ILoad = 0.8A
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
−50
0
50
100
150
−50
0
50
100
150
Tj [°C]
Tj [°C]
Data Sheet
21
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Turn-ON time tON to VOUT = 90% versus
Load Current I Load
Turn-OFF time tOFF to VOUT = 90% versus
Load Current I Load
70
70
60
50
40
30
20
Tj = −40 °C
Tj = −40 °C
Tj = 25 °C
Tj = 150 °C
Tj = 25 °C
60
50
40
30
20
10
0
Tj = 150 °C
10
VS = 24 V
0.2
VS = 24 V
0.2
0
0
0.4
0.6
0.8
0
0.4
0.6
0.8
ILoad [A]
ILoad [A]
Turn-ON delay time tON_delay to VOUT = 10% versus
Load Current I Load
Turn-OFF delay time tOFF_delay to VOUT = 10% versus
Load Current I Load
50
50
Tj = −40 °C
Tj = −40 °C
45
45
Tj = 25 °C
Tj = 25 °C
Tj = 150 °C
Tj = 150 °C
40
40
35
30
25
20
15
10
35
30
25
20
15
10
5
5
VS = 24 V
VS = 24 V
0
0
0
0.2
0.4
0.6
0.8
0
0.2
0.4
0.6
0.8
ILoad [A]
ILoad [A]
Data Sheet
22
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6
Protection Functions
The device provides integrated protection functions. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Protection functions are designed to prevent the destruction of
the ITS4090Q-EP-D due to fault conditions described in the data sheet. Please note that fault conditions are
not considered as normal operation conditions and the protection functions are neither designed for
continuous operation nor for repetitive operation.
6.1
Loss of Ground Protection
In case of loss of module ground when the load remains connected to ground, the device protects itself by
automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied at the
input pins.
In an application where the inputs are directly controlled by logic levels < VS (e.g. by a microcontroller without
galvanic isolation), it is recommended to use input resistors 1) between the external control circuit
(microcontroller) and the ITS4090Q-EP-D to protect also the external control circuit in case of loss of device
ground.
In case of loss of module or device ground, a current (IOUT(GND)) can flow out of the DMOS. Figure 14 sketches
the situation.
ZGND is recommended to be a resistor in series to a diode.
ITS4090Q-EP-D
VS
+
-
ZDS(AZ)
ZD(AZ)
ST
RST
Logic
INx
RIN
IOUT(GND)
OUTx
GND
ZGND
Figure 14 Loss of Ground Protection with External Components
1) Recommended value is 10 kΩ
Data Sheet
23
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.2
Undervoltage Protection
If the supply voltage falls below VS(UV) the undervoltage protection of the device is triggered. VS(UV) represents
hence the minimum voltage for which the switch still can hold ON. Once the device is off VS(OP)_MIN represents
the lowest voltage where the device is turning on again (and thus the channels can be switched again). If the
supply voltage is below the undervoltage threshold VS(UV), the channels of the device are OFF (or turning OFF).
As soon as the supply voltage is recovering and exceeding the threshold of the functional supply voltage
VS(OP)_MIN, the device is re-powering and its channels can be switched again. In addition the protection
functions as well as diagnosis become operational once VSOP_MIN is reached. Figure 15 sketches the
undervoltage mechanism.
VOUT
VS
VS(UV)
VS(OP)_MIN
Figure 15 Undervoltage Behavior
6.2.1
Overvoltage Protection
There is an integrated clamping mechanism for overvoltage protection (ZD(AZ)). To ensure this mechanism
operates properly in the application, the current in the Zener diode ZD(AZ) must be limited by a ground resistor.
Figure 16 shows a typical application to withstand overvoltage issues. In case of supply voltage higher than
VS(AZ), the voltage across supply to ground path is clamped. As a result, the internal ground potential rises to
VS - VS(AZ). Due to the ESD Zener diodes, the potential at pin INx rises almost to that potential, depending on
the impedance of the connected circuitry 1). In the case the device was ON, prior to overvoltage, the ITS4090Q-
EP-D remains ON. In case the ITS4090Q-EP-D was OFF, prior to overvoltage, the power transistor can be
activated. In case the supply voltage is above VS(SC) and below VDS(AZ), the output transistor is still operational
and follows the input. If at least one channel is in ON-state, parameters are no longer within specified range
and lifetime is reduced compared to the nominal supply voltage range. This especially impacts the short
circuit robustness, as well as the maximum energy EAS capability. ZGND is recommended to be either a resistor
(27 Ω) in series to a diode or alternatively a 150 Ω power resistor.
1) Hence, the usage of external input resistors needs to be considered
Data Sheet
24
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
ISOV
VS
+
-
ZDS(AZ)
ZD(AZ)
ST
RST
Logic
INx
RIN
IOUT
OUTx
ITS4090Q-EP-D
GND
ZGND
Figure 16 Overvoltage Protection with External Components
Data Sheet
25
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.3
Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diodes of the affected power DMOS channels will dissipate power.
The current flowing through the intrinsic body diode is limited externally by the load itself. But in addition the
current into the ground path and the logic pins must be limited by an external resistor to the maximum
allowed current described in Chapter 4.1. Figure 17 shows a typical application. ZGND resistor is used to limit
the current through the Zener protection of the device. ZGND is recommended to be either a resistor (~ 27 Ω) in
series to a diode or alternatively a power resistor (~ 150 Ω).
During reverse polarity no protection functions are available.
VS
Microcontroller
ITS4090Q-EP-D
VDS(REV)
Protection
diodes
-
+
-VS(REV)
ZDS(AZ)
ZD(AZ)
ST
INx
RST
Logic
RIN
OUTx
GND
ZGND
Figure 17 Reverse Polarity Protection with External Components
Data Sheet
26
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.4
Overload Protection
In case of overload, such as high inrush current of a cold lamp filament, or short circuit to ground, the
ITS4090Q-EP-D offers a set of protection mechanisms which is illustrated in Figure 18.
6.4.1
Current Limitation
As a first step, the instantaneous power in the switch is contained within a safe range by limiting the current
to the maximum current allowed in the switch IL(LIM). During this time, where the current is limited to IL(LM), the
DMOS temperature is increasing caused by the voltage drop VDS over the DMOS.
Overtemperature concept:
Overtemperature behavior:
VIN
H
L
tON
Tj(SC)
t
tOFF
VOUT
ON
heating
up
0
t
Tj
OFF
cooling
down
Tj
Tj(SC)
∆Tj(SC)
Device
Status
∆Tj(SC)
Normal
Toggling
Overtemperature
t
t
VST
H
L
OFF
ON
OFF
ON
OFF
Waveforms turn on into a short circuit:
Waveforms short circuit during on state:
VIN
H
VIN
H
L
L
tON
tON
t
t
tOFF
tOFF
VOUT
VOUT
0
0
t
t
IL(LIM)
IL(LIM)
0
0
t
t
tST(FAULT)
tST(FAULT)_SC1
VST
H
VST
H
L
L
t
t
Normal
operation
OFF
OFF
OUT shorted to GND
Overloaded
OFF
OFF
Shut down by overtemperature and restart after
cooling down (thermal toggling) once the device
exceeds thermal threshold after being heated up
during current limitation state
Shut down by overtemperature and restart after
cooling down (thermal toggling) once the device
exceeds thermal threshold after being heated up
during current limitation state
Figure 18 Protection behavior of the ITS4090Q-EP-D
Data Sheet
27
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.4.2
Temperature Limitation in the Power DMOS
Each channel incorporates one temperature sensor. Activation of this temperature sensor will cause an
overheated channel to switch OFF to prevent destruction. Any protective overtemperature shutdown event
triggered within a channel is switching OFF the output of the corresponding channel until the temperature
reaches an acceptable value again.
A restart functionality is implemented that is switching the channel ON again after the DMOS temperature has
sufficiently cooled down.
6.5
Electrical Characteristics: Protection Functions
Table 5
Electrical Characteristics: Protection Functions 1)
VS = 8 V to 36 V, Tj = -40°C to 150°C (unless otherwise specified).
Typical values are given at VS = 24 V, Tj = 25°C
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Loss of Ground
2) 3)
Output leakage current
while GND disconnected
IOUT(GND)
–
0.1
650
70
–
mA
mV
V
VS = 24 V
P_6.5.1
P_6.5.2
P_6.5.3
Reverse Polarity
Drain source diode voltage VDS(REV)
during reverse polarity
–
700
75
IL = -2 A
Tj = 150°C
Overvoltage
4)
Overvoltage protection
Overload Condition
Load current limitation
VS(AZ)
65
ISOV = 5 mA
IL(LIM)
Tj(SC)
1.2
1.5
1.8
A
–
P_6.5.4
P_6.5.6
3)
Thermal shutdown
temperature
150
175
200
°C
–
3)
Thermal shutdown
hysteresis
ΔTj(SC)
–
30
–
K
–
P_6.5.7
1) Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Integrated
protection functions are designed to prevent IC from destruction under fault conditions described in the data sheet.
Fault conditions are considered as “outside” normal operating range. Protection functions are designed neither for
continuous nor repetitive operation.
2) All pins are disconnected except VS and OUT.
3) Not subject to production test; specified by design.
4) For practical cases it is recommended to place a resistor in the range of ≥ 27 Ω into the GND path to limit the GND
current associated with overvoltage events.
Data Sheet
28
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.6
Typical Performance Characteristics Protection Functions
Typical Performance Characteristics
Current Limit IL(LIM) versus
Junction Temperature Tj
Clamping Voltage VS(AZ) versus
Voltage Tj
2
1.8
1.6
1.4
1.2
1
75
74
73
72
71
70
69
68
67
66
65
0.8
0.6
0.4
0.2
VDS = 12V
0
−50
0
50
100
150
−50
0
50
100
150
Tj [°C]
Tj [°C]
Data Sheet
29
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
7
Diagnostic Functions
For diagnosis purpose, the ITS4090Q-EP-D provides a digital signal at pin ST. This signal is called STATUS. The
STATUS pin is realized as open drain output and must be connected to an external pull-up resistor. During
normal operation the STATUS signal is logic “High” (H). During short circuit to ground or overtemperature
condition the STATUS signal is logic “Low” (L). Table 6 shows the corresponding truth table.
Table 6
Device Operation INX all INi except INX
Diagnostic Truth Table 1) 2)
OUTX all OUTi except OUTX ST
Comment
3) External pull
up at ST pin
Normal Operation
L
H
H
L
L
OFF
ON
OFF
ON
X
H
H
H
H
L
H
don’t care
don’t care
don’t care
don’t care
ON
OFF
X
3) 4)
3)
Short Circuit to GND H
Overtemperature
ON
X
H
OFF 5)
X
L
1) Please refer to Table 7 for more details.
2) Not subject to production test; specified by design.
3) “X” denotes status of OUTi according to the status of the corresponding input signals INi.
4) Device not in specified RDS(ON)
5) Channel remains off during cooling-down phase of power stage; then channel tries to re-start.
.
7.1
Electrical Characteristics: Diagnostic Functions
Table 7
Electrical Characteristics: Diagnostic Functions
VS = 8 V to 36 V, Tj = -40°C to 150°C (unless otherwise specified).
Typical values are given at VS = 24 V, Tj = 25°C
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Diagnostic Timing in Overload Condition
1)
STATUS settling time for overload tST(FAULT)
detection
–
–
30
20
–
µs
VS = 24 V;
P_7.1.1
load jump of RL:
47Ω -> 12 Ω;
Please refer to
Figure 18 for
more details
STATUS settling time for channel tST(FAULT)_SC1
start-up into existing overload 2)
90
µs VDS ≥ 8 V;
Please refer to
P_7.1.9
Figure 18 for
more details
“Low” level STATUS voltage
“High” level STATUS voltage
VST(L)
VST(H)
IST
–
2
–
–
–
–
0.5
V
V
IST = 1.6 mA 3)
P_7.1.3
P_7.1.4
P_7.1.5
4)
3)
–
VS > VST
Current through STATUS pin
(Operating Range)
1.6
mA VST < 0.5 V
Data Sheet
30
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
Table 7
Electrical Characteristics: Diagnostic Functions (cont’d)
VS = 8 V to 36 V, Tj = -40°C to 150°C (unless otherwise specified).
Typical values are given at VS = 24 V, Tj = 25°C
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
Channel fault detection
interrogation time
(Sequential Pulse Width)
Tx
3
6
µs
µs
µs
µs
VST < 0.5 V 5)
P_7.1.2
5)
STATUS signal “High” valid
window after Tx on fault affected
channel
Tm
40
200
–
80
–
150
–
–
P_7.1.6
P_7.1.8
P_7.1.7
1)
Minimum delay between
subsequent Tx interrogation
windows.
TX-2-X
–
1)
Maximum delay time between Tx TD
(“High” to “Low”) on fault
affected channel and STATUS
“High” signal Tm
8
–
–
1) Not subject to production test; specified by design.
2) This parameter describes the status settling time when a channel is switched on into an already existing overload
condition. This parameter is referenced to the edge of the input pin IN that switches the channel into overload.
3) Levels referenced to device ground.
4) Depends on pull-up circuit that is used within application; maximum ratings of STATUS pin need to be respected.
5) Please refer to “Channel Fault Detection” on Page 31 for more details.
7.2
Channel Fault Detection
The ITS4090Q-EP-D is equipped with an intelligent channel fault detection system, which allows with the aid
of a microcontroller to identify and communicate the channel on which the fault occurs.
During normal operation the STATUS pin is kept “High” by the external pull-up resistor as shown in Table 6.
If - in case of a fault - the application requires the information on which of the channels the fault occurs when
a “Low” STATUS is flagged, then the microcontroller can be programmed according to the sequence depicted
as an example in Figure 19. The figure shows a case where three channels are active (these are channels 1, 2
and 4). Channel 3 in this example is not switched ON. During normal operation of channels 1, 2 and 4 the
STATUS signal is “High”. If a fault occurs, e.g. at channel 4, the STATUS signal goes “Low” to flag an error to the
microcontroller. The microcontroller, in order to identify on which channel the fault occurs, must send a
“Low” pulse sequentially to the input of each active channel, that is channels 1, 2 and 4 in this case. These
pulses are shown in Figure 19 and their width is denominated Tx. The pulse width Tx should be between 3 µs
up to 6 µs in order to make sure that the output does not react to this short inversion input level. The STATUS
signal will go to “High” for a short period of time Tmonly after the channel on which the fault occurs gets a
“Low” pulse from the microcontroller, which in this case is after channel 4 receives a “Low” pulse for a time Tx.
In this way, by reading back whether an inversion of the STATUS flag within Tm occurs, the microcontroller is
able to detect on which channel the fault occurs. Once the microcontroller receives this information it can
start to switch OFF the channel on which the fault occurs (channel 4 in this case) via the corresponding input
pin. For the delay time TD between Tx going “Low” and Tm going “High” a value of 8 µs needs to be taken into
account.
Data Sheet
31
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
Normal Operation
Fault at channel 4
Normal Operation
Tm
Tm
Tm
Fault
?
?
Channel
STATUS
IN1
TD
TD
TD
TX
TX
IN2
TX-2-X
TX-2-X
IN3
TX
IN4
t
An inverted ST-pin signal following a TX interrogation pulse within a time window Tm on a given channel confirms a fault channel.
A non-inverted ST-pin signal after a TX pulse (dashed lines) indicate that corresponding channel is not in fault condition.
Figure 19 Channel Fault Detection Timing Diagram
Data Sheet
32
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
7.3
Typical Performance Characteristics Diagnostic Functions
Typical Performance Characteristics
Status Settling Time tST(FAULT) versus
Status Settling Time tST(Fault)_SC1 versus
Junction Temperature Tj (overload during ON)
Junction Temperature Tj (switch on into overload)
80
80
tST(Fault)_SC1
typ. tST(Fault) for RL: 47 Ω −> 12 Ω
typ. tST(Fault) for RL: 47 Ω −> 0 Ω
70
60
50
40
30
20
10
0
70
60
50
40
30
20
VS = 24V
10
VS = 24V
VDS = 8V
0
−50
0
50
100
150
−50
0
50
100
150
Tj [°C]
Tj [°C]
Maximum Delay Time TD (TX ‘H->L’ to ST ‘L->H’) vs. ST “High” Valid window (after TX) TM versus
Junction Temperature Tj
Junction Temperature Tj
10
100
TM
90
TD
9
VS = 24V
8
7
6
5
4
3
2
1
0
80
70
60
50
40
30
20
10
VS = 24V
0
−50
0
50
100
150
−50
0
50
100
150
Tj [°C]
Tj [°C]
Data Sheet
33
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Input Pins
8
Input Pins
8.1
Input Circuitry
The input circuitry is compatible with 3.3 V and 5 V microcontrollers as well as input levels up to VS 1). The
concept of the input pin is to react to voltage thresholds which are referenced to device ground. An
implemented Schmitt trigger avoids any undefined state if the voltage on the input pin is slowly increasing or
decreasing. The output is either OFF or ON but cannot be in a linear or undefined state. Figure 20 shows the
electrical equivalent input circuitry. In case a channel is permanently not needed, the corresponding input pin
shall not be left floating but tied with a serial resistor to device ground (not module ground). The
recommended value for the serial resistor is 2.2 kΩ.
VS
ITS4090Q-EP-D
Bias
Gate
Driver
INx
VIH
Inv.
Comp
Device
Logic
OUTx
GND
ZGND
Figure 20 Input Pin Circuitry
8.2
Input Pin Voltage
The input pin IN uses a comparator with hysteresis. Switching “ON / OFF” of the channels takes place in a
defined region, set by the thresholds VIN(L),max and VIN(H),min. The exact values where the “ON” and “OFF” take
1) VIN must not exceed VS. The relation VIN ≤ VS must always be fulfilled.
Data Sheet
34
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Input Pins
place depend on the process, as well as on the temperature. To avoid cross talk and parasitic turn-ON or turn-
OFF, a hysteresis is implemented. This ensures an improved immunity to noise.
8.3
Electrical Characteristics: Input Pins
Table 8
Electrical Characteristics: Input Pins
VS = 8 V to 36 V, Tj = -40°C to 150°C (unless otherwise specified).
Typical values are given at VS = 24 V, Tj = 25°C
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Input Pins Characteristics
1)
“Low” level input voltage
range
VIN(L)
VIN(H)
-0.3
2
–
–
0.8
36
V
V
–
P_8.3.1
P_8.3.2
1)
“High” level input voltage
range
VS > VIN
2)
Input voltage hysteresis
“Low” level input current
“High” level input current
VIN(HYS)
IIN(L)
–
–
–
250
38
–
mV
µA
µA
–
P_8.3.3
P_8.3.4
P_8.3.5
70
70
VIN = 0.8 V
VIN = 24 V
IIN(H)
46
1) Levels referenced to device ground.
2) Not subject to production test; specified by design.
Data Sheet
35
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Input Pins
8.4
Typical Performance Characteristics Input Pins
Typical Performance Characteristics
Input Voltage thresholds VIN(L) VIN(H) versus
Junction Temperature Tj
Input Voltage hysteresis VIN(HYS) versus
Junction Temperature Tj
2
1.8
1.6
1.4
1.2
1
0.8
VIN(HYS)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.8
0.6
0.4
VIN(H)
VIN(L)
0.2
0
VS = 24V
VS = 24V
0
0
50
100
150
0
50
100
150
Tj [°C]
Tj [°C]
Input Pin Current IIN(H) versus
Supply Voltage V S
Input Pin Current IIN(H) versus
Junction Temperature Tj
70
70
VIN = 24V
Tj −40°C
Tj 25°C
60
60
50
40
30
20
10
0
Tj 150°C
50
40
30
20
10
VS = 28.8V
0
0
5
10
15
20
25
0
50
100
150
VIN [V]
Tj [°C]
Data Sheet
36
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Application Information
9
Application Information
9.1
Application Diagram
Note:
This is a very simplified example of an application circuit. The function must be verified in the real
application.
Linear
VOUT
External
VIN
Voltage Regulator
e.g. IFX1763
components for
Surge Immunity
COUT
VS
VDD
VS
Microcontroller
e.g. XMC4xxx
I/O
OUT1
OUT2
IN1
IN2
I/O
VDD
30 kΩ
ST
I/O
I/O
ITS4090Q-EP-D
OUT3
OUT4
IN3
IN4
I/O
TM
GND
2.2 kΩ
GND
ZGND
External components for reverse polarity protection and overvoltage
pulses. Recommended setup for ZGND is a diode for reverse polarity in
series with a resistor of ~27Ω to limit GND current during overvoltage
spikes.
Figure 21 Application Diagram with ITS4090Q-EP-D
In Figure 21 above a simplified application diagram is shown where the inputs are galvanically isolated from
VS with optocouplers. Thanks to the fact that the input pins are 24 V capable they can be directly connected to
the optocouplers. Reverse polarity protection can be achieved with external components. In this context it
should be noted that input pins of channels which are permanently unused have to be tied with 2.2 kΩ
resistance to device ground. In addition the TM-pin must be always be tied with a serial resistor to device
ground in order to protect the pin in case of reverse polarity. The recommended value for this serial resistor is
also 2.2 kΩ. For applications where no galvanic isolation is present between the external control circuitry (e.g
microcontroller) and the input pins of the ITS4090Q-EP-D serial input resistors need to be placed in order to
Data Sheet
37
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Application Information
protect the external control circuitry and the input structures of the ITS4090Q-EP-D under fault conditions
(like e.g. reverse polarity, loss of ground or overvoltage). For further details please also refer to the
corresponding sections in Chapter 6. The recommended value for such serial input resistors is 10 kΩ however
application specific optimized values may also depend on the individual application conditions as well as the
applied external control circuitry / microcontroller.
9.2
Thermal Considerations
If the cooling possibilities within the application are not sufficient to sink the heat of the dissipated power the
junction temperature Tj of the device may exceed its maximum specified rating of 150°C and eventually trigger
a thermal shutdown of the overheated channels to protect the device from destruction. Such thermal
shutdown events may occur e.g. if one or more channels are operated in overload conditions that are causing
the current limitation functionality to become active. If the current limitation of a channel becomes active the
power dissipation will rise rapidly and in many cases lead to thermal shutdown events of the corresponding
channels within short periods of time.
But also under nominal load conditions the power dissipation can become too high inside an application if it
is applied at high environmental temperature TAMB and if at the same time the cooling capability of the PCB is
not sufficient (thanks to the very good RDSON performance of the ITS4090Q-EP-D this restriction is limited to
cases with poor thermal connection to the PCB being applied at very high ambient temperatures TAMB as will
be shown below). In general the cooling capability of an IC on a PCB within an application can be described for
static cases by its thermal resistance from junction-to-ambient RthJA. The thermal resistance RthJA can be
improved by adding cooling area on top- or bottom layer of the PCB or by adding inner layers that are
connected to the VS layer with thermal vias. Thermal vias show the best efficiency for heat distribution if
directly placed underneath the exposed pad of the ITS4090Q-EP-D. The achievable values for RthJA will differ
from application to application. As reference simulation values of RthJA for a set of standardized JEDEC cases
are provided in Chapter 4.4 “Thermal Resistance” on Page 12. Actual values in real applications naturally
can be lower or higher.
For cases where the achievable thermal resistance RthJA and the hereof resulting thermal budget within an
application is not sufficient for a given ambient temperature TAMB there is no other choice than to lower the
load current to smaller numbers than the allowed maximum nominal current of 750 mA. Figure 22 illustrates
how the derating of the nominal current due to excessive power dissipation can look like as a function of
achievable RthJA and given TAMB. The graphs show how the thermal budget with its limiting condition Tj = 150°C
can be shared between the influencing parameters TAMB, RthJA, ILoad depending on the number of active
channels nCH. Due to the excellent ratio of RDSON versus nominal load current this impact shown in the
mentioned figures below are relevant only for worst case scenarios like RthJA of “footprint only” where no
additional cooling is present at all but solely footprint and PCB traces to the pins of the device. Even under
such harsh conditions the only noteworthy limitations occur for TAMB > 75°C if all four channels are operated
at full load. An arbitrary RthJA value of 100 K/W is depicted in addition and may serve as an RthJA - reference
value for which derating may become relevant when being exposed to high ambient temperatures of
TAMB = 85°C and above.
The calculation of the thermal budget displayed in the graphs follows simple rules as given in the equations
below. It should be noted that the calculation is restricted to static cases where the resulting TAMB and Tj have
reached a stable equilibrium.
(9.1)
Tj = TAMB + RthJA × PDISS
(9.2)
PDISS = I2Load × RDS(ON) × nCH + VS × IGND
Data Sheet
38
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Application Information
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
3 channels active
4 channels active
R
= 100 K/W
= 119 K/W
R
= 100 K/W
= 119 K/W
thJA
thJA
(V = 28V)
(V = 28V)
S
S
R
R
thJA
thJA
20
30
40
50
60
[°C]
70
80
90
100
20
30
40
50
60
T [°C]
AMB
70
80
90
100
T
AMB
Figure 22 Possible thermal derating of nominal current due to insufficient cooling capability of PCB
Data Sheet
39
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Package Outlines
10
Package Outlines
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Figure 23 PG-TSDSO-14 (Plastic Dual Small Outline Package) (RoHS-Compliant)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Data Sheet
40
Rev. 1.0
2018-06-14
ITS4090Q-EP-D
90 mΩ Quad Channel Smart High-Side Power Switch
Revision History
11
Revision History
Revision Date
Changes
1.0
2018-06-14 Data Sheet (Initial Release)
Data Sheet
41
Rev. 1.0
2018-06-14
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