JMK212BJ476MG-T [INFINEON]
HIGHLY INTEGRATED 14A SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR; 高度集成的14A单输入电压同步降压稳压器
| 型号： | JMK212BJ476MG-T |
| 厂家： | 
Infineon |
| 描述： | HIGHLY INTEGRATED 14A SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR |
| 文件： | 总36页 (文件大小：1356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD97511
IR3837MPbF
TM
SupIRBuck
HIGHLY INTEGRATED 14A
SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Description
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Greater than 96% Maximum Efficiency
The IR3837 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard PWM controller and MOSFETs
make IR3837 a space-efficient solution, providing
accurate power delivery for low output voltage
applications.
Single 16V Application
Single 5V Application
Wide Output Voltage Range: 0.6V to 0.9*Vin
Continuous 14A Load Capability
Programmable Switching Frequency up to 1.5MHz
Internal Digital Soft-Start
IR3837 is a versatile regulator which offers
programmability of switching frequency and
current limit while operates in wide input and
output voltage range.
Enable Input with Voltage Monitoring Capability
Hiccup Mode Over Current Protection
Internal LDO
External Synchronization
Enhanced PreBias Start up
The switching frequency is programmable from
250kHz to 1.5MHz for an optimum solution.
External Reference for Margining Purposes
Input for Tracking Applications
It also features important protection functions,
such as Pre-Bias startup, hiccup current limit and
thermal shutdown to give required system level
security in the event of fault conditions.
Integrated MOSFET Drivers and Bootstrap Diode
Operating Junction Temp: -40oC <Tj<125oC
Thermal Shut Down
Power Good Output with Tracking Capability
Over Voltage Detection Feature
IR3837 offers margining capability through Vref
pin. During the margining operation, PGood
tracks Vref via feedback to ensure correct status
of the output voltage.
Pin Compatible with 6A and 10A Versions
Small Size 5mmx6mm PQFN, 0.9 mm Height
Lead-free, Halogen-free and RoHS Compliant
The internal LDO enables the device to operate
from a single supply. This internal LDO can be
bypassed when an external bias voltage is
available.
Applications
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Netcom and Telecom Applications
Data Center Applications
Distributed Point of Load Power Architectures
Fig. 1. Typical application diagram
1
Rev 1.31
IR3837MPbF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
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PVin, Vin ……………………………………………… -0.3V to 25V
Vcc/LDO_out ……………….……..……..……….…… -0.3V to 8V (Note2)
Boot
SW
……………………………………..……….….. -0.3V to 33V
…………………………………………..……… -0.3V to 25V (DC), -4V to 25V (AC, 100ns)
Boot to SW ……..…………………………… …..…. -0.3V to Vcc+0.3V (Note1)
OCset …………………………………………..…… -0.3V to 30V
Input / output Pins ………………………………... ... -0.3V to Vcc+0.3V (Note1)
PGnd to Gnd ……………...………………….…….…. -0.3V to +0.3V
Storage Temperature Range .................................... -55°C To 150°C
Junction Temperature Range ................................... -40°C To 150°C (Note2)
ESD Classification …………………………… ……… JEDEC(2KV)
Moisture sensitivity level………………...……………. JEDEC Level 2 @260 °C (Note 5)
Note1: Must not exceed 8V
Note2: Vcc must not exceed 7.5V for Junction Temperature between -10oC and -40oC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of the specifications are not implied.
Package Information
5mm x 6mm Power QFN
(Top View)
11
PGnd
12
SW
13
PVin
θJA = 35oC / W
θJ-PCB = 2oC / W
Boot
Enable
Vp
14
Vcc/LDO_out
10
17
Gnd
Vin
9
8
15
16
Sync
1
4
7
2
3
5
6
Fb Vref Comp Gnd Rt OCset PGood
ORDERING INFORMATION
PACKAGE
DESIGNATOR
PACKAGE
PIN
COUNT
PARTS PER
REEL
DESCRIPTION
M
M
IR3837MTRPbF
IR3837MTR1PbF
17
17
4000
750
2
Rev 1.31
IR3837MPbF
Block Diagram
Fig. 2. Simplified block diagram of the IR3837
3
Rev 1.31
IR3837MPbF
Pin Description
Pin Name
Description
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator via resistor divider to set the output voltage and
provide feedback to the error amplifier
1
2
Fb
External reference voltage, can be used for margining operation. A
100nF capacitor should be connected between this pin and Gnd.
Vref
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to Fb to provide loop compensation
3
4
5
Comp
Gnd
Rt
Signal ground for internal reference and control circuitry
Use an external resistor from this pin to Gnd to set the switching
frequency
Current limit set point. A resistor from this pin to SW pin will set the
current limit threshold
6
7
OCset
PGood
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to Vcc
External Synchronization, this pin is used to synchronize the device’s
switching with an external clock. It is recommended that the external
Sync clock be set to 20% above the free-running frequency. If not used,
this pin can be left floating.
Sync
Vin
8
9
Input voltage for Internal LDO. A 1.0µF capacitor should be connected
between this pin and PGnd. If external supply is connected to
Vcc/LDO_out pin, this pin should be left floating.
VCC
Input Bias Voltage, output of internal LDO. Place a minimum 2.2µF cap
from this pin to PGnd
10
11
/LDO_out
Power Ground. This pin serves as a separated ground for the MOSFET
drivers and should be connected to the system’s power ground plane.
PGnd
12
13
SW
Switch node. This pin is connected to the output inductor
Input voltage for power stage
PVin
Supply voltage for high side driver, a 100nF capacitor should be
connected between this pin and SW pin.
14
15
Boot
Enable pin to turn on and off the device, if this pin is connected to PVin
pin through a resistor divider, input voltage UVLO can be implemented.
Enable
16
17
Vp
Input to error amplifier for tracking purposes
Gnd
Signal ground for internal reference and control circuitry
4
Rev 1.31
IR3837MPbF
Recommended Operating Conditions
Symbol
Definition
Min
Max
Units
PVin
Vin
Input Voltage for power stage
Input Voltage for internal LDO *
1.5
7.0
4.5
4.5
0.6
0
16
16
6.5
7.5
0.9*Vin
14
V
Vcc/LDO_out Supply Voltage *
Boot to SW
Vo
Io
Supply Voltage
Output Voltage
Output Current
A
Fs
Tj
Switching Frequency
Junction Temperature
225
-40
1650
125
kHz
oC
* Vcc/LDO_out can be connected to an external regulated supply (≈ 5V). If so, the Vin input should be
left unconnected.
Electrical Specifications
Unless otherwise specified, these specification apply over, 7.0V<Vin=PVin<16V, Vref=0.6V
in 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC.
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
POWER STAGE
Power Losses
Ploss
Vin=12V, Vo=1.8V, Io=14A,
Fs=600kHz, L=0.51uH, Note4
VBoot -Vsw =5.0V,
3
W
Top Switch
Rds(on)_Top
12
16
ID=14A,Tj=25C
mΩ
Bottom Switch
Rds(on)_Bot
Vcc=5.0V, ID=14A
I(Boot)= 30mA
5.3
7
Bootstrap Diode Forward
Voltage
180
260
470
mV
SW leakage Current
Isw
SW=0V, Enable=0V
6
µA
SW=0V, Enable=high, Vp=0V
14
SUPPLY CURRENT
Vin Supply Current (Standby)
Iin(Standby)
Iin(Dyn)
Enable low , No Switching,
400
µA
Vin Supply Current (Dyn)
Enable high, Fs=500kHz,
Vin=12V
17
mA
INTERNAL REGULATOR (LDO)
Output Voltage
IntVcc
Vin(min)=7.0V, Io=0-50mA,
Cload=2.2uF
4.7
5.2
5.7
V
IntVcc Dropout
IntVcc_drop Io=50mA, Cload=2.2uF
50
70
150
mV
mA
Short Circuit Current
Ishort
INTERNAL DIGITAL SOFT START
Soft Start Clock Frequency
Clk(SS)
Note4
168
200
0.2
254
kHz
Soft Start Ramp Rate
Ramp(SS)
mV/us
5
Rev 1.31
IR3837MPbF
Electrical Specifications (continued)
Unless otherwise specified, these specification apply over, 7.0V<Vin=PVin<16V, Vref=0.6V
in 0oC<Tj< 125oC. Typical values are specified at Ta = 25oC.
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Vos_Vp
Vfb-Vp, Vp=0.6V, Vref >2.0V
Vfb-Vref, Vref=0.6V, Vp>2.0V
-1
-1
+1
1
Input Offset Voltage
%
Vos_Vref
Input Bias Current
Input Bias Current
Sink Current
IFb(E/A)
IVp(E/A)
Isink(E/A)
Isource(E/A)
SR
-1
-1
+1
+1
A
A
0.40
8
0.85
10
1.2
13
mA
mA
V/s
MHz
dB
Source Current
Slew Rate
Note4
Note4
Note4
7
12
20
Gain-Bandwidth Product
DC Gain
GBWP
20
100
3.4
30
40
Gain
110
3.5
150
120
3.75
220
1.2
Maximum Voltage
Minimum Voltage
Common Mode Voltage
Vmax(E/A)
Vmin(E/A)
V
mV
V
0
OSCILLATOR
Rt Voltage
0.665
225
0.7
250
500
1500
1.8
0.735
275
V
Rt=59K
Frequency Range
Rt=28.7K
Rt=9.53K, Note4
Note4
450
550
FS
kHz
1350
1650
Ramp Amplitude
Ramp Offset
Vramp
Ramp(os)
Dmin(ctrl)
Dmax
Vp-p
V
Note4
0.6
Min Pulse Width
Max Duty Cycle
Fixed Off Time
Sync Frequency Range
Note4
70
ns
Fs=250kHz
Note4
91
%
300
ns
20% above free running
frequency
225
1650
kHz
Sync Pulse Duration
Sync Level Threshold
100
2
200
0.6
ns
V
Sync High
Sync Low
0.6
REFERENCE VOLTAGE
Feedback Voltage
VFB
Vref pin floating, Vp=Vcc
0oC<Tj<125oC
-40oC<Tj<125oC, Note3
V
Accuracy
-1.0
-2.0
0.54
+1.0
+2.0
1.2
25
%
Vref margining voltage
Sink Current
Vref_marg
Isink_Vref
V
Vref=0.7V
19
19
µA
µA
Source Current
Isource_Vref
Vref=0.5V
25
Tracker Comparator Threshold Tracker(upper)
Tracker(lower)
Vref pulled up externally
Vref pulled up externally
Vref pulled up externally
1.35
1.05
220
1.5
1.2
300
1.6
1.3
420
V
Tracker Comparator
Hysteresis
Tracker_Hys
mV
6
Rev 1.31
IR3837MPbF
Electrical Specifications (continued)
PARAMETER
SYMBOL
TEST CONDITION
Fs=250kHz
MIN
TYP
MAX
UNIT
FAULT PROTECTION
10.4
21.5
68
11.8
24.4
77
13.2
27.3
86
OCSET Current
IOCSET
µA
Fs=500kHz
Fs=1500kHz
Note4
OC comp Offset Voltage
SS off time
VOFFSET
-6
0
+6
mV
SS_Hiccup
4096
140
20
Cycles
Thermal Shutdown
Thermal Hysteresis
Note4
Note4
°C
V
UNDER VOLTAGE LOCKOUT
VCC-Start-Threshold
VCC_UVLO_Start
VCC_UVLO_Stop
Enable_UVLO_Start
Enable_UVLO_Stop
Ien
Vcc Rising Trip Level
Vcc Falling Trip Level
Supply ramping up
Supply ramping down
Enable=3.3V
4.06
3.76
1.14
0.75
4.26
3.96
1.2
4.46
4.16
1.36
0.95
VCC-Stop-Threshold
Enable-Start-Threshold
Enable-Stop-Threshold
Enable leakage current
0.85
V
µA
10
PGOOD
Power Good upper Threshold
VPG(upper)
Fb Rising, Vref < 1.2V
Fb Rising, Vref > 1.5V
Fb Falling
115
115
%Vref
%Vp
s
Upper Threshold Delay
VPG(upper)_Dly
VPG(lower)
256/Fs
85
Power Good lower Threshold
Fb Rising, Vref < 1.2V
Fb Rising, Vref > 1.5V
Fb Rising
%Vref
%Vp
s
85
Lower Threshold Delay
Soft Start Delay Time
PGood Voltage Low
VPG(lower)_Dly
Tdelay(Delay)
PG(voltage)
256/Fs
10
Note4
ms
IPgood=-5mA
0.5
V
Tracker Comparator Upper
Threshold
Tracker Comparator Lower
Threshold
VPG(tracker_upper) Vp Rising, Vref > 1.5V
VPG(tracker_lower) Vp Falling, Vref > 1.5V
0.5
0.3
V
s
Tracker Comparator Delay
Tdelay(tracker)
Vp Rising, Vref > 1.5V
256/Fs
Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note4: Guaranteed by design but not tested in production
Note5: Upgrade to industrial/MSL2 level applies from date codes 1141 (marking explained on application note AN1132 page 2).
Products with prior date code of 1141 are qualified with MSL3 for Consumer market.
7
Rev 1.31
IR3837MPbF
Typical Efficiency and Power Loss Curves
Vin=12V, Vcc=5V (external), Io=1A-14A, Fs=600kHz, Room Temperature, No Air Flow
The table below shows the inductors used for each of the output voltages
in the efficiency measurement.
Vo [V]
1.0
L [µH]
0.4
MFR
Vitec
P/N
DCR [mΩ]
0.29
59PR9875N
59PR9876N
59PR9876N
59PR9876N
1.2
1.5
1.8
2.5
3.3
5.0
0.51
0.51
0.51
0.68
1.0
Vitec
Vitec
Vitec
0.29
0.29
0.29
0.72
1.17
1.17
Wurth Elek. 744 332 0068
Wurth Elek. 744 332 0100
Wurth Elek. 744 332 0100
1.0
97
95
93
91
89
87
85
83
81
79
77
75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Load Current (A)
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
4.7
4.2
3.7
3.2
2.7
2.2
1.7
1.2
0.7
0.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Load Current (A)
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
8
Rev 1.31
IR3837MPbF
Typical Efficiency and Power Loss Curves
Vin=12V, Vcc/LDO_out=5.2V, Io=1A-14A, Fs=600kHz, Room Temperature, No Air Flow
The same inductors as listed on the previous page have been used.
97
95
93
91
89
87
85
83
81
79
77
75
73
71
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Load Current (A)
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
4.7
4.2
3.7
3.2
2.7
2.2
1.7
1.2
0.7
0.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Load Current (A)
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
9
Rev 1.31
IR3837MPbF
TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC), Fs=500 kHz
Iin(Dyn)
Iin(Standby)
400
17.0
380
360
16.8
340
320
16.6
300
280
16.4
260
240
16.2
220
200
180
160
16.0
15.8
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temp [ºC]
Temp [ºC]
FREQUENCY
IOCSET(500kHz)
27.5
550
540
530
520
510
500
490
480
470
460
450
26.5
25.5
24.5
23.5
22.5
21.5
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temp [ºC]
Temp [ºC]
Vcc(UVLO) Start
Vcc(UVLO) Stop
4.46
4.41
4.36
4.31
4.26
4.21
4.16
4.11
4.06
4.16
4.11
4.06
4.01
3.96
3.91
3.86
3.81
3.76
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temp [ºC]
Temp [ºC]
Enable(UVLO) Stop
Enable(UVLO) Start
1.36
0.95
0.93
0.91
0.89
0.87
0.85
0.83
0.81
0.79
0.77
0.75
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temp [ºC]
Temp [ºC]
Vcc_LDO
Vfb
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
0.612
0.608
0.604
0.600
0.596
0.592
0.588
-40
-20
0
20
40
60
80
100
120
140
-40
-20
0
20
40
60
80
100
120
140
Temp [ºC]
Temp [ºC]
10
Rev 1.31
IR3837MPbF
Rdson of MOSFETs Over Temperature at Vcc=5V
18
16
14
12
10
8
6
4
-40
-20
0
20
40
60
80
100
120
140
Temperature [ºC]
Sync-FET
Ctrl-FET
Rdson of Sync-FET versus Vcc at different Temperatures
9
8
7
6
5
4
3
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
Vcc [V]
-40C
0C
25C
65C
100C
125C
11
Rev 1.31
IR3837MPbF
Thermal De-rating Curves
Test Conditions: Vin=12V, Vout=1.8V, Vcc/LDO_out=5.2V, Fs=600kHz, 0- 400LFM
L=0.51uH (59P9876N)
15
14
13
12
11
10
9
8
7
25
30
35
40
45
50
55
60
65
70
75
80
85
Ambient Temperature [°C]
0 LFM
100LFM
200LFM
300LFM
400LFM
12
Rev 1.31
IR3837MPbF
Enable
Circuit Description
The Enable features another level of flexibility for
start up. The Enable has precise threshold which
is internally monitored by Under-Voltage Lockout
(UVLO) circuit. Therefore, the IR3837 will turn on
only when the voltage at the Enable pin exceeds
this threshold, typically, 1.2V.
THEORY OF OPERATION
Introduction
The IR3837 uses a PWM voltage mode control
scheme with external compensation to provide
good noise immunity and maximum flexibility in
selecting inductor values and capacitor types.
If the input to the Enable pin is derived from the
bus voltage by a suitably programmed resistive
divider, it can be ensured that the IR3837 does
not turn on until the bus voltage reaches the
desired level (Fig. 3). Only after the bus voltage
reaches or exceeds this level will the voltage at
Enable pin exceed its threshold, thus enabling
the IR3837. Therefore, in addition to being a logic
input pin to enable the IR3837, the Enable
feature, with its precise threshold, also allows the
user to implement an Under-Voltage Lockout for
The switching frequency is programmable from
250kHz to 1.5MHz and provides the capability of
optimizing the design in terms of size and
performance.
IR3837 provides precisely regulated output
voltage programmed via two external resistors
from 0.6V to 0.9*Vin.
The IR3837 operates with an internal bias supply
voltage of 5.2V (LDO) which is connected to the
Vcc/LDO_out pin. This allows operation with
single supply. The IC can also be operated with
an external supply from 4.5V to 6.5V, allowing an
extended operating input voltage (PVin) range
from 1.5V to 16V. For using the internal supply,
the Vin pin should be connected to PVin pin. If an
external supply is used, it should be connected to
Vcc/LDO_out pin and the Vin pin should be left
floating.
the bus voltage (PVin).
This is desirable
particularly for high output voltage applications,
where we might want the IR3837 to be disabled
at least until PVin exceeds the desired output
voltage level.
Pvin (12V)
10. 2V
Vcc (5.2V)
The device utilizes the on-resistance of the low
side MOSFET (sync FET) as current sense
element. This method enhances the converter’s
efficiency and reduces cost by eliminating the
Enable
Enable Threshold=1.2V
SS
need for external current sense resistor.
IR3837 includes two low Rds(on) MOSFETs using
IR’s HEXFET technology. These are specifically
designed for high efficiency applications.
Fig. 3. Normal Start up, device turns on
when the bus voltage reaches 10.2V
Figure 4a. shows the recommended start-up
sequence for the normal (non-tracking, non-
sequencing) operation of IR3837, when Enable is
used as a logic input. In this operating mode Vref
is left floating. Figure 4b. shows the
recommended startup sequence for sequenced
operation of IR3837 with Enable used as logic
input. For this mode of operation, Vref is left
floating. Figure 4c shows the recommended
startup sequence for tracking operation of
IR3837 with Enable used as logic input. For this
mode of operation, Vref is connected to a voltage
greater than 1.5V.
Under-Voltage Lockout and POR
The under-voltage lockout circuit monitors the
voltage of Vcc/Ldo pin and the Enable input. It
assures that the MOSFET driver outputs remain
in the off state whenever either of these two
signals drop below the set thresholds. Normal
operation resumes once Vcc/LDO and Enable
rise above their thresholds.
The POR (Power On Ready) signal is generated
when all these signals reach the valid logic level
(see system block diagram). When the POR is
asserted the soft start sequence starts (see soft
start section).
13
Rev 1.31
IR3837MPbF
Vref
This pin reflects the internal reference voltage
which is used by the error amplifier to set the
output voltage. In most operating conditions this
pin is only connected to an external bypass
capacitor and it is left floating. In tracking mode
this pin should be connected to an external
voltage greater than 1.5V and less than 7V. For
margining applications, an external voltage
source is connected to Vref pin and overrides
the internal reference voltage. The external
voltage source should have a low internal
resistance (<100Ω) and be able to source and
sink more than 25µA.
Pre-Bias Startup
Fig. 4a. Recommended startup for
Normal operation
IR3837 is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.
Pvin (12V)
The output starts in asynchronous fashion and
keeps the synchronous MOSFET (sync FET)
off until the first gate signal for control MOSFET
(control FET) is generated. Figure 5a shows a
typical Pre-Bias condition at start up. The sync
FET always starts with a narrow pulse width
and gradually increases its duty cycle with a
step of 25%, 50%, 75% and 100% until it
reaches the steady state value. The number of
these startup pulses for the sync FET is
internally programmed. Figure 5b shows a
series of 32, 16, 8 startup pulses.
Vcc (5.2V)
Enable>1. 2V
SS
Vp
Fig. 4b. Recommended startup for sequencing
operation (ratiometric or simultaneous)
Pvin (12V)
Fig. 5a. Pre-Bias startup
Vcc (5.2V)
Vcc > Vref > 1.5V
Enable >1. 2V
SS
Vp
Fig. 4c. Recommended startup for memory
tracking operation (Vtt-DDR)
Fig. 5b. Pre-Bias startup pulses
14
Rev 1.31
IR3837MPbF
Table 1. Switching Frequency and IOCSet vs.
Soft-Start
External Resistor (Rt)
The IR3837 has a digital internal soft-start to
control the output voltage rise and to limit the
current surge at the start-up. To ensure correct
start-up, the soft-start sequence initiates when
the Enable and Vcc rise above their UVLO
thresholds and generate the Power On Ready
(POR) signal. The internal SS signal linearly
rises with the rate of 0.2mV / µs from 0V to 2V.
Figure 6 shows the waveforms during soft start
(also refer to figure 11). The normal start up time
is fixed, and is equal to:
Rt (kΩ)
47.5
35.7
28.7
23.7
20.5
17.8
15.8
14.3
12.7
11.5
10.7
9.76
9.31
Fs (kHz)
300
Iocset (μA)
14.7
19.6
400
500
24.35
29.54
34.1
600
700
800
39.3
900
44.3
1000
1100
1200
1300
1400
1500
48.95
55.1
1.3V - 0.7V
3ms
Tstart
- - - - - - - - - - - - - - (1)
0.2mV/s
60.85
65.4
During the soft start the OCP is enabled to
protect the device for any short circuit and over
current condition.
71.7
75.15
Over-Current Protection
The over current protection is performed by
sensing current through the RDS(on) of the sync
FET. This method enhances the converter’s
efficiency and reduces cost by eliminating a
current sense resistor. As shown in figure 7, an
external resistor (ROCSet) is connected between
OCSet pin and the switch node (SW) which sets
the current limit set point.
An internal current source sources current
(IOCSet ) out of the OCSet pin. This current is a
function of Rt and hence, of the free-running
switching frequency.
700
I
OCSet (μA)
...................................(2)
Rt (k)
Fig. 6. Theoretical operation waveforms
during soft-start (non tracking / non sequencing)
Table 1. shows IOCSet at different switching
frequencies. The internal current source
develops a voltage across ROCSet. When the sync
FET is turned on, the inductor current flows
through Q2 and results in a voltage at OCSet
which is given by:
Operating Frequency
The switching frequency can be programmed
between 250kHz – 1500kHz by connecting an
external resistor from Rt pin to Gnd. Table 1
tabulates the oscillator frequency versus Rt.
VOCSet (IOCSet ROCSet ) (RDS(on) IL )..........(3)
An over current is detected if the OCSet pin goes
below ground. However, to avoid false tripping ,
due to the noise generated when the sync FET is
turned on, the OCP comparator is enabled about
200ns after sync-FET is turned on.
Shutdown
The IR3837 can be shutdown by pulling the
Enable pin below its 0.85 V threshold. This will
tri-state both, the high side driver as well as the
low side driver.
15
Rev 1.31
IR3837MPbF
External Synchronization
The IR3837 incorporates an internal circuit which
enables synchronization of the internal oscillator
(using rising edge) to an external clock. An
external resistor from Rt pin to Gnd is still
required to set the free-running frequency close
to the Sync input frequency. This function is
important to avoid sub-harmonic oscillations due
to beat frequency for embedded systems when
multiple POL (point of load) regulators are used.
Applying the external signal to the Sync input
changes the effective value of the ramp signal
(Vramp/Vosc).
Vosc 1.8 fFree_ Run fSync ......................(5)
1
Equation (5) shows that the effective amplitude of
the ramp is reduced after the external Sync
signal is applied. More difference between the
frequency of the Sync and the free-running
frequency results in more change in the effective
amplitude of the ramp signal. Therefore, since
the ramp amplitude takes part in calculating the
loop-gain and bandwidth of the regulator, it is
recommended to not use a Sync frequency which
is much higher than the free-running frequency
(or vice versa). In addition, the effective value of
the ramp signal, given by equation (5), should be
used when the compensator is designed for the
regulator.
Fig. 7. Connection of over current sensing resistor
As mentioned earlier, an over current is detected
if the OCSet pin goes below ground. Hence, at
the current limit threshold, VOCset=0. Then, for a
current limit setting ILimit, ROCSet is calculated as
follows:
R
DS(on) * I
ROCSet
Limit ........................(4)
IOCSet
An over-current detection trips the OCP
comparator, latches OCP signal and cycles the
soft start function in hiccup mode.
The pulse width of the external clock, which is
applied to the sync, should be greater than 100ns
and its high level should be greater than 2V,
while its lower level is less than 0.6V. For more
information refer to the Oscillator section in page-
6. If this pin is left floating, the IC will run with the
free running frequency set by the resistor Rt.
The hiccup is performed by making the internal
SS signal equal to zero and counting the number
of switching cycles. The Soft Start pin is held low
until 4096 cycles have been completed. The
OCP signal resets and the converter recovers.
After every soft start cycle, the converter stays in
this mode until the overload or short circuit is
removed.
Output Voltage Tracking and Sequencing
An optional 10pF-22pF filter capacitor can be
connected from OCSet pin to PGnd. It is
recommended to use this capacitor for very
narrow duty cycle applications (pulse-width
<150ns).
The
IR3837
can
accommodate
user
programmable tracking and/or sequencing
options using Vp, Vref, Enable, and Power Good
pins. In the block diagram presented on page 3,
the error-amplifier (E/A) has been depicted with
three positive inputs. Ideally, the input with the
lower voltage is used for regulating the output
voltage and the other two inputs are ignored. In
practice the voltage of the other two inputs
should be about 200mV greater than the low-
voltage input so that their effects can completely
be ignored. For normal operation, Vp is tied to
Vcc (1.5V < Vp < Vcc) and Vref is left floating
(with a bypass capacitor).
Thermal Shutdown
Temperature sensing is provided inside IR3837.
The trip threshold is typically set to 140oC. When
trip threshold is exceeded, thermal shutdown
turns off both MOSFETs and resets the internal
soft start.
Automatic restart is initiated when the sensed
temperature drops within the operating range.
There is a 20oC hysteresis in the thermal
shutdown threshold.
16
Rev 1.31
IR3837MPbF
Therefore, in normal operating condition, after
Enable goes high the SS ramps up the output
voltage until Vfb (voltage of feedback/Fb pin)
reaches about 0.6V. Then Vref takes over and
the output voltage is regulated (refer to Fig. 11).
Tracking and sequencing operations can be
implemented to be simultaneous or ratiometric
(refer to figures 9 and 10). Figure 8 shows typical
circuit configuration for sequencing operation.
With this power-up configuration, the voltage at
the Vp pin of the slave reaches 0.6V before the
Fb pin of the master. If RE/RF =RC/RD,
simultaneous startup is achieved. That is, the
output voltage of the slave follows that of the
master until the voltage at the Vp pin of the slave
reaches 0.6 V. After the voltage at the Vp pin of
Tracking-mode operation is achieved by
connecting Vref to Vcc (1.5V<Vref<Vcc). Then,
while Vp=0, Enable is taken above its threshold
so that the soft start circuit generates internal SS
signal. After the internal SS signal reaches the
final value (refer to Fig. 4c) ramping up the Vp
input will ramp up the output voltage. In tracking
mode, Vfb always follows Vp which means Vout
is always proportional to Vp voltage (typical for
DDR/Vtt rail applications)
the slave exceeds 0.6V, the internal
0.6V
reference of the slave dictates its output voltage.
In reality the regulation gradually shifts from Vp
to internal Vref. The circuit shown in Fig. 8 can
also be used for simultaneous or ratiometric
tracking operation if Vref of the slave is
In sequencing mode of operation (simultaneous
or ratiometric), Vref is left floating and Vp is kept
to ground level until after SS signal reaches the
final value. Then Vp is ramped up and Vfb
follows Vp. When Vp>0.6V the error-amplifier
switches to Vref and the output voltage is
regulated with Vref.
connected to Vcc. Table
2 on page 18
summarizes the required conditions to achieve
simultaneous / ratiometric tracking or sequencing
operations.
Fig. Typical wavefmr sequencing mode
of oration: (a) simultaneous, (b) ratiometric
Fig. 8. Application Circuit for Simultaneous
and ratiometric Sequencing
Fig. 0 Typical wavorn tracking mode of
operion: (a) simultaneous, (b) ratiometric
17
Rev 1.31
IR3837MPbF
Power Good Output
The IC continually monitors the output voltage via
Feedback (Fb pin). The feedback voltage is
compared to a threshold. The threshold is set
differently at different operating modes and the
results of the comparison sets the PGood signal.
Figures 11, 12, and 13 show the timing diagram
of the PGood signal at different operating modes.
The PGood pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation.
Table 2. The required conditions to achieve simultaneous / ratiometric tracking and sequencing
operations with the circuit configuration of Fig. 8
Operating Mode
Vref (slave)
0.6V (Float)
Vp
Required Condition
-
Normal (Non-Sequencing,
Non-Tracking)
> 1.5V
Simultaneous Sequencing
Ratiometric Sequencing
Simultaneous Tracking
Ratiometric Tracking
0.6V
0.6V
Ramp up from 0V
Ramp up from 0V
Ramp up from 0V
Ramp up from 0V
RA/RB > RE/RF =RC/RD
RA/RB >RE/RF > RC/RD
RE/RF =RC/RD
> 1.5V
> 1.5V
RE/RF >RC/RD
TIMING DIAGRAM OF PGOOD FUNCTIONS
Vref
0.6V
0
2.0V
1.3V
0.7V
SSOK
Internal SS
0
1.15*Vref
Fb
0.85*Vref
0
PGood
0
256/Fs
256/Fs
Fig.11 Non-sequence Startup and Vref Margin (Vp =Vcc)
18
Rev 1.31
IR3837MPbF
TIMING DIAGRAM OF PGOOD FUNCTIONS
Fig.12 Vp Tracking (Vref >1.5V, SS=H)
Fig.13 Vp Sequence and Vref Margin
19
Rev 1.31
IR3837MPbF
Maximum Duty Ratio Considerations
Minimum on time Considerations
A fixed off-time of 300 ns maximum is specified
for the IR3837. This provides an upper limit on
the operating duty ratio at any given switching
frequency. Thus, the higher the switching
frequency, the lower is the maximum duty ratio at
which the IR3837 can operate. To allow some
margin, the maximum operating duty ratio in any
application using the IR3837 should still
accommodate about 500 ns off-time. Fig 14.
shows a plot of the maximum duty ratio v/s the
switching frequency, with 300 ns off-time.
The minimum ON time is the shortest amount of
time for which the Control FET may be reliably
turned on, and this depends on the internal
timing delays. For the IR3837, the typical
minimum on-time is specified as 70 ns.
Any design or application using the IR3837 must
ensure operation with a pulse width that is higher
than this minimum on-time and preferably higher
than 150 ns. This is necessary for the circuit to
operate without jitter and pulse-skipping, which
can cause high inductor current ripple and high
output voltage ripple.
95
90
85
80
75
70
65
60
55
50
Vout
Fs V Fs
D
ton
in
In any application that uses the IR3837, the
following condition must be satisfied:
ton(min) ton
Vout
ton(min)
250
450
650
850
1050
1250
1450
1650
Vin Fs
Switching Frequency (kHz)
Vout
Vin Fs
ton(min)
Fig. 14. Maximum duty cycle v/s switching
frequency.
The minimum output voltage is limited by the
reference voltage and hence Vout(min) = 0.6 V.
Therefore, for Vout(min) = 0.6 V,
Vout(min)
Vin Fs
ton(min)
0.6 V
V Fs
4106 V/s
in
150 ns
Therefore, at the maximum recommended input
voltage 16V and minimum output voltage, the
converter should be designed at a switching
frequency that does not exceed 250 kHz.
Conversely, for operation at the maximum
recommended operating frequency (1.65 MHz)
and minimum output voltage (0.6V), The input
voltage (PVin) should not exceed 2.42V,
otherwise pulse skipping will happen.
At low output voltages (below 1V) specially at
Vo=0.6V, it is recommended to design the
compensator so that the bandwidth of the loop
does not exceed 1/10 of the switching frequency.
20
Rev 1.31
IR3837MPbF
Application Information
Design Example:
R
8
Vo Vref 1
................................(8)
The following example is a typical application for
IR3837. The application circuit is shown on page
27.
R9
When an external resistor divider is connected to
the output as shown in figure 16.
Vin =12 V (13.2V max)
Vo =1.8 V
Equation (8) can be rewritten as:
Vref
Io =14 A
R9 R8
...............................(9)
VoVref
ΔVo ≤ 2%Vo for 30% load transient)
Fs = 600kHz
For the calculated values of R8 and R9 see
feedback compensation section.
VOUT
Enabling the IR3837
IR3837
As explained earlier, the precise threshold of
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage as shown in figure
15.
R
8
Fb
R9
Vin
Fig. 16. Typical application of the IR3837 for
programming the output voltage
IR3837
R1
Enable
R2
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to
supply a gate voltage at least 4V greater than
the voltage at the SW pin, which is connected to
the source of the Control FET . This is achieved
Fig. 15. Using Enable pin for UVLO
implementation
by using
a bootstrap configuration, which
For a typical Enable threshold of VEN = 1.2 V
comprises the internal bootstrap diode and an
external bootstrap capacitor (C6). The operation
of the circuit is as follows: When the sync FET is
turned on, the capacitor node connected to SW
is pulled down to ground. The capacitor charges
towards Vcc through the internal bootstrap diode
(figure 17), which has a forward voltage drop VD.
The voltage Vc across the bootstrap capacitor
C6 is approximately given as
R2
Vin(min)
*
VEN 1.2.......... (6)
R1 R2
VEN
Vin( min ) VEN
R2 R1
.......... (7)
For a Vin (min)=10.2V, R1=49.9K and R2=6.8k ohm
is a good choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 23.7 kΩ, using
Table 1.
Vc Vcc VD .......................... (10)
When the control FET turns on in the next cycle,
the capacitor node connected to SW rises to the
bus voltage Vin. However, if the value of C6 is
appropriately chosen, the voltage Vc across C6
remains approximately unchanged and the
voltage at the Boot pin becomes:
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.6V. The divider ratio
is set to provide 0.6V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
VBoot Vin Vcc VD ........................................(11)
21
Rev 1.31
IR3837MPbF
Inductor Selection
The inductor is selected based on output power,
operating frequency and efficiency requirements.
A low inductor value causes large ripple current,
resulting in the smaller size, faster response to a
load transient but poor efficiency and high output
noise. Generally, the selection of the inductor
value can be reduced to the desired maximum
ripple current in the inductor
point is usually found between 20% and 50%
ripple of the output current.
. The optimum
(i)
For the buck converter, the inductor value for the
desired operating ripple current can be
determined using the following relation:
Fig. 17. Bootstrap circuit to generate
Vc voltage
i
1
Vin Vo L ; t D
t
Fs
............................... (14)
Vo
L
Vin Vo
Vin i* Fs
A bootstrap capacitor of value 0.1uF is suitable
for most applications.
Where:
Vin Maximum input voltage
Vo Output Voltage
Δi Inductor ripple current
Fs Switching frequency
Δt Turn on time
Input Capacitor Selection
The ripple current generated during the on time of
the control FET should be provided by the input
capacitor. The RMS value of this ripple is
expressed by:
D Duty cycle
IRMS Io D(1D) ........................(12)
If Δi ≈ 35%(Io), then the output inductor is
calculated to be 0.52μH. Select L=0.51μH,
59PR9876N, from VITEC which provides a
compact, low profile inductor suitable for this
application.
Vo
D
.............................(13)
V
in
Where:
D is the Duty Cycle
Output Capacitor Selection
IRMS is the RMS value of the input capacitor
current.
The voltage ripple and transient requirements
determine the output capacitors type and values.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent
Series Inductance (ESL) are other contributing
components. These components can be
described as
Io is the output current.
For Io=14A and D = 0.15, the IRMS = 5.0A.
Ceramic capacitors are recommended due to
their peak current capabilities. They also feature
low ESR and ESL at higher frequency which
enables better efficiency. For this application, it is
advisable to have 4x10uF, 16V ceramic
capacitors, ECJ-3YX1C106K from Panasonic. In
addition to these, although not mandatory, a
1x330uF, 25V SMD capacitor EEV-FK1E331P
may also be used as a bulk capacitor and is
recommended if the input power supply is not
located close to the converter.
Vo Vo( ESR ) Vo( ESL ) Vo( C )
Vo( ESR ) IL * ESR
V
Vo
L
in
Vo( ESL )
* ESL
.........................(15)
IL
8* Co * Fs
Vo( C )
22
Rev 1.31
IR3837MPbF
Where:
∆Vo = output voltage ripple
∆IL = Inductor ripple current
Since the output capacitor has a major role in the
overall performance of the converter and
determines the result of transient response,
selection of the capacitor is critical. The IR3837
can perform well with all types of capacitors.
As a rule, the capacitor must have low enough
ESR to meet output ripple and load transient
requirements.
Fig. 8. Gain and Phase of LC ilter
The IR3837 uses a voltage-type error amplifier
with high-gain (110dB) and high-bandwidth
(30MHz). The output of the amplifier is available
for DC gain control and AC phase compensation.
The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore it is advisable to select
ceramic capacitors due to their low ESR and ESL
and small size. Seven of Taiyo Yuden’s
JMK212BJ476MG-T (47uF, 6.3V, ≈3mΩ)
capacitors is a good choice.
The error amplifier can be compensated either in
type II or type III compensation.
Local feedback with Type II compensation is
shown in Fig. 19.
It is also recommended to use a 0.1µF ceramic
capacitor at the output for high frequency
filtering.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. If the output capacitor’s ESR
generates a zero at 5kHz to 50kHz, the zero
generates acceptable phase margin and the
Type II compensator can be used.
Feedback Compensation
The IR3837 is a voltage mode controller. The
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed-loop transfer
function with the highest 0 dB crossing frequency
and adequate phase margin (greater than 45o).
The ESR zero of the output capacitor is
expressed as follows:
1
FESR
...........................(17)
2π*ESR*Co
The output LC filter introduces a double pole,
–40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180o
(see figure 18). The resonant frequency of the LC
filter is expressed as follows:
1
FLC
.............................(16)
2π Lo Co
Figure 18 shows gain and phase of the LC filter.
Since we already have 180o phase shift from the
output filter alone, the system runs the risk of
being unstable.
Fig. 19. Type II compensation network
and its asymptotic gain plot
23
Rev 1.31
IR3837MPbF
The additional pole is given by:
The transfer function (Ve/Vout) is given by:
1
Zf
F
.................................(24)
V
1sRC4
P
e
3
H(s)
.....(18)
C4*CPOLE
C4 CPOLE
2π*R *
V
ZIN
sRC4
3
out
8
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero, expressed by:
The pole sets to one half of the switching
frequency which results in the capacitor CPOLE
:
1
1
CPOLE
....................(25)
R
3
1
H
s
.....................................(19)
............................(20)
π*R *F
3
s
π*R3*F
s
R
8
C4
1
F
z
2π*R *C4
3
For a general solution for unconditional stability
for any type of output capacitors, and a wide
range of ESR values, we should implement local
feedback with a type III compensation network.
The typically used compensation network for
voltage-mode controller is shown in figure 20.
First select the desired zero-crossover frequency
(Fo):
F FESR and F
1/5~1/10*F .......(21)
o
o
s
Use the following equation to calculate R3:
V
OUT
ZIN
C3
V *F *FESR*R
osc
o
8
R
...........................(22)
3
C4
C7
V *F2
R3
in
LC
R8
R10
Zf
Where:
Vin = Maximum Input Voltage
osc = Amplitude of the oscillator Ramp Voltage
Fo = Crossover Frequency
Fb
Ve
E/A
V
R9
Comp
F
F
ESR = Zero Frequency of the Output Capacitor
LC = Resonant Frequency of the Output Filter
V
REF
R8 = Feedback Resistor
Gain (dB)
To cancel one of the LC filter poles, place the
zero before the LC filter resonant frequency pole:
|H(s)| dB
F 75%F
z
LC
Frequency
F
F
F
F
P3
P2
Z1
Z2
1
F 0.75*
.....................................(23)
z
2π L *Co
o
Fig.20. Type III Compensation network and
its asymptotic gain plot
Use equations (20), (21) and (22) to calculate
C4.
One more capacitor is sometimes added in
parallel with C4 and R3. This introduces one
more pole which is mainly used to suppress the
switching noise.
24
Rev 1.31
IR3837MPbF
Again, the transfer function is given by:
Table 3. Different types of compensators
Compensator
Typical Output
Capacitor
F ESR vs F 0
Zf
Ve
Type
H(s)
Type II
Type III
F LC < F ESR < F 0 < F S /2
F LC < F 0 < F ESR
Electrolytic
Vout
ZIN
SP-Cap, Ceramic
By replacing Zin and Zf according to figure 20,
the transfer function can be expressed as:
The higher the crossover frequency is, the
potentially faster the load transient response will
be. However, the crossover frequency should be
low enough to allow attenuation of switching
noise. Typically, the control loop bandwidth or
crossover frequency (Fo) is selected such that
(1sR3C4 )
1sC7
R8 R10
C4 *C3
H(s)
sR (C C ) 1sR
(1sR C )
8
4
3
3
10
7
C4 C3
....(26)
F
1/5~1/10
*F
o
s
The compensation network has three poles and
two zeros and they are expressed as follows:
The DC gain should be large enough to provide
high DC-regulation accuracy. The phase margin
should be greater than 45o for overall stability.
FP1 0............................................................(27)
For this design we have:
Vin=12V
Vo=1.8V
1
FP2
FP3
...........................................(28)
2π* R10 *C7
Vosc=1.8V
1
1
..............(29)
Vref=0.6V
Lo=0.51uH
Co=7x47uF, ESR≈3mΩ each
2π* R3 *C3
C4 *C3
2π* R3
C4 C3
1
FZ1
.........................................(30)
It must be noted here that the value of the
capacitance used in the compensator design
must be the small signal value. For instance, the
small signal capacitance of the 47uF capacitor
used in this design is 26uF at 1.8 V DC bias and
600 kHz frequency. It is this value that must be
used for all computations related to the
compensation. The small signal value may be
obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they
may also be inferred from measuring the power
stage transfer function of the converter and
measuring the double pole frequency FLC and
using equation (16) to compute the small signal
Co.
2π* R3 *C4
1
1
FZ2
..........(31)
2π*C7 *( R8 R10 ) 2π*C7 * R8
Cross over frequency is expressed as:
V
1
in
F R *C7 *
*
................................(32)
o
3
V
2π*L *Co
osc
o
Based on the frequency of the zero generated by
the output capacitor and its ESR, relative to
crossover frequency, the compensation type can
be different. Table 3 shows the compensation
types for relative locations of the crossover
frequency.
These result to:
FLC=16.5 kHz
FESR=2.04 MHz
Fs/2=300 kHz
25
Rev 1.31
IR3837MPbF
Programming the Current-Limit
Select crossover frequency F0=100 kHz
Since FLC<F0<Fs/2<FESR, Type III is selected to
place the pole and zeros.
The Current-Limit threshold can be set by
connecting a resistor (ROCSet) from the SW pin
to the OCSet pin. The resistor can be calculated
by using equation (4). This resistor (ROCSet) must
be placed close to the IC.
Detailed calculation of compensation Type III :
o
Desired Phase Margin 70
The RDS(on) has
a
positive temperature
coefficient and it should be considered for the
worst case operation (40% increase due to
temperature has been considered in below).
1sin
1sin
F F
17.63kHz
Z2
o
ROCSetIOCSet
ISET IL(critical)
.......................(33)
1sin
1sin
RDS(on)
F F
567.1kHz
P2
o
RDS( on ) 5.3 mΩ*1.4 7.42 mΩ
Select: F 0.5*F 8.82 kHz and
ISET Io( LIM ) 14 A*1.5 21A
Z1
Z2
(50% over nominal output current )
IOCSet 29.54 μA (at Fs 600 kHz)
ROCSet 5.28 kΩ Select ROCSet 5.23 kΩ
F 0.5*F 300 kHz
P3
s
Select:C7 2.2nF
The optional filter capacitor from OCSet pin to
PGnd has not been used for this design.
Calculate R , C3 and C4 :
3
Setting the Power Good Threshold
2π*F *L *Co *V
o
o
R
osc ;R 3.98 kΩ
In this design IR3837 is used in normal (non-
tracking, non-sequencing) mode, therefore the
PGood thresholds are internally set at 85% and
115% of Vref. At startup as soon as the internal
soft start signal reaches 2V (Figure 11), and
assuming Fb voltage follows Vref, the PGood is
asserted. As long as the voltage at the Fb pin is
between the thresholds (mentioned above),
Enable is high, and no fault happens, the PGood
remains high.
3
3
C7 *V
in
Select: R 4.02k
3
1
C4
C3
;C4 4.49 nF, Select: C4 4.7 nF
;C3 132 pF, Select:C3 120pF
2π*F *R
Z1
3
1
2π*F *R
P3
3
The PGood is an open drain output. Hence, it is
necessary to use a pull up resistor, RPG, from
PGood pin to Vcc. The value of the pull-up
resistor must be chosen such as to limit the
current flowing into the PGood pin to less than
5mA when the output voltage is not in regulation.
A typical value used is 10kΩ.
Calculate R , R and R :
10
8
9
1
R
; R 127.5Ω, Select:R 127Ω
10
10
10
2π*C7 *F
P2
Vref Bypass Capacitor
1
R
-R ; R 3.98kΩ,
8
10
8
A bypass capacitor of about 0.1uF is required to
be placed between Vref and Gnd pins. This
capacitor should be placed as close as possible
to Vref pin.
2π*C7 *F
Z2
Select:R 4.02kΩ
8
V
ref
R
*R ;R 2.01kΩ Select:R 2 kΩ
9
8
9
9
V -V
o
ref
26
Rev 1.31
IR3837MPbF
Application Diagram:
Fig. 21. Application circuit diagram for a 12V to 1.8 V, 14 A Point Of Load Converter
Suggested Bill of Materials for the application circuit:
Part Reference
Cin
Quantity
Value
1 330uF
4 10uF
1 0.51uH
7 47uF
1 49.9K
1 6.8K
Description
Manufacturer
Panasonic
Part Number
SMD Elecrolytic, Fsize, 25V, 20%
1206, 16V, X7R, 20%
EEV-FK1E331P
ECJ-3YX1C106K
59PR9876N
Panasonic - ECG
Vitec
Lo
11x7.2x7.5mm, 20%, 0.29mΩ
Ceramic, 6.3V, 0805, X5R,20%
Thick Film, 0603,1/10 W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10 W,1%
Thick Film, 0603,1/10W,1%
0603, 25V, X7R, 10%
Co
Taiyo Yuden
Rohm
JMK212BJ476MG-T
MCR03EZPFX4992
MCR03EZPFX6801
MCR03EZPFX2372
MCR03EZPFX5231
MCR03EZPFX1002
ECJ-1VB1E104K
MCR03EZPFX4021
ECJ-1VC1H121J
ECJ-1VB1H472K
ECJ-1VB1E104K
MCR03EZPFX4021
MCR03EZPFX2001
ERJ-3EKF1270V
ECJ-1VB1H222K
ECJ-1VB1A225K
IR3837MPbF
R1
R2
Rohm
Rt
1 23.7k
1 5.23k
1 10K
Rohm
ROCSet
RPG
Cref
R3
Rohm
Rohm
1 0.1uF
1 4.02k
1 120pF
1 4.7nF
1 0.1uF
1 4.02K
1 2.0K
Panasonic - ECG
Rohm
Thick Film, 0603,1/10W,1%
50V, 0603, NPO, 5%
C3
Panasonic- ECG
Panasonic - ECG
Panasonic - ECG
Rohm
C4
0603, 50V, X7R, 10%
C6
0603, 25V, X7R, 10%
R8
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
0603, 50V, X7R, 10%
R9
Rohm
R10
C7
1 127
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
International Rectifier
1 2200pF
1 2.2uF
1 IR3837
CVcc
U1
0603, 10V, X5R, 10%
SupIRBuck, 14A, PQFN 5x6mm
27
Rev 1.31
IR3837MPbF
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc/LDO_out=5.2V, Vo=1.8V, Io=0-14A, Room Temperature, No Air Flow
Fig. 22: Start up at 14A Load (Note 6)
Ch1:Vout Ch2:PGood Ch3:EN Ch4: Vin
Fig. 23: Start up at 14A Load (Note 6)
Ch1:Vout Ch2:PGood Ch3:Vcc Ch4: Vin
Fig. 25: Output Voltage Ripple, 14A
load Ch1: Vout
Fig. 24: Start up with 1.62V Prebias,
0A Load, Ch1:Vout Ch2: PGood Ch3: EN
Fig. 27: Short (Hiccup) Recovery
Ch1:Vout, Ch2:PGood , Ch4:Iout
Fig. 26: Inductor node at 14A load
Ch3:SW
28
Rev 1.31
IR3837MPbF
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc/LDO_out=5.2V, Vo=1.8V, Room Temperature, No Air Flow
Fig. 28: Transient Response
1.4A(10%)-5.6A(40%) load (0.5A/us) Ch1:Vout, Ch4:Io
Note6: Enable (EN) is tied to Vin via a resistor divider and triggered when Vin is exceeding above 10.2V.
29
Rev 1.31
IR3837MPbF
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc/LDO_out=5.2V, Vo=1.8V, Io=0-14A, Room Temperature, No Air Flow
Fig.29: Bode Plot at 10A load shows a bandwidth of 93kHz and phase margin of 49 degrees
30
Rev 1.31
IR3837MPbF
Layout Considerations
The connection between the OCSet resistor and
the SW pin should not share any trace with the
connection between the bootstrap capacitor and
the SW pin. Instead, it is recommended to use a
Kelvin connection of the trace from the OCSet
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Make all the connections for the power
components in the top layer with wide, copper
filled areas or polygons. In general, it is desirable
to make proper use of power planes and
polygons for power distribution and heat
dissipation.
The inductor, output capacitors and the IR3837
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at
the PVin pin of IR3837.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vin, Vcc, Vref and Vp should be
close to their respective pins. It is important to
place the feedback components including
Vin
PGnd
resistor and the trace from the bootstrap
Vin
capacitor at the SW pin. PAGlsnod, place the OCset
resistor close to the device.
In a multilayer PCB use one layer as a power
Vout
AGnd
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
Vout
AGnd
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
It is recommended to place all the compensation
parts over the analog ground plane in top layer.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias. Figure 30 illustrates the
implementation of the layout guidelines outlined
above, on the IRDC3837 4 layer demoboard.
feedback
resistors
and
compensation
components close to Fb and Comp pins.
Enough copper &
minimum length
ground path between
Input and Output
AGnd
Vin
PGnd
All bypass caps
should be placed as
close as possible to
their connecting
pins.
Compensation parts
should be placed as
close as possible to
the Comp pin.
Resistors Rt and
R
OCSet should be
Vout
placed as close as
possible to their pins.
PGnd
Fig. 30a. IRDC3837 Demoboard layout
considerations – Top Layer
31
Rev 1.31
IR3837MPbF
Boot cap uses separate
trace from ROCSet to be
connected to SW node
PGnd
Fig. 30b. IRDC3837 demoboard layout
considerations – Bottom Layer
Power Ground plane
Analog Ground plane
Feedback trace
should be kept
away form noise
sources
Single point connection
between AGND &
PGND, should be close
to the SupIRBuck, kept
away from noise
sources.
Fig. 30c. IRDC3837 demoboard layout
considerations – Mid Layer 1
The trace which
connects ROCSet
to SW node is
separated from
the trace which
connect Boot
Cap to SW node
Fig. 30d. IRDC3837 demoboard layout
considerations – Mid Layer 2
32
Rev 1.31
IR3837MPbF
PCB Metal and Components Placement
Evaluations have shown that the best overall performance is achieved using the substrate/PCB
layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm
on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and
experiments should be run to confirm the limits of self-centering on specific processes. For further
information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead
(PQFN) Board Mounting Application Note.” (AN-1132)
PCB metal pad sizing (all dimensions in mm)
PCB metal pad spacing (all dimensions in mm)
33
Rev 1.31
IR3837MPbF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should
be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto
the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the high
aspect ratio of the solder resist strip separating the lead lands from the pad land.
34
Rev 1.31
IR3837MPbF
Stencil Design
Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner
than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder
joints with the ground pad; high reductions sometimes create similar problems. Stencils in the
range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results.
Evaluations have shown that the best overall performance is achieved using the stencil design
shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction
should be adjusted for stencils of other thicknesses.
Stencil pad sizing (all dimensions in mm)
Stencil pad spacing (all dimensions in mm)
35
Rev 1.31
IR3837MPbF
MILIMITERS
MIN MAX
INCHES
MIN MAX
MILIMITERS
INCHES
DIM
DIM
MIN
MAX
MIN
MAX
A
A1
b
b1
c
D
E
e
e1
e2
0.800 1.000 0.0315 0.0394
0.000 0.050 0.0000 0.0020
0.375 0.475 0.1477 0.1871
0.250 0.350 0.0098 0.1379
L
M
N
O
P
Q
R
0.350
2.441
0.703
2.079
3.242
1.265
2.644
1.500
0.450 0.0138 0.0177
2.541 0.0961 0.1000
0.803 0.0277 0.0316
2.179 0.0819 0.0858
3.342 0.1276 0.1316
1.365 0.0498 0.0537
2.744 0.1041 0.1080
1.600 0.0591 0.0630
0.203 REF.
5.000 BASIC
6.000 BASIC
1.033 BASIC
0.650 BASIC
0.852 BASIC
0.008 REF.
1.969 BASIC
2.362 BASIC
0.0407 BASIC
0.0256 BASIC
0.0335 BASIC
S
t1, t2, t3
t4
0.401 BASIC
1.153 BASIC
0.727 BASIC
0.016 BACIS
0.045 BASIC
0.0286 BASIC
t5
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market (Note5)
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 09/11
36
Rev 1.31
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