L7833S [INFINEON]
HEXFETPower MOSFET; HEXFETPower MOSFET
| 型号： | L7833S |
| 厂家： | 
Infineon |
| 描述： | HEXFETPower MOSFET |
| 文件： | 总12页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94668B
IRL7833
IRL7833S
IRL7833L
HEXFET® Power MOSFET
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Consumer Use
VDSS RDS(on) max
Qg
32nC
3.8m
30V
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D2Pak
IRL7833S
TO-262
IRL7833L
TO-220AB
IRL7833
Absolute Maximum Ratings
Parameter
Max.
Units
VDS
Drain-to-Source Voltage
30
V
V
Gate-to-Source Voltage
± 20
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
150
110
600
I
I
I
@ TC = 25°C
@ TC = 100°C
D
D
A
DM
Maximum Power Dissipation
Maximum Power Dissipation
P
P
@TC = 25°C
@TC = 100°C
140
72
W
D
D
Linear Derating Factor
Operating Junction and
0.96
W/°C
°C
T
-55 to + 175
J
T
Storage Temperature Range
STG
Mounting Torque, 6-32 or M3 screw
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
Max.
1.04
–––
62
Units
Rθ
Rθ
Rθ
Rθ
Junction-to-Case
–––
0.50
–––
–––
JC
CS
JA
JA
Case-to-Sink, Flat, Greased Surface
°C/W
Junction-to-Ambient
Junction-to-Ambient (PCB Mount)
40
Notes through are on page 12
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1
4/22/04
IRL7833/S/L
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
Drain-to-Source Breakdown Voltage
30
–––
–––
V
VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ
RDS(on)
Breakdown Voltage Temp. Coefficient –––
18
––– mV/°C Reference to 25°C, ID = 1mA
Ω
m
Static Drain-to-Source On-Resistance
–––
–––
1.4
3.1
3.7
–––
-11
–––
–––
–––
–––
–––
32
3.8
4.5
2.3
V
GS = 10V, ID = 38A
GS = 4.5V, ID = 30A
V
VGS(th)
Gate Threshold Voltage
V
VDS = VGS, ID = 250µA
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
150
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
––– mV/°C
1.0
150
100
-100
–––
47
µA
nA
S
V
DS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
GS = 20V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
V
VGS = -20V
gfs
VDS = 15V, ID = 30A
Qg
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
td(on)
tr
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
8.7
5.1
13
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
V
DS = 16V
GS = 4.5V
nC
V
ID = 30A
Gate Charge Overdrive
5.3
18
See Fig. 16
Switch Charge (Qgs2 + Qgd)
Output Charge
22
nC VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
ns ID = 26A
Turn-On Delay Time
Rise Time
18
50
td(off)
tf
Turn-Off Delay Time
Fall Time
21
Clamped Inductive Load
6.9
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 4170 –––
VGS = 0V
pF VDS = 15V
ƒ = 1.0MHz
–––
–––
950
470
–––
–––
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
560
30
Units
mJ
A
EAS
IAR
Avalanche Current
Repetitive Avalanche Energy
EAR
14
mJ
Diode Characteristics
Parameter
Continuous Source Current
Min. Typ. Max. Units
Conditions
MOSFET symbol
D
IS
–––
–––
150
(Body Diode)
A
showing the
G
ISM
Pulsed Source Current
–––
–––
600
integral reverse
S
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
42
1.2
63
51
V
T = 25°C, I = 30A, V = 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
ns T = 25°C, I = 30A, VDD = 15V
J F
Qrr
di/dt = 100A/µs
34
nC
2
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IRL7833/S/L
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
7.0V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
7.0V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM
BOTTOM
2.7V
2.7V
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
100
1000
0.1
1
10
100
1000
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
1000
100
10
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
1.5
1.0
0.5
T
= 25°C
4.0
J
V
= 15V
DS
20µs PULSE WIDTH
-60 -40 -20
T
0
20 40 60 80 100 120 140 160 180
2.0
3.0
V
5.0
6.0
7.0
8.0
, Junction Temperature (°C)
, Gate-to-Source Voltage (V)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRL7833/S/L
100000
12.0
10.0
8.0
V
= 0V,
f = 1 MHZ
GS
I
= 30A
C
= C + C , C SHORTED
D
iss
gs gd ds
C
= C
rss
gd
V
V
= 24V
= 15V
C
= C + C
ds gd
oss
DS
DS
10000
1000
100
C
C
iss
6.0
oss
4.0
C
rss
2.0
0.0
1
10
, Drain-to-Source Voltage (V)
100
0
5
10 15 20 25 30 35 40
Total Gate Charge (nC)
V
Q
DS
G
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.00
100.00
10.00
1.00
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
T
= 175°C
J
100µsec
1msec
T
= 25°C
J
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
0.10
0.1
0.0
0.5
V
1.0
1.5
2.0
2.5
3.0
1
10
, Drain-to-Source Voltage (V)
DS
100
, Source-to-Drain Voltage (V)
V
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRL7833/S/L
2.5
2.0
1.5
1.0
0.5
0.0
160
120
80
40
0
LIMITED BY PACKAGE
I
= 250µA
D
25
50
75
100
125
150
175
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
TC, Case Temperature (°C)
T
J
Fig 9. Maximum Drain Current Vs.
Fig 10. Threshold Voltage Vs. Temperature
Case Temperature
10
1
D = 0.50
0.20
P
DM
0.10
0.05
0.1
t
1
t
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL7833/S/L
15V
2000
1600
1200
800
400
0
I
D
TOP
12A
21A
30A
DRIVER
+
L
V
BOTTOM
DS
D.U.T
AS
R
G
V
DD
-
I
A
2
VGS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I
AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
-
VDD
D.U.T
Current Regulator
VGS
Same Type as D.U.T.
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
.2µF
12V
.3µF
Fig 14a. Switching Time Test Circuit
VDS
+
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
VGS
I
I
D
G
Current Sampling Resistors
td(on)
td(off)
tr
tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRL7833/S/L
Driver Gate Drive
P.W.
P.W.
D =
D.U.T
Period
Period
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
+
-
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRL7833/S/L
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
drive output
loss
conduction
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
Qoss
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
in rr in
(
)
2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on )
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
Qgd
ig
Qgs2
ig
+ I ×
× V × f + I ×
× V × f
in
in
+ Q × V × f
(
Qoss
)
g
g
+
×V × f
in
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFETdata sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRL7833/S/L
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
- B -
3.78 (.149)
3.54 (.139)
2.87 (.113)
2.62 (.103)
4.69 (.185)
4.20 (.165)
1.32 (.052)
1.22 (.048)
- A -
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
LEAD ASSIGNMENTS
1 - GATE
1
2
3
2 - DRAIN
3 - SOURCE
4 - DRAIN
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
0.93 (.037)
0.69 (.027)
0.55 (.022)
0.46 (.018)
3X
3X
1.40 (.055)
3X
1.15 (.045)
0.36 (.014)
M
B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE : THIS IS AN IRF1010
WITH ASSEMBLY
A
INTERNATIONAL
RECTIFIER
PART NUMBER
LOT CODE 9B1M
IRF1010
9246
LOGO
9B 1M
DATE CODE
(YYWW)
ASSEMBLY
LOT CODE
YY = YEAR
WW = WEEK
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9
IRL7833/S/L
D2Pak Package Outline
D2Pak Part Marking Information
10
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IRL7833/S/L
TO-262 Package Outline
TO-262 Part Marking Information
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11
IRL7833/S/L
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
26.40 (1.039)
24.40 (.961)
4
3
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Notes:
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 1.3mH, RG = 25Ω, IAS = 30A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A.
ꢀ When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994.
This is only applied to TO-220AB package.
TO-220AB package isnot recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/04
12
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