MA12070P_技术文档

MA12070P

Filterless and High-Efficiency +4V to +26V

Audio Amplifier with I²S Digital Input

Description

Features

The MA12070P is a super-efficient audio power

amplifier based on proprietary multi-level switching

technology. It supports a 4-26V supply voltage range,

allowing it to be used in many different applications.

•

Proprietary Multi-level Switching Technology

◦

3-level and 5-level modulation

◦

Low EMI emission

Filterless amplification

Multi-level switching enables very low power loss

during operation. In addition, it allows the amplifier to

be used in filterless configurations at full rated power

in a wide range of audio products.

◦

Digital Power Management Algorithm

•

High Power Efficiency (PMP4)

◦

400mW Idle power dissipation (26V PVDD, all

channels switching)

>80% Efficiency at 2W power (1kHz sine, 8Ω)

>92% Efficiency at Full Power (1kHz sine, 8Ω)

The MA12070P features an embedded digital power

management scheme. The power management

algorithm dynamically adjusts switching frequency and

modulation to optimize power loss and EMI across the

output power range.

◦

Audio Performance (PMP2)

◦

>101dB DNR (A-w, rel. to 1% THD+N power

level)

140µV output integrated noise (A-w)

0.007% THD+N at high output levels

An integrated digital-to-analog converter enables

digital I2S audio stream input. It supports sample rates

from 44.1 kHz to 192 kHz.

◦

•

4^thOrder Feedback Error Control

Highly flexible output stage configurations are offered,

ranging from four single-ended outputs to a single

parallel-BTL output.

◦

High suppression of supply disturbance

HD audio quality

Supply Voltages: +4V to +26V (PVDD) and +5V

(A/DVDD)

Volume Control and Limiter

The MA12070P features protection against DC, short-

circuits,

over-temperature

and

under-voltage

•

situations.

2x30W continuous output power (RL = 8Ω at 22V,

Flexible “Power Mode Profiles” allow the user to utilize

the multi-level switching technique for very low power

loss or very high audio performance.

PMP4, 10% THD+N level, without heatsink)

2×80W peak output power (26V PVDD, R_L= 4Ω,

10% THD+N level)

•

2.0, 2.1, 4.0, 1.0 Output Stage Configurations

Protection

Device communication and programming is controlled

through an I2C interface as well as dedicated control

pins.

◦

Under-voltage-lockout

Over-temperature warning/error

Short-circuit/overload protection

Power stage pin-to-pin short-circuit

Error-reporting through serial interface (I2C)

DC protection

Applications

•

Battery Operated Speakers

Wireless and Docking Speakers

Soundbars

Multiroom Systems

Home Theater Systems

•

I2C control (four selectable addresses)

Heatsink free operation with EPAD-down package

Package

•

64-pin QFN Package with exposed thermal pad

(EPAD) and Lead-free Soldering

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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V 1.1

2022-02-09

1 Ordering Information

Table 1-1

Moisture

Sensitivity Level

Part Number

MA12070P

Package

Description

Quad Flat No-leads package, EPAD-down (exposed thermal pad on

bottom side)

QFN-64

Level 3

2 Known Issues and Limitations

Please refer to the errata sheet document for descriptions of issues and limitations relating to device operation and performance.

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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3 Typical Application Block Diagram

100nF

C_FGD

1µF

C_GD0

1µF

C_GD1

1µF

C_FDC

VDD

C_GDC

1µF

AVDD

DVDD

1µF

AVSS

CREF

CMSE

DVSS

CDC

Analog

power

and

reference

voltages

C_DC

PVDD

1µF

Charge pump power supplies

1µF

PVDD

1µF 1µF

470µF

PVSS

Audio source

PVDD

Power

SD0

SD1

Data pair 0

(0L,0R)

DAC

OUT0A

CF0AP

CF0AN

amp

2x10µF

DAC

C_F0A

PVSS

0L

PVDD

Power

amp

OUT0B

CF0BP

CF0BN

2x10µF

C_F0B

PVSS

SCK

WS

CLK

CLKM/S

PVDD

Power

management

Clock and

timing

Clock

management

Power

amp

OUT1A

CF1AP

CF1AN

2x10µF

C_F1A

Temp sensor

PVSS

0R

PVDD

Control and protection

Power

amp

OUT1B

CF1BP

CF1BN

2x10µF

C_F1B

EMC filter

depending on

application

PVSS

EPAD

5V

Host system

Figure 3-1 Typical application block diagram

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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4 Pin Description

4.1 Pinout MA12070P

Top view

Pin 1

Indicator

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

PVSS

⁴⁸PVSS

PVSS

CF0AN

OUT0A

CF0AP

PVDD

⁴⁷PVSS

⁴⁶CF1AN

⁴⁵OUT1A

⁴⁴OUT1A

⁴³CF1AP

⁴²PVDD

⁴¹PVDD

⁴⁰CF1BP

³⁹OUT1B

³⁸OUT1B

³⁷CF1BN

exposed thermal

pad on bottom side

PVDD

CF0BP

OUT0B

CF0BN

PVSS

36

PVSS

³⁵PVSS

³⁴/MUTE

³³/ENABLE

/CLIP

/ERROR

Figure 4-1 Pinout MA12070P

Datasheet

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4.2 Pin Function

Table 4-1

Pin No.

Name

Type¹

Description

1

2

PVSS

P

Power ground for internal power amplifiers

3

CF0AN

OUT0A

CF0AP

PVDD

CF0BP

OUT0B

CF0BN

PVSS

P

Connect to external flying capacitor negative terminal for amplifier channel 0A

Audio power output 0A

4

O

P

5

Audio power output 0A

6

Connect to external flying capacitor positive terminal for amplifier channel 0A

Power supply for internal power amplifiers

7

P

8

P

Power supply for internal power amplifiers

9

P

Connect to external flying capacitor positive terminal for amplifier channel 0B

Audio power output 0B

10

11

12

13

14

15

16

17

18

O

P

Audio power output 0B

Connect to external flying capacitor negative terminal for amplifier channel 0B

Power ground for internal power amplifiers

P

PVSS

P

Power ground for internal power amplifiers

/CLIP

O

P

Audio clipping indicator (open drain output), pulled low when clipping occurs

Error indicator (open drain output), pulled low when an error occurs

Power supply for internal analog circuitry

/ERROR

AVDD

CMSE

O

Decoupling pin for internally generated common-mode voltage in SE configuration.

Should be externally decoupled to AVSS. Can be left floating for 2 x BTL and PBTL

configurations.

19

20

AVSS

CREF

P

Ground for internal analog circuitry

O

Decoupling pin for internally generated analog reference voltage. Should be externally

decoupled to AVSS.

21

22

23

24

25

26

27

28

29

30

31

32

33

SCK

WS

I

I2S, digital audio serial clock. Must be synchronized to CLK

I2S, digital audio word select. Must be synchronized to CLK

I2S, digital audio serial data pair 0

SD0

I

SD1

I

I2S, digital audio serial data pair 1

AVSS

DVSS

SCL

P

IO

I

Ground for internal analog circuitry

Ground for internal digital circuitry

I2C bus serial clock

AD0

I2C device address select 0 (see “MCU/Serial control interface” section)

I2C device address select 1 (see “MCU/Serial control interface” section)

I2C bus serial data

AD1

I

SDA

IO

I

CLKM/S

CLK

Reserved - must be pulled low

I

Clock input. Must be present before enabling the amplifier.

/ENABLE

I

When pulled high, the device is reset and kept in an inactive state with minimum power

consumption.

34

35

36

37

38

39

40

/MUTE

PVSS

I

Mute audio output when pulled low

P

O

P

Power ground for internal power amplifiers

Connect to external flying capacitor negative terminal for amplifier channel 1B

Audio power output 1B

PVSS

CF1BN

OUT1B

CF1BP

Audio power output 1B

Connect to external flying capacitor positive terminal for amplifier channel 1B

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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Pin No.

41

Name

PVDD

CF1AP

OUT1A

CF1AN

PVSS

Type¹

Description

P

O

P

I

Power supply for power amplifiers

42

Power supply for power amplifiers

43

Connect to external flying capacitor positive terminal for amplifier channel 1A

Audio power output 1A

44

45

Audio power output 1A

46

Connect to external flying capacitor negative terminal for amplifier channel 1A

Power ground for internal power amplifiers

Internally connected to DVDD – should be not connected

SE/BTL/PBTL configuration select 1

47

48

PVSS

49

NC

50

MSEL1

MSEL0

CGD1N

51

I

SE/BTL/PBTL configuration select 0

52

P

Connect to external decoupling capacitor negative terminal for internal gate driver

power supply 1

53

54

CGD1P

VGDC

P

Connect to external decoupling capacitor positive terminal for internal gate driver

power supply 1

Internally generated virtual ground voltage for digital core. Should be decoupled to

DVDD.

55

56

57

DVDD

CDC

P

Power supply for internal digital circuitry and charge pumps

Connect to external decoupling capacitor for digital core internal power supply

CFDCP

Connect to external flying capacitor positive terminal for internal digital core power

supply

58

CFDCN

P

Connect to external flying capacitor negative terminal for internal digital core power

supply

59

60

DVSS

P

Power ground for internal digital circuitry

CGD0P

Connect to external decoupling capacitor positive terminal for internal gate driver

power supply 0

61

62

63

64

CGD0N

CFGDP

CFGDN

NC

P

Connect to external decoupling capacitor negative terminal for internal gate driver

power supply 0

Connect to external flying capacitor positive terminal for internal gate driver power

supplies

Connect to external flying capacitor negative terminal for internal gate driver power

supplies

Internally connected to DVDD - should be not connected

Type¹: P = Power; I = Input; O = Output; IO = Input or Output

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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5 Absolute Maximum Ratings

Table 5-1

Parameter

Value

Unit

Power Supplies

Power stage supply voltage, PVDD

System supply voltage, DVDD, AVDD

Input / Output

-0.5 to +27.5

-0.5 to +6.0

V

Logic: /ENABLE, /MUTE, /ERROR, /CLIP, MSEL0, MSEL1,

CLKM/S, CLKIO, SCL, SDA, AD0, AD1

Output current, Logic and Interface

-0.5 to +6.0

25

V

mA

Thermal Conditions

-40 to +85

-40 to +150

-65 to +150

23

°C

Ambient temperature range, T_A

Junction temperature range, T_J

Storage temperature range

°C

Thermal resistance, Junction-to-Ambient

Thermal resistance, Junction-to-EPAD

Lead soldering temperature, 10s

°C/W

°C

2.3

+300

Electrostatic Discharge (ESD)

Human body model (HBM)

Charged device model (CDM)

± 2000

± 1000

V

PLEASE NOTE:

Device usage beyond the above stated ratings may cause permanent damage to the device. Permanent usage at the above stated ratings may limit

device lifetime and result in reduced reliability. This is a stress rating only; functional operation of the device at these or any other conditions above

those indicated in the operational section of this specification is not implied.

See “Recommended Operation Conditions” for continuous functional ratings.

Datasheet

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6 Recommended Operating Conditions

Table 6-1

Symbol

PVDD

Parameter

Power Stage Power Supply

Min

5

Typ

Max

26

Unit

V

DVDD

AVDD

V_{IH_3V3}

Digital Power Supply

4.75

5

5.25

Analog Power Supply

High Level for:

/ENABLE, /MUTE, /ERROR, /CLIP, CLKIO, SCL, SDA, AD0, AD1

Low Level for:

2

V

V_{IL_3V3}

/ENABLE, /MUTE, /ERROR, /CLIP, CLKIO, SCL, SDA, AD0, AD1

High Level for MSEL0, MSEL1, CLKM/S

Low Level for MSEL0, MSEL1, CLKM/S

DC Offset Level for Analog Inputs

Audio Signal Level for Analog Inputs

Minimum Load in Bridge-Tied Load Mode

Minimum Load in Parallel Bridge-Tied Load Mode

Minimum Load in Single Ended Mode

0.8

V

V_{IH_5V0}

V_{IL_5V0}

3.5

1.2

0.8

3.8

V

V_{IN_dc}

2.5

1.8

4

V

V_{IN_ac}

Vpp

Ω

R_L(BTL)

R_L(PBTL)

R_L(SE)

3.2

1.6

2.4

2

Ω

3

Ω

Minimum required equivalent load inductance per output pin

for short circuit protection

L_Leq

0.5

0

µH

°C

T_A

Ambient temperature range

+25

+85

Note: Minimum Load resistance was measured in Filterless output condition.

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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7 Electrical and Audio Characteristics

Table 7-1

Power Mode Profile = 0; VDD (Analog & Digital) = +5V; PVDD = +26V; T_A= 0°C to +85°C. Typical values are at T_A= +25°C

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Output Power per channel (peak),

Without Heatsink, see Note 1

THD+N = 10%, RL = 8Ω, f = 1kHz

45

W

P_OUT(BTL)

THD+N = 10%, RL = 4Ω, f = 1kHz

THD+N = 1%, RL = 8Ω, f = 1kHz

THD+N = 1%, RL = 4Ω, f = 1kHz

80

35

60

W

Output Power per channel

(continuous) Without Heatsink,

see Note 2

RL = 8Ω, f = 1kHz, PVDD = +22V

30

W

Output Power (peak), see Note 1

THD+N = 10%, RL = 2Ω, f = 1kHz

THD+N = 1%, RL = 2Ω, f= 1kHz

THD+N = 10%, RL = 4Ω, f = 1kHz

THD+N = 10%, RL = 3Ω, f = 1kHz

THD+N = 1%, RL = 4Ω, f = 1kHz

THD+N = 1%, RL = 3Ω, f = 1kHz

NENABLE = 1 → 0

160

120

20

W

P_OUT(PBTL)

P_OUT(SE)

Output Power per channel (peak),

see Note 1

W

25

W

15

W

20

W

T_ENABLE

T_MUTE

Shutdown/Full Operation Timing

Mute/Unmute Timing

1

ms

mV

dB

Ω

NMUTE = 1 → 0 and 0 → 1

0.3

Output Offset Voltage, see Note 4

Output Offset Voltage, see Note 4,5

Power Supply Rejection Ratio

Resistance, switch on

±35

V_OS,BTL/PBTL

V_OS,SE

PSRR

50

70

± 100mVpp ripple voltage

0.10

618

316

158

0.15

672

336

168

0.20

726

R_on

Power Mode A

Power Mode B & C

Power Mode D

kHz

MHz

A

Power MOSFET Switching

Frequency, see Note 3

356

f_SW

178

Clock Output Frequency

Maximum Output Current

Crosstalk

2.7151 2.8224

2.9296

f_{CLK_IO}

8

I_OUT/OCP_THR

X_Talk

BTL, POUT = 1W, f=1kHz, Ch1 & 2

-108

dB

Note 1: The thermal design of the target application will significantly impact the ability to achieve the peak output power levels for extended time.

See “Thermal Characteristics and Test Signals” section for thermal optimization recommendations.

Note 2: Continuous power measurements were performed on the MA12070 proprietary Amplifier EVK without heatsinking at 25⁰C ambient

temperature in Power Mode Profile 4.

Note 3: Power MOSFET switching frequency depends on which properties are assigned to the individual power modes of the device. Detailed

information on this can be found in “Power Mode Management” section.

Note 4: Offset is specified as the voltage difference between the “mute” and “unmute” state.

Note 5: The offset number is only guaranteed for the SE channels in 2.1 configuration.

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Table 7-2

VDD (Analog & Digital) = +5V; PVDD = +26V; Typical values are at T_A= +25°C; Output Configuration: BTL

Symbol

Parameter

Conditions

Min

Typ

91

Max

Unit

%

η

Efficiency

POUT = 2×40W, 8Ω , PMP = 0

POUT = 2×40W, 8Ω , PMP = 1

POUT = 2×40W, 8Ω , PMP = 2

91

%

89

%

POUT = 2×40W, 8Ω , PMP = 4

POUT = 2×80W, 4Ω , PMP = 0

POUT = 2×80W, 4Ω , PMP = 1

POUT = 2×80W, 4Ω , PMP = 2

POUT = 2×80W, 4Ω , PMP = 4

92

87

86

88

%

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Table 7-3

Power Mode Profile = 0; VDD (Analog & Digital) = +5V; PVDD = +26V; T_A= 0°C to +85°C. Typical values are at T_A= +25°C.

Symbol

I_shutdown

I_idle,mute

Parameter

Conditions

Min

Typ

Max Unit

Current Consumption, PVDD

Shutdown

10

35

180

12

µA

mA

%

Current Consumption, PVDD

Current Consumption, AVDD+DVDD

Idle, mute

4

6

9

Idle, unmute, inputs grounded

1kHz, POUT = 1W, RL = 4Ω

1kHz, POUT = 20W, RL = 4Ω

20-20kHz, A-weighted

18

I_idle,unmute

I_DVDD+AVDD

30

35

42

0.013

0.014

100

150

THD+N

Total Harmonic Distortion + Noise

%

DNR

Dynamic Range¹

dB

V_noise

Output integrated noise level

105

190

µVrms

Table 7-4

Power Mode Profile = 2; VDD (Analog & Digital) = +5V; PVDD = +26V; T_A= 0°C to +85°C. Typical values are at T_A= +25°C.

Symbol

I_shutdown

I_idle,mute

Parameter

Conditions

Min

Typ

Max Unit

Current Consumption, PVDD

Shutdown

10

35

180

12

µA

mA

%

Current Consumption, PVDD

Current Consumption, AVDD+DVDD

Idle, mute

4

6

Idle, unmute, inputs grounded

1kHz, POUT = 1W, RL = 4Ω

1kHz, POUT = 20W, RL = 4Ω

20-20kHz, A-weighted

11

22

I_idle,unmute

I_DVDD+AVDD

33

38

45

0.012

0.016

101

140

THD+N

Total Harmonic Distortion + Noise

%

DNR

Dynamic Range¹

dB

V_noise

Output integrated noise level

110

170

µVrms

¹Output power at THD+N < 1% reference to noise floor at -60dBFS signal.

NOTE: MA12070P gives users the freedom to choose Power Mode Profiles (PMP) independently. As noted in the specifications table, the choice in

power mode profiles gives a trade-off between power efficiency and audio performance as an individual set of performance characteristics. See

“Power Mode Profiles” section for more details.

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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8 Functional description

Multi-level modulation

The power stage of the MA12070P is a true multi-level switching topology. Each half-bridge is capable of delivering a

PWM output with three voltage levels, rather than the conventional two. The three-level half-bridges are each driven

with a two-phase PWM signal, so that the switching frequency seen at the PWM output is twice that of the individual

power MOSFET switching frequency.

For very low EMI in BTL configuration, the two half-bridges are operated in a complementary fashion (i.e. with 240⁰

phase shift), which removes common-mode PWM output content. This configuration is ideal for driving long speaker

cables without an output filter. Differentially, this modulation method drives the filter/load assembly with three PWM

levels.

For reduced power loss in the BTL configuration, the half-bridges can also be driven in a quadrature phase shifted

fashion (i.e. with 90⁰ phase shift). This provides a total of five PWM levels at the load, along with a quadrupling of

MOSFET switching frequency with respect to the differential PWM switching frequency. With this modulation scheme,

the MOSFET switching frequency can therefore be lowered, in order to decrease switching losses. The five-level

modulation scheme produces a common-mode voltage on the load wires, but with less high-frequency content

compared to conventional two-level BD modulation.

The multi-level switching topology of the MA12070P makes filterless operation viable, since the modulation schemes

ensure little or no idle losses in the speaker magnetic system.

For applications with stringent EMC requirements or long speaker cables, the MA12070P can operate with a very small

and inexpensive EMI/EMC output filter. This is enabled by the multiple PWM output levels and the frequency

multiplication seen on the PWM switching nodes. Notably, with the multi-level modulation of the MA12070P, there is

no tradeoff between idle power loss and inductor cost/size, which is due to the absence of inductor ripple current under

idle conditions in all configurations. Due to the high filter cutoff frequency, non-linearities of LC components have less

impact on audio performance than with a conventional amplifier. Therefore, the MA12070P can operate with

inexpensive iron-powder cored inductors and ceramic (X7R) filter capacitors with no significant audio performance

penalty.

Very low power consumption

The MA12070P achieves very low power loss under idle and near-idle operating conditions. This is due to the zero idle

ripple property of the multi-level PWM scheme, in combination with the programmable automatic reduction of

switching frequency at low modulation index levels; resulting in a state-of-the-art power efficiency at low and medium

output power levels.

For high output power levels, power efficiency is determined primarily by the on-resistance (Rds_on) of the output power

MOSFETs. With music and music-like (e.g. pink noise) output signals with high crest factor, the reduced near-idle losses

of the MA12070P contribute to reducing power losses compared to a conventional amplifier with the same Rds_on. In

most applications, this allows the MA12070P to run at high power levels without a heatsink.

Power Mode Management

The MA12070P is equipped with an intelligent power management algorithm which applies automatic power mode

selection during audio playback. In this state, the amplifier will seamlessly transition between three different power

modes depending on the audio level in order to achieve optimal performance in terms of power loss, audio performance

and EMI. Figure 8-1 shows an illustration of the basic power mode management. Alternatively, it is possible to manually

select the desired power mode for the MA12070P via the serial interface.

In both manual and automatic power mode selection, the power mode can be configured and set on-the-fly during

audio playback, with no audible artifacts. This makes it possible to optimize the target application to achieve the best

possible operating performance at all audio power levels.

During automatic power mode selection, the MA12070P can transition between power modes at programmable audio

level thresholds. The thresholds can be set via the serial control interface, by addressing the associated registers.

Datasheet

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Please read the Important Notice and Warnings at the end of this document

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Power mode

change

Power mode

change

1

2

3

Power mode

Audio level

Low to

moderate

Medium

High

Max

Figure 8-1 Illustration of automatic power mode selection ranges.

To allow easy use of the power mode management, “Power Mode Profiles” have been defined. The “Power Mode

Profiles” address the appropriate power modes for a variety of applications.

Power Modes Profiles

The MA12070P provides 5 different power mode profiles for operating the internal power amplifiers. The power mode

profiles give the user freedom to choose optimal settings of the amplifier for the intended application.

The available power modes profiles are referred to as 0, 1, 2, 3 and 4 and can be set by programming the according

register (see). The power mode profile selection affects various parameters such as switching frequency, modulation

scheme and loop-gain, thus providing flexibility in design tradeoffs such as audio performance, power loss and EMI.

Table 8-1 shows the characteristics of the power mode profiles.

Table 8-1 Power Mode Profile characteristics

Property

PM switch seq.

Idle loss

Profile 0

D↔D↔C

Very low

Profile 1

B↔B↔B

Low

Profile 2

B↔B↔A

Low

Profile 3

D↔B↔A

Very low

Profile 4

D↔D↔D

Very low

Full scale

efficiency

Good

Best

Good

Best

Normal

Good/Best

Only DC

Best

Good

THD+N

Common-mode

content, idle

Only DC

DC + Sidebands

around 600kHz,

1.8MHz, 3.0MHz,

etc.

DC + sidebands

around 300kHz,

900kHz, 1.5MHz,

etc.

Common-mode

content, full-scale

audio

Only DC

Differential

content low-to-

mid-power

Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands

around multiples

of 1.2MHz

around multiples

of 1.2MHz

around multiples

of 1.2MHz

around multiples

of 600kHz

around multiples

of 600kHz

Differential

content mid-to-

high power

Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands Audio + sidebands

around multiples

of 600kHz

around multiples

of 1.2MHz

around multiples

of 1.2MHz

around multiples

of 1.2MHz

around multiples

of 600kHz

Filterfree:

optimized audio

performance,

active speaker

applications

Filterfree:

optimized audio

performance,

default

LC filter: high

efficiency, high

audio perform-

ance, good EMI,

low ripple loss

Filterfree:

optimized

efficiency, active

speaker

Filterfree:

optimized

efficiency, default

applications

Application

applications

Note: There is a programmable “Profile 5” which allows the user to set up a custom profile.

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The first row of Table 8-1 shows that each Power Mode Profile follows a certain Power Mode transition sequence. This

means that each Power Mode within every Power Mode Profile will have its specific set of properties (A, B, C or D).

The exact details of each assigned set of properties is reflected in Table 8-2.

Table 8-2 Set of properties assigned to Power Modes in the selectable Power Mode Profiles

Property

A

B

C

D

FET switching

frequency, f_FET

600kHz

300kHz

150kHz

Modulation scheme

3-level

5-level

3-level

5-level

Switching frequency

seen at load, f_SW

1.2MHz (2 x f_FET

)

1.2MHz (4 x f_FET

)

600kHz (2 x f_FET

)

600kHz (4 x f_FET)

Idle loss

Reduced

Low

Very low

Full scale efficiency

Open-loop gain

THD+N

Normal

High

Good

High

Good

Low

Best

Low

Best

Good

Only DC

Common-mode

content, idle

Only DC

Common-mode

content, full-scale

audio

DC + sidebands around

600kHz, 1.8MHz,

3.0MHz, etc.

DC + sidebands around

300kHz, 900kHz,

1.5MHz, etc.

Only DC

Audio + sidebands

around multiples of

1.2MHz

Audio + sidebands

around multiples of

1.2MHz

Audio + sidebands

around multiples of

600kHz

Audio + sidebands

around multiples of

600kHz

Differential content

Next to the pre-defined Power Mode Profiles it is also possible to define a custom profile which will be available under

Power Mode Profile 5. This profile can be configured using the “custom power mode profile” register (address 30). See

“Register Map” section for more details.

The MA12070P employs feedback of the output PWM signals in order to compensate for noise and other non-idealities

in the power processing path. A fourth-order analog feedback loop is used, which typically provides a loop gain of 60dB

to suppress errors in the audio band. For the typical high efficiency application this results in low THD (Total Harmonic

Distortion) at all audio frequencies, as well as excellent immunity (in excess of 75dB) to power supply borne

interferences.

Maximum achievable loop-gain is typically set by the PWM frequency stability criteria. Inherent frequency multiplication

of the multilevel topology therefore allows for a much more aggressive loop-filter (and therefore better THD and noise

properties) because of a higher effective PWM switching frequency seen at the output. See “Profile 0 and Profile 2” in

Table 8-1 for high-fidelity Power Mode Profiles.

For the lowest switching frequencies, the proprietary loop filter architecture seamlessly reduces feedback bandwidth

to ensure loop stability. In most applications (e.g. filterless applications), no further special attention is required to

ensure loop stability. In applications with very stringent EMI requirements, an LC filter can be used. In these cases

attention to loop stability is required since an un-damped LC filter effectively represents a short-circuit to ground at the

resonance frequency. In extreme cases, this can cause instability of the analog feedback loops. In order to avoid this, an

LC filter should use an inductor with more than 10mΩ DC resistance, and a series R-C circuit should be used to limit the

Q of the LC circuit to around 5.

Power supplies

The MA12070P generates internal supply voltages and uses external capacitors for this purpose and for decoupling.

Datasheet

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Gate driver supplies

The MA12070P utilizes a floating supply voltage for the gate driver circuitry generated internally by a charge pump. The

gate driver power supply voltage is approximately 6V to 9V higher than PVDD. For PVDD voltages of 24V and higher it is

recommended to add decoupling capacitors (1uF & 100nF) from CGD0N & CGD1N to GND for improved power supply

robustness. Table 8-3 shows the required external charge pump and decoupling capacitors.

Table 8-3 Gate driver supply capacitors

Name

C_GD0

Purpose

Connection

CGD0P, CGD0N

CGD1P, CGD1N

CFGDP, CFGDN

CGD0N, GND

CGD1N, GND

Type

Value

1uF

Decoupling of gate driver supply voltage 0

Decoupling of gate driver supply voltage 1

Charge pump flying capacitor

16V, high capacity, low precision

50V, high capacity, low precision

C_GD1

1uF

C_FGD

100nF

C_GD0N

C_GD1N

Decoupling of gate driver supply voltage 0

Decoupling of gate driver supply voltage 1

1uF, 100nF

Digital core supply

The digital control unit in the MA12070P uses a supply voltage generated internally by a charge pump and a voltage

regulator for highest efficiency. Table 8-4 lists the external capacitors required and describes their function and

connection.

Table 8-4 Digital supply capacitors

Name

C_DC

Purpose

Connection

CDC, GND

Type

Value

1uF

Charge pump output voltage decoupling to GND

>=6.3V, high capacity, low precision

C_FDC

Charge pump flying capacitor

CFDCP, CFDCN >=6.3V, high capacity, low precision

VGDC, DVDD >=6.3V, high capacity, low precision

1uF

C_GDC

Decoupling of digital core virtual ground voltage

on the VGDC pin. The voltage on the VGDC pin is

approximately 1.8V below DVDD, i.e. about 3.2V

1uF

Flying capacitors

The MA12070P power stage uses flying capacitors to generate a ½PVDD supply voltage to enable multi-level operation.

Each output switch node OUTXX has a corresponding flying capacitor, with a positive and a negative terminal, CFXXP

and CFXXN.

The two flying capacitor terminals are to be considered high power switching nodes carrying voltages and currents

similar to that on the OUTXX nodes. Care must be taken in the PCB design to reduce both the inductance and the

resistance of these nodes. Table 8-5 lists the flying capacitors, incl. connection, type and value.

Table 8-5 Flying capacitors

Name

C_F0A

Purpose

Connection

CF0AP, CF0AN

CF0BP, CF0BN

CF1AP, CF1AN

CF1BP, CF1BN

Type

Value

10uF

Half-bridge 0A flying capacitor

Half-bridge 0B flying capacitor

Half-bridge 1A flying capacitor

Half-bridge 1B flying capacitor

>=25V, high capacity, low precision

C_F0B

C_F1A

C_F1B

Care must be taken when choosing flying capacitors in applications where maximum output power is needed. The

effective capacitance of poor ceramic capacitors can be greatly reduced when a DC bias voltage is applied. A

recommended part is the GRM21BZ71E106KE15L capacitor from Murata. Other parts may also be used as long as the

effective capacitance is minimum 4.0 µF at 0.5*PVDD voltage.

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Protection

The MA12070P integrates a range of protection features to protect the device and attached speakers from damage.

Protection features include:

•

Current protection on OUTXX nodes during operation.

On-chip temperature sensor for protection against device over-heating.

Undervoltage supply monitors on AVDD, DVDD, VGDC and PVDD.

DC protection, preventing DC to be present on the amplifier outputs.

Over-current protection on OUTXX nodes

During switching operation the output stage monitors the forward current flow in all output switches that are turned

on. This is done to limit the maximum power dissipated in the switches and prevent damage to the device and the

speaker load. The current in the output stage can exceed unwanted levels if:

•

The speaker load impedance drops to a low value while the device is powered from a high PVDD supply.

A failure occurs on the speaker terminals causing a low impedance short.

The speaker is damaged and thereby exhibiting a low impedance.

Over-current protection and short-circuit protection use a latching mechanism. If an over current or a short-circuit

condition occurs, it will shut down the power stage and report the error on the /ERROR pin. By default the power stage

will restart and remove the latch – after 1-2 sec. If the over current is still present it will cycle through the described

process again until the over current is removed. Current limiting will not occur for currents below the OCP_THRlevel, see

Table 7-1.

Current protection against speaker terminal shorts requires an equivalent load inductance L_Leqon each of the output

OUTXX pins (see Table 6-1). Load inductance from loudspeaker cables and, if used, ferrite beads (EMC filter) will typically

be sufficient.

Temperature protection

An on-chip temperature sensor effectively safeguards the device against a thermally induced failure due to overloading

and/or insufficient cooling.

A high junction temperature initially causes a temperature warning, TW. This can be detected by reading the error

register (address 124, bit 4) via I2C. If the temperature continues to rise the device will reach the temperature error (TE)

level and set the TE bit in the error register (address 124, bit 5). This will cause the device to stop all switching activity.

The device will restart after sufficient cooling down of the system. Both TW and TE will report the error on the /ERROR

pin.

Table 8-6 High-Temperature Warning and Error Signaling Levels

Symbol

TE_THR,SET

TE_THR,CLR

TW_THR,SET

TW_THR,CLR

Parameter

Test Conditions

Temperature rising

Temperature falling

Temperature rising

Temperature falling

Typical Value

Unit

°C

High-Temperature Error (TE) Set Threshold

High-Temperature Error (TE) Clear Threshold

High-Temperature Warning (TW) Set Threshold

High-Temperature Warning (TW) Clear Threshold

150

135

125

105

°C

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Power supply monitors

The MA12070P features integrated PVDD, DVDD and AVDD under-voltage lockout.

Table 8-7 shows typical limits for the supply monitors.

Table 8-7 Under-voltage lockout levels

Parameter

DVDD under-voltage error threshold

Test Conditions

DVDD Rising

Typical Value

Unit

V

UVP_DVDD

UVP_AVDD

UVP_PVDD

4.2

DVDD Falling

4.0

V

AVDD under-voltage error threshold

PVDD under-voltage error threshold

AVDD Rising

AVDD Falling

PVDD Rising

PVDD Falling

4.2

4.0

4.3

4.1

V

DC protection

The MA12070P incorporates a circuit, detecting whether a DC is present on the amplifier output terminals driving the

loudspeaker. In case of an unexpected DC being present on any of the amplifier outputs, the power stage will be shut

down to protect the loudspeaker from harmful DC content. Furthermore, a failure is reported on the /ERROR pin and in

the error register readable by the device serial interface. The power stage can be restarted by resetting the device by

cycling the /ENABLE pin or toggle the eh_clear bit (bit 2, address 45) to clear the error register. DC protection is default

on. It can be disabled by clearing bit 2 of Eh_dcShdn (address 0x26).

For the DC protection circuit to trigger, the DC value of an output pin must be staying above 0.63*PVDD or below

0.37*PVDD for more than 700ms.

Digital serial audio input

The MA12070P provides a digital serial audio interface for providing up to four input PCM audio signals to the amplifier.

The digital serial audio input port on the MA12070P consist of the pins SCK (serial clock), WS (word select), SD0 (serial

data 0 – input channels 0L and 0R), and SD1 (serial data 1 – input channels 1L and 1R). All pins are inputs, i.e. the serial

input port is slave. The format of the digital serial audio inputs can be configured using the serial control interface. The

timing diagram for left justified mode (default) are illustrated in Figure 8-2 and I2S mode in Figure 8-3. In the following

the various settings for the digital serial audio input interface are described.

Table 8-8 Parameters for the digital serial audio input interface

Address(bits)

Register name

Description

0x35(2-0)

i2s_format

PCM word format:

000: i2s

001: left justified (default)

100: right justified 16bits

101: right justified 18bits

110: right justified 20bits

111: right justified 24bits

Clocking edge of the serial clock signal (SCK):

0x36(0)

i2s_sck_pol

0: Serial data (SDX) and word select (WS) are changing at rising edge of the serial

clock signal (SCK). The MA12070P will capture data at the falling edge of the

serial clock signal SCK.

1: Serial data (SDX) and word select (WS) are changing at falling edge of the

serial clock signal (SCK). The MA12070P will capture data at the rising edge of

the serial clock signal SCK. (default)

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0x36(4-3)

i2s_framesize

Number of data bits per frame:

00: 64 serial clock (SCK) cycles are present in each period of the word select

signal (WS). (default)

01: 48 serial clock (SCK) cycles are present in each period of the word select

signal (WS).

10: 32 serial clock (SCK) cycles are present in each period of the word select

signal (WS).

11: reserved

0x36(1)

i2s_ws_pol

Temporal pairing of the two PCM data words in the serial data signals:

0: First word of a simultaneously sampled PCM data pair is transmitted while

word select (WS) is low. (default)

1: First word of a simultaneously sampled PCM data pair is transmitted while

word select (WS) is high.

0x36(2)

0x36(5)

i2s_order

Bit order for PCM data words:

0: Most significant bit of the PCM data word is transmitted first. (default)

1: Least significant bit of the PCM data word is transmitted first.

Left/right order of the two temporally paired PCM words:

i2s_rightfirst

0: Left PCM data word (of a simultaneously sampled PCM data pair) is send first.

(default)

1: Right PCM data word (of a simultaneously sampled PCM data pair) is send

first.

1/FS

WS

SCK

Left Channel 32 bits

Right Channel 32 bits

N

N-1

1

0

N

N-1

1

0

N

SD0/SD1

MSB

LSB

MSB

LSB

Figure 8-2 Timing diagram of left justified mode (default).

1/FS

WS

SCK

1Bit

Left Channel 32 bits

Right Channel 32 bits

N

N-1

1

0

N

N-1

1

0

SD0/SD1

MSB

LSB

MSB

LSB

Figure 8-3 Timing diagram of I2S mode with 2x32 bit.

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Volume and limiter processor (VLP)

The MA12070P incorporates a volume and limiter processor (VLP). The VLP is a dedicated digital signal processor

capable of processing up to four audio channels. Customized signal processing is used to ensure preservation of the

audio quality in all stages of the VLP.

Figure 8-4 shows a functional block diagram of the VLP. The VLP is capable of applying a high precision volume control

on the incoming audio signals. After volume scaling, the signals can be passed through high precision limiters to protect

the loudspeakers from overload or to avoid undesired clipping occurring due to bad signal or gain scaling (volume

overdrive). The VLP can also be programmed to reduce the signal level in case of a temperature warning event to

prevent a system shutdown caused by overheating.

Figure 8-4. Functional block diagram of the volume and limiter processor (VLP)

Volume control

The volume controls in the VLP are organized as a master volume, which applies gain on all channels and four channel

volumes, applying gain on each of the individual channels. The resulting gain for a channel will consequently be a

product of the master volume and the channel gain. To avoid undesired audible artifacts when changing the volume

settings, smoothing is performed on the resulting gain before applying it to the audio signal.

The master volume and the channel volume settings can be controlled via the serial control interface. Each volume

setting is represented by 10 bits. The 10 bits are organized as an 8-bit number giving the integer part of the gain in dB

(the digits before the decimal point) - and a 2-bit number giving the fractional part of the gain in dB (the digits after the

decimal point). The granularity of volume settings is 0.25dB. The mapping from the serial control interface register to

the gain is shown in Table 8-9.

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Table 8-9 VLP Mapping from register values to gain and level

Integer dB

register setting

Fractional dB

register setting

VLP Gain/Level dB

dec Hex

dec hex

0

(0x00)

…

0

1

…

3

0

1

2

3

0

1

2

3

0

…

3

0

…

2

3

(0x0)

(0x1)

…

24.00

23.75

…

22 (0x16)

23 (0x17)

24 (0x18)

25 (0x19)

(0x3)

(0x0)

(0x1)

(0x2)

(0x3)

(0x0)

(0x1)

(0x2)

(0x3)

(0x0)

…

1.25

1.00

0.75

0.50

0.25

0.00

-0.25

-0.50

-0.75

-1.00

…

167 (0xA7)

168 (0xA8)

(0x3)

(0x0)

…

-143.75

-144.00

…

255 (0xFF)

(0x2)

(0x3)

-144.00

Limiter

The limiter block in the VLP is capable of ensuring that the audio output level from the MA12070P is kept below a

programmable threshold level, regardless of the volume gain settings and signal level. This way, the limiter can protect

the loudspeakers against harmful signal levels and prevent severe degradation of audio quality, due to clipping caused

by volume over-drive of the audio system.

The input to output level characteristic for the limiter is illustrated on Figure 8-5. At input audio levels below the

threshold, the gain through the limiter is unity and consequently the limiter passes the signal unaffected. This is seen as

a 1:1 slope on the input to output level characteristic plot. If the input signal level increases above the threshold level,

the limiter reduces the gain correspondingly in order to reduce the output signal level to the threshold level. This way

the output signal level will generally not exceed the threshold.

The slew-rate of the limiter is finite and the output signal can therefore occasionally exceed the set threshold. When

the limiter reduces the gain (caused by the input signal level exceeding the threshold) the speed of gain reduction is

limited by an attack-time constant. Similarly, when the limiter restores the gain to unity after being active the speed of

gain increase is limited by a release-time constant. The attack-time constant and the release-time constant can be

controlled in three steps (“slow”, ”normal” and “fast”) via the serial control interface. An example of the attack and

release behavior for the limiter is shown in Figure 8-6.

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Limiter bypassed

Threshold

Limiter active

Inputlevel (dBFS)

Figure 8-5 Input to Output level characteristic for the Limiter

Threshold

Input level

Output level

Time

Unity gain

Limiter gain

Time

Attack Phase

Release Phase

Figure 8-6 Example of limiter attack - and release behavior

VLP parameter interface

The parameters for the volume controls and limiters are accessible via the serial control interface. In Table 8-10 is shown

a list of parameters in the VLP.

Table 8-10 Parameters and status signals for the VLP accessible via the serial control interface.

Address

Register name

Description

(bits)

0x35 (5-4)

0x35 (7-6)

0x35 (3)

audio_proc_release

audio_proc_attack

audio_proc_enable

Controls the limiter release time. 00: slow, 01: normal, 10: fast

Controls the limiter attack time. 00: slow, 01: normal, 10: fast

Controls the processing bypass mux

When high use the VLP

When low: bypass the VLP

0x36 (6)

0x36 (7)

0x40

audio_proc_ limiterEnable Controls the Limiter bypass mux

When high: use the limiter

When low: bypass the limiter

audio_proc_mute

vol_db_master

Controls the mute mux

When high: mute the audio

When low: play as normal

Controls the integer dB gain for the master volume¹

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0x41 (1-0)

0x42

vol_lsb_master

vol_db_ch0

Controls the fractional dB gain for the master volume (quarter dB’s) ¹

Controls the integer dB gain for channel 0L¹

0x43

vol_db_ch1

Controls the integer dB gain for channel 0R¹

0x44

vol_db_ch2

Controls the integer dB gain for channel 1L¹

0x45

vol_db_ch3

Controls the integer dB gain for channel 1R¹

0x46 (1-0)

0x46 (3-2)

0x46 (5-4)

0x46 (7-6)

0x47

vol_lsb_ch0

vol_lsb_ch1

vol_lsb_ch2

vol_lsb_ch3

thr_db_ch0

Controls the fractional dB gain for channel 0R (quarter dBs) ¹

Controls the fractional dB gain for channel 0L (quarter dBs) ¹

Controls the fractional dB gain for channel 1R (quarter dBs) ¹

Controls the fractional dB gain for channel 1L (quarter dBs) ¹

Controls the integer dBFS limiter threshold level for channel 0L¹

Controls the integer dBFS limiter threshold level for channel 0R¹

Controls the integer dBFS limiter threshold level for channel 1L¹

Controls the integer dBFS limiter threshold level for channel 1R¹

Controls the fractional dBFS limiter threshold level for channel 0L(quarter dBFS)¹

Controls the fractional dBFS limiter threshold level for channel 0R(quarter dBFS)¹

Controls the fractional dBFS limiter threshold level for channel 1L(quarter dBFS)¹

Controls the fractional dBFS limiter threshold level for channel 1R(quarter dBFS)¹

Indicates if limiters are active

0x48

thr_db_ch1

0x49

thr_db_ch2

0x4A

thr_db_ch3

0x4B (1-0)

0x4B (3-2)

0x4B (5-4)

0x4B (7-6)

0x7E (7-4)

thr_lsb_ch0

thr_lsb_ch1

thr_lsb_ch2

thr_lsb_ch3

audio_proc_limiter_mon

Bit 4 high: limiter is active on channel 0L

Bit 5 high: limiter is active on channel 0R

Bit 6 high: limiter is active on channel 1L

Bit 7 high: limiter is active on channel 1R

0x7E (3-0)

audio_proc_clip_mon

Indicates if clipping occurs on the VLP output signals

Bit 0 high: clipping present on channel 0L

Bit 1 high: clipping present on channel 0R

Bit 2 high: clipping present on channel 1L

Bit 3 high: clipping present on channel 1R

¹See Table 8-9 for mapping.

Clock system

The MA12070P incorporates a clock system consisting of an input clock divider, a PLL, a low-jitter low-TC oscillator

(2.8224 MHz), and control logic. At the CLK input pin the MA12070P requires a clock signal that is in phase-lock with the

incoming digital serial audio samples. This CLK input signal provides the reference for the internal PLL through the input

clock divider circuit. The CLK frequency is auto-detected by the MA12070P, and when a valid frequency is detected, the

corresponding input divider ratio is selected to internally generate the correct reference clock to the PLL. The PLL divider

ratio is also selected as a function of the CLK base frequency (2.8224 or 3.072 MHz).

The clock for the internal DAC’s is sourced from the PLL, or at some CLK rates, a divided version of the CLK input. Valid

combinations of audio sample rate (fs) and CLK frequency are listed in Table 8-11 together with maximum number of

supported VLP channels.

Table 8-11 Valid combinations of audio sample rate and CLK frequency

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Also maximum number of supported VLP channels are shown

Audio sample rate (fs) CLK frequency

No. VLP channels

44.1kHz

64 x fs = 2822.4kHz

128 x fs = 5644.8kHz

256 x fs = 11289.6kHz

512 x fs = 22579.2kHz

64 x fs = 3072kHz

4

48kHz

4

128 x fs = 6144kHz

256 x fs = 12288kHz

512 x fs = 24576kHz

32 x fs = 2822.4kHz

64 x fs = 5644.8kHz

128 x fs = 11289.6kHz

256 x fs = 22579.2kHz

32 x fs = 3072kHz

4

88.2kHz

96kHz

2

64 x fs = 6144kHz

2

128 x fs = 12288kHz

256 x fs = 24576kHz

16 x fs = 2822.4kHz

32 x fs = 5644.8kHz

64 x fs = 11289.6kHz

128 x fs = 22579.2kHz

16 x fs = 3072kHz

2

176.4kHz

192kHz

None

32 x fs = 6144kHz

64 x fs = 12288kHz

128 x fs = 24576kHz

MCU/Serial control interface

The I2C serial control interface of the MA12070P allows an I2C master to read and/or modify a wide range of device

parameters.

The I2C interface consists of four physical pins, SDA, SCL, AD0 and AD1. I2C decoder logic handles transaction protocol

and read/write access to the device register bank. SDA and SCL are standard bidirectional I2C slave pins for data and

clock, respectively. Both SDA and SCL must be pulled-up to a digital I/O (3.3V - 5V) with a 5k resistor on each pin and

operated in standard I2C mode up to 100 kbps transmission rate. Pins AD0 and AD1 are used to configure the 7-bit I2C

address of the device. The I2C address is decoded according to Table 8-12.

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Table 8-12 I2C address decoding

I2C device address

AD1 pin

AD0 pin

7-bit I2C address

0b0100000

0x20

0x21

0x22

0x23

0

1

0

1

0

1

0b0100001

0b0100010

0b0100011

The I2C interface enables read/write operations to the device register bank. The register bank is organized as a 128

entry, byte wide memory, holding device configuration and status registers. The address space from 0 to 80 holds

read/write registers and the address space from 96 to 127 are read only. The complete address map and description of

each register is presented in “Register Map” section.. Figure 8-7 shows the block schematic of the I2C interface between:

I2C bus and MA12070P (serial interface controller and the register bank).

Digital I/O

DVDD

I2C bus

MA12040

Read/Write

Read only

SDA

SCL

AD0

AD1

Serial interface

controller

Register bank

Figure 8-7. I2C bus interface and register bank

I2C write operation

Each I2C transaction is initiated from a master by sending an I2C start condition followed by the 7-bit I2C device address

and cleared read/write bit. The device address and read/write bit is signaled on the SDA bus by pulling the bus to ground

indicating a ‘0’ or releasing the bus to indicate a ‘1’. The I2C SDA input is sampled by the device on the rising edge of the

SCL bus.

If the transmitted I2C address matches the configured address of the device, the device will acknowledge the request

by pulling the SDA bus to ground. The master samples the acknowledged bit from the device on the next rising edge of

SCL. The I2C initialization as described is shown in the waveform in Figure 8-8.

Figure 8-8. I2C init addressing sequence.

To complete the device register write operation, the master must continue transmitting the address and at least one

data byte. The device continues to acknowledge each byte received on the 9^thSCL rising edge. Each additional data

written to the device is written to the next address in the register bank.

The write transaction is terminated when the master sends a stop signal to the device. The stop signal consists of a rising

edge on SDA during SCL kept high. Figure 8-9 shows a single write operation.

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Figure 8-9 I2C write operation.

I2C read operation

To read data from the device register bank, the read transaction is started by sending a write command to the I2C

address with the R/W bit cleared, followed by the device address to read from. See Figure 8-10.

Figure 8-10 I2C read transaction, register bank to be read from is written to the device.

The device will acknowledge the two bytes. Then data can be fetched from the device by sending a repeated start,

followed by an I2C read command consisting of a byte with the device I2C address and the R/W bit set.

The device will acknowledge the read request and start to drive the SDA bus with the bits from the requested register

bank address. See Figure 8-11.

Figure 8-11 I2C read transaction last part.

The read transaction continues until the master does not acknowledge the 9^thbit of the data read byte transaction and

sends a stop signal. The stop condition is defined as a rising edge of SDA while SCL is high. Timing requirements are

reflected in Table 8-13.

Table 8-13 I2C timing requirements

Parameter

Min

Typ

Max Unit

Clock frequency¹

SDA and SCL rise time

SDA and SCL fall time

SCL clock high

0

100

400

kHz

1

µs

1

µs

1

µs

SCL clock low

µs

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Data, setup

300

10

1

ns

µs

Data, hold

Min stop to start condition

NOTE¹: Pull up resistance is equal to 2.2kΩ for 400kHz.

/CLIP pin and soft-clipping

The /CLIP pin changes from a HIGH state to LOW state when audio output is close to clipping. A system microcontroller

can at this instance decrease volume level or, if possible, increase power stage voltage in order to avoid clipping. The

associated modulation index for both channel 0 and channel 1 can be read out by reading address 98 and address 102

respectively. Note that /CLIP pin is an open-drain output which means that it should be pulled-up through a pull-up

resistor to the digital I/O DVDD of the system.

To minimize possible audible artifacts from sticky clipping or ringing around the clipping region, it is possible to enable

a soft-clipping scheme. This clipping scheme prevents the amplifier to sticky clip and minimizes ringing which

subsequently minimizes possible audible artifacts apart from normal clipping audibility. The soft-clipping scheme can

be enabled by setting bit 7 of address 10.

/ERROR pin and error handling

The /ERROR pin changes from a HIGH state to a LOW state when one of the associated error sources is triggered. A

system microcontroller can at this instance read out the error registers (address 45 and 109). According to the type of

error or warning the right measures can be taken. The errors will be shown in the error register (address 124) which

shows the live status of the error sources. Another register error_acc (address 109) will contain all the errors

accumulated over time. The error_acc register can be cleared by toggling the eh_clear bit (bit 2, address 45).

Table 8-14 shows the content of the error vector which is mapped to both the error register and the accumulated error

register. A more detailed explanation can be found in “Register Map” section.

Table 8-14 Error vector

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

dc_prot

pps

ote

otw

uvp

pll

ocp

fcov

Note that the /ERROR pin has an open-drain output and should be pulled up to the interface I/O rail.

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9 Application Information

Input/Output Configurations

The MA12070P is highly flexible regarding configuration of the four power amplifier channels. MA12070P can be set to

four different output configurations. By setting the configuration pins MSEL0 and MSEL1 according to Table 9-1, the

device is configured to one of the four different configurations. Each configuration is individually described in the

following sections.

Table 9-1 Signal configuration

MSEL0 pin

MSEL1 pin

Configuration

0

1

0

1

0

1

1 channel parallel bridge tied load (PBTL)

2 channels single ended load (SE) and 1 channel bridge tied load (BTL)

2 channels bridge tied load (BTL)

4 channels single ended load (SE)

Bridge Tied Load (BTL) Configuration

In BTL configuration, two input- and output terminals are used per channel as shown in Figure 9-1. This way two

power stage half-bridges are used to form one differential output configuration. This configuration will enable the full

potential of multi-level technology where the speaker load will experience up to 5 levels. This enables low near-idle

power consumption and beneficial noise properties.

Audio source

OUT0A

OUT0B

OUT1A

OUT1B

Data pair 0

(0L,0R)

SD0

SD1

Serial clock

(master)

Word select

SCK

(slave)

WS

Master clock

CLK

EMC filter

depending on

application

5V

Figure 9-1 Bridge tied load (BTL) configuration, with symmetrical audio sources.

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Single Ended (SE) Configuration

In single ended (SE) configuration, the MA12070P is able to drive one loudspeaker per output power stage, i.e. up to

four loudspeakers. The output is biased to half the power supply voltage, ½ PVDD. One of the solutions to drive a speaker

in this configuration is to use AC-coupling capacitors (C_out)in series with the load, as shown in Figure 9-2. The value of

the capacitors depends on the load resistance and the desired audio bandwidth.

Table 9-2 shows examples of AC-coupling capacitor values. The DC voltage across the capacitors at the output is

approximately ½PVDD. However, significant AC-voltage swing might occur at low frequencies, which must be accounted

for in the voltage rating of the capacitors.

Audio source

C_out

+

OUT0A

OUT0B

OUT1A

Data pair 0

(0L,0R)

SD0

SD1

Data pair 1

(1L,1R)

C_out

+

Serial clock

(master)

Word select

SCK

(slave)

WS

Master clock

CLK

OUT1B

5V

EMC filter

depending on

application

5V

Figure 9-2 Four channel, single ended (SE) configuration.

Table 9-2 Typical values for the output AC-coupling capacitor, C_out

Load Resistance

Output AC-coupling

capacitor, C_out

220µF

-3dB frequency

8Ω

4Ω

90Hz

20Hz

24Hz

1000µF

2200µF

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Combined SE and BTL Configuration

A combination of SE and BTL configuration can be used as shown in Figure 9-3. In this configuration two half-bridges are

combined to run in BTL configuration and the two remaining half-bridges are configured to run in SE configuration.

Audio source

OUT0A

OUT0B

OUT1A

Data pair 0

(0L,dummy)

SD0

SD1

Data pair 1

(1L,1R)

Serial clock

(master)

Word select

SCK

(slave)

WS

C_out

+

Master clock

CLK

C_out

OUT1B

5V

EMC filter

depending on

application

Figure 9-3 Combined Bridge tied load (BTL) and single ended (SE) configuration, with SE audio sources

Parallel Bridge Tied Load (PBTL)

For providing additional power the MA12070P can be configured for mono operation using a parallel BTL mode (PBTL),

as shown in Figure 9-4. In this fashion the two BTL output stages are combined to be able to deliver twice the current.

This makes high output power sub-woofer application possible.

Audio source

OUT0A

OUT0B

OUT1A

OUT1B

Data pair 0

(0L,dummy)

SD0

SD1

0L

Serial clock

(master)

Word select

SCK

(slave)

WS

EMC filter

depending on

application

Master clock

CLK

Figure 9-4 Parallel Bridge Tied Load (PBTL) configuration

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EMC output filter Considerations

The proprietary 5-level modulation significantly reduces EMC emissions, and the amplifiers can pass the Radiated

Emission test with speaker cables lengths up to 80 cm with just a small ferrite filter. For cables longer than 80 cm it is

recommended to use a LC-filter.

For more information regarding filter type, components and measurements, see the document “Applications note –

EMC Output Filter Recommendations” at the Infineon homepage.

Audio Performance Measurements

In a typical audio application the outputs of the MA12070P will be connected directly to the speaker loads. However,

for audio performance evaluation it can be beneficial to configure the circuit board with an LC filter. This is due to the

fact that many audio analyzers do not handle PWM signals at their inputs well.

When using an audio analyzer configured with an external and/or internal measurement filter the use of an LC filter is

not necessary. However, be sure to verify the audio analyzer’s input limits before connecting it to a filterless amplifier

output.

When using an LC filter, the design depends on the specific load. L and C values should therefore be optimized for this.

Thermal Characteristics and Test Signals

Performing audio measurements by use of an audio analyzer is typically very helpful during the evaluation of an

amplifier. However, using an audio analyzer can be misleading when evaluating thermal performance.

Audio analyzers typically generate full tone, continuous sine wave signals as the input signal for the amplifier. While this

is required to perform many audio measurements, it is also the worst-case thermal scenario for the device. Using full-

scale continuous sine waves for thermal evaluation or testing will lead to an overly conservative and more costly thermal

design which will be unnecessary in almost all real audio applications.

Actual audio content, such as music, has much lower RMS values compared to its maximum peak output power than a

full-scale continuous sine wave. This results in significantly less heat dissipation from the device when amplifying actual

audio. For thermal evaluation it is therefore recommended to use actual music signals during tests. Alternatively, a pink

noise signal can be used to emulate a music signal.

It is not uncommon for an amplifier solution to have limited thermal performance, potentially resulting in thermal

protection shutdown, when amplifying full-scale continuous sine wave signals.

Start-up procedure

It is recommended to follow the start-up procedure as described below:

1) Make sure the all hardware pins are configured correctly: e.g. BTL, Slave Clock mode.

2) Keep the device in disable and mute: /ENABLE = 1; /MUTE = 0.

3) Bring up 5V VDD supply and PVDD supply (it does not matter if VDD or PVDD comes up first, provided that

the device is held in disable).

4) Wait for VDD and PVDD to be stable.

5) CLK must be present before enabling the amplifier.

6) Enable device: /ENABLE = 0.

7) Program applicable initialization to registers.

8) Unmute device: /MUTE = 1.

9) The device is now in normal operation state.

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Shut-down / power-down procedure

It is recommended to follow the start-up procedure as described below:

1) The device is in normal operation state.

2) Mute device: /MUTE = 0.

3) Disable device: /ENABLE = 1.

4) The device is now power-down state.

5) Bring down 5V VDD supply and PVDD supply.

6) The device is now in shut-down state.

Recommended PCB Design for MA12070P (EPAD-down package)

The QFN package with exposed thermal pad at the bottom side is thermally sufficient for most applications. However,

in order to remove heat from the package care should be taken in designing the PCB.

The PCB footprint for the device should include a thermal relief pad underneath the device with a size of 6 x 6 mm. This

thermal relief pad must be centered so the device can be soldered easily. It is recommended to use a PCB design with

two or more layers of copper for good thermal performance. Using multiple layers enables a design with a large area of

copper connected to the EPAD.

To achieve best thermal performance it is also important to design the surrounding connections in such a way that

avoids cutting up the copper area into many sections.

Figure 9-5 shows a PCB design using 26 via connections directly underneath the chip between the top and bottom layers.

These should be placed on a grid each with a 0.65 mm plated through hole. These connections ensure good thermal

transfer from the top side EPAD to a large section of ground connected copper area on the bottom side of the PCB.

Figure 9-5 Example of 2-layer PCB layout, top and bottom layers

It is recommended to use a PCB made from glass/epoxy laminate (e.g. FR-4) material. This type of material works well

with PCB designs that require thermal relief as it can endure high temperatures for a long duration of time.

PCB copper thickness is recommended to be a minimum of 35μ (1 oz) and the PCB must be made to the IPC 6012C, Class

2 standard.

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10 Typical Characteristics (PVDD = +26V, Load = 4Ω + 22µH)

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

1

0,1

0,01

0,001

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

1

10

100

0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 10-1 THD+N vs Output Power for PMP0

Figure 10-2 THD+N vs Output Power for PMP1

100

10

100

10

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

1

0,1

0,01

0,001

0,01

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

Output Power (W)

Figure 10-4 THD+N vs Output Power for PMP4

1

10

100

0,001

0,01

0,1

Output Power (W)

Figure 10-3 THD+N vs Output Power for PMP2

1

10

100

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BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

1W

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 10-5 THD+N vs Frequency for PMP0

Figure 10-6 THD+N vs Frequency for PMP1

100

10

100

10

1W

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

Frequency (Hz)

Figure 10-7 THD+N vs Frequency for PMP2

2000

20000

Frequency (Hz)

Figure 10-8 THD+N vs Frequency for PMP4

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BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

10 20 30 40 50 60 70 80 90

0

10 20 30 40 50 60 70 80 90

Output Power (W)

Figure 10-9 PMP0 Efficiency (VDD+PVDD) vs Output Power

100

Figure 10-10 PMP1 Efficiency (VDD+PVDD) vs Output Power

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

10 20 30 40 50 60 70 80 90

0

10 20 30 40 50 60 70 80 90

Output Power (W)

Figure 10-11 PMP2 Efficiency (VDD+PVDD) vs Output Power

Figure 10-12 PMP4 Efficiency (VDD+PVDD) vs Output Power

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BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

1

100

10

1

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 10-13 Input Power vs Output Power for PMP0

Figure 10-14 Input Power vs Output Power for PMP1

100

10

1

100

10

1

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 10-15 Input Power vs Output Power for PMP2

Figure 10-16 Input Power vs Output Power for PMP4

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BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

10

1

10

1

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

0,1

0,01

0,001

0,01

0,001

PMP0

PMP1

PMP2

PMP4

0,0001 0,001 0,01

Output Power (W)

Figure 10-17 PVDD Current vs Output Power for PMP0 & PMP1 Figure 10-18 PVDD Current vs Output Power for PMP2 & PMP4

0,1

1

10

100 1000

0,0001 0,001 0,01

0,1

1

10

100 1000

Output Power (W)

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

Load = 4Ω + 22µH

PMP2

PMP4

PMP0

PMP1

4

6

8

10 12 14 16 18 20 22 24 26

4

6

8

10 12 14 16 18 20 22 24 26

PVDD (V)

Figure 10-19 PVDD Idle Current vs PVDD for PMP0 & PMP1

Figure 10-20 PVDD Idle Current vs PVDD for PMP2 & PMP4

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BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

Load = 4Ω + 22µH

1% THD+N

10% THD+N

4

6

8

10 12 14 16 18 20 22 24 26

4

6

8

10 12 14 16 18 20 22 24 26

PVDD (V)

Figure 10-21 Output Power vs PVDD for PMP0

Figure 10-22 Output Power vs PVDD for PMP1

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

Load = 4Ω + 22µH

1% THD+N

10% THD+N

4

6

8

10 12 14 16 18 20 22 24 26

4

6

8

10 12 14 16 18 20 22 24 26

PVDD (V)

Figure 10-23 Output Power vs PVDD for PMP2

Figure 10-24 Output Power vs PVDD for PMP4

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BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 10-25 Gain vs Frequency for PMP0

Figure 10-26 Gain vs Frequency for PMP1

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 10-27 Gain vs Frequency for PMP2

Figure 10-28 Gain vs Frequency for PMP4

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BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

Ch1 to Ch0

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 10-29 Crosstalk vs Frequency for PMP0

Figure 10-30 Crosstalk vs Frequency for PMP1

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

PVDD = +26V

Load = 4Ω + 22µH

PVDD = +26V

Load = 4Ω + 22µH

Ch1 to Ch0

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 10-31 Crosstalk vs Frequency for PMP2

Frequency (Hz)

Figure 10-32 Crosstalk vs Frequency for PMP4

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11 Typical Characteristics (PVDD = +26V, Load = 8Ω + 22µH)

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

1

0,1

0,01

0,001

0,01

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

1

10

100

0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 11-1 THD+N vs Output Power for PMP0

Figure 11-2 THD+N vs Output Power for PMP1

100

10

100

10

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

1

0,1

0,01

0,001

0,01

0,001

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

Output Power (W)

Figure 11-4 THD+N vs Output Power for PMP4

1

10

100

0,001

0,01

0,1

Output Power (W)

Figure 11-3 THD+N vs Output Power for PMP2

1

10

100

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 40 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

1W

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 11-5 THD+N vs Frequency for PMP0

Figure 11-6 THD+N vs Frequency for PMP1

100

10

100

10

1W

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

Frequency (Hz)

Figure 11-7 THD+N vs Frequency for PMP2

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 11-8 THD+N vs Frequency for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 41 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

10

20

30

40

50

60

0

10

20

30

40

50

60

Output Power (W)

Figure 11-9 PMP0 Efficiency (VDD+PVDD) vs Output Power

100

Figure 11-10 PMP1 Efficiency (VDD+PVDD) vs Output Power

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

10

20

30

40

50

60

0

10

20

30

40

50

60

Output Power (W)

Figure 11-11 PMP2 Efficiency (VDD+PVDD) vs Output Power

Figure 11-12 PMP4 Efficiency (VDD+PVDD) vs Output Power

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 42 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

1

100

10

1

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 11-13 Input Power vs Output Power for PMP0

Figure 11-14 Input Power vs Output Power for PMP1

100

10

1

100

10

1

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 11-15 Input Power vs Output Power for PMP2

Figure 11-16 Input Power vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 43 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

10

1

10

1

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

0,1

0,01

0,001

0,01

PMP0

PMP1

PMP2

PMP4

0,001

0,0001 0,001 0,01

0,1

1

10

100 1000

0,0001 0,001 0,01

0,1

1

10

100 1000

Output Power (W)

Figure 11-17 PVDD Current vs Output Power for PMP0 & PMP1

Figure 11-18 PVDD Current vs Output Power for PMP2 & PMP4

10

Load = 8Ω + 22µH

9

8

7

6

5

4

3

2

8

7

6

5

4

3

2

1

0

PMP0

PMP1

PMP2

PMP4

1

0

4

6

8

10 12 14 16 18 20 22 24 26

4

6

8

10 12 14 16 18 20 22 24 26

PVDD (V)

Figure 11-19 PVDD Idle Current vs PVDD for PMP0 & PMP1

Figure 11-20 PVDD Idle Current vs PVDD for PMP2 & PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 44 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

Load = 8Ω + 22µH

1% THD+N

10% THD+N

0

4

6

8

10 12 14 16 18 20 22 24 26

4

6

8

10 12 14 16 18 20 22 24 26

PVDD (V)

Figure 11-21 Output Power vs PVDD for PMP0

Figure 11-22 Output Power vs PVDD for PMP1

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

Load = 8Ω + 22µH

1% THD+N

10% THD+N

0

4

6

8

10 12 14 16 18 20 22 24 26

4

6

8

10 12 14 16 18 20 22 24 26

PVDD (V)

Figure 11-23 Output Power vs PVDD for PMP2

Figure 11-24 Output Power vs PVDD for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 45 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

Frequency (Hz)

Figure 11-26 Gain vs Frequency for PMP1

2000

20000

Frequency (Hz)

Figure 11-25 Gain vs Frequency for PMP0

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 11-27 Gain vs Frequency for PMP2

Figure 11-28 Gain vs Frequency for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 46 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

Ch1 to Ch0

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 11-29 Crosstalk vs Frequency for PMP0

Figure 11-30 Crosstalk vs Frequency for PMP1

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

PVDD = +26V

Load = 8Ω + 22µH

PVDD = +26V

Load = 8Ω + 22µH

Ch1 to Ch0

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 11-31 Crosstalk vs Frequency for PMP2

Frequency (Hz)

Figure 11-32 Crosstalk vs Frequency for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 47 of 88

V 1.1

2022-02-09

12 Typical Characteristics (PVDD = +24V, Load = 4Ω + 22µH)

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

1

0,1

0,01

0,001

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

1

10

100

0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 12-1 THD+N vs Output Power for PMP0

Figure 12-2 THD+N vs Output Power for PMP1

100

10

100

10

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

1

0,1

0,01

0,001

0,01

0,001

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

Output Power (W)

Figure 12-3 THD+N vs Output Power for PMP2

1

10

100

0,001

0,01

0,1

Output Power (W)

Figure 12-4 THD+N vs Output Power for PMP4

1

10

100

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 48 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

1W

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 12-5 THD+N vs Frequency for PMP0

Figure 12-6 THD+N vs Frequency for PMP1

100

10

100

10

1W

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

Frequency (Hz)

Figure 12-7 THD+N vs Frequency for PMP2

2000

20000

20

200

Frequency (Hz)

Figure 12-8 THD+N vs Frequency for PMP4

2000

20000

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 49 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PVDD = +24V

Load = 4Ω + 22µH

Output Power

Per Channel

PVDD = +24V

Load = 4Ω + 22µH

Output Power

Per Channel

0

10 20 30 40 50 60 70 80 90

0

10 20 30 40 50 60 70 80 90

Output Power (W)

Figure 12-9 PMP0 Efficiency (VDD+PVDD) vs Output Power

100

Figure 12-10 PMP1 Efficiency (VDD+PVDD) vs Output Power

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PVDD = +24V

Load = 4Ω + 22µH

Output Power

Per Channel

PVDD = +24V

Load = 4Ω + 22µH

Output Power

Per Channel

0

10 20 30 40 50 60 70 80 90

0

10 20 30 40 50 60 70 80 90

Output Power (W)

Figure 12-11 PMP2 Efficiency (VDD+PVDD) vs Output Power

Figure 12-12 PMP4 Efficiency (VDD+PVDD) vs Output Power

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 50 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

1

100

10

1

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 12-13 Input Power vs Output Power for PMP0

Figure 12-14 Input Power vs Output Power for PMP1

100

10

1

100

10

1

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 12-15 Input Power vs Output Power for PMP2

Figure 12-16 Input Power vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 51 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

10

1

10

1

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

0,1

0,01

0,001

PMP0

PMP1

0,001

0,0001 0,001 0,01

0,1

1

10

100 1000

0,0001 0,001 0,01

0,1

1

10

100 1000

Output Power (W)

Figure 12-17 PVDD Current vs Output Power for PMP0

Figure 12-18 PVDD Current vs Output Power for PMP1

10

1

10

1

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

0,1

0,01

PMP2

PMP4

0,001

0,0001 0,001 0,01

0,1

1

10

100 1000

0,0001 0,001 0,01

0,1

1

10

100 1000

Output Power (W)

Figure 12-19 PVDD Current vs Output Power for PMP2

Figure 12-20 PVDD Current vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 52 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 12-21 Gain vs Frequency for PMP0

Figure 12-22 Gain vs Frequency for PMP1

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 12-23 Gain vs Frequency for PMP2

Figure 12-24 Gain vs Frequency for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 53 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

Ch1 to Ch0

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 12-25 Crosstalk vs Frequency for PMP0

Figure 12-26 Crosstalk vs Frequency for PMP1

0

-10

0

-10

Ch0 to Ch1

PVDD = +24V

Load = 4Ω + 22µH

PVDD = +24V

Load = 4Ω + 22µH

Ch1 to Ch0

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 12-27 Crosstalk vs Frequency for PMP2

Frequency (Hz)

Figure 12-28 Crosstalk vs Frequency for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 54 of 88

V 1.1

2022-02-09

13 Typical Characteristics (PVDD = +24V, Load = 8Ω + 22µH)

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

1

0,1

0,01

0,001

0,01

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

1

10

100

0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 13-1 THD+N vs Output Power for PMP0

Figure 13-2 THD+N vs Output Power for PMP1

100

10

100

10

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

1

0,1

0,01

0,001

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

Output Power (W)

Figure 13-3 THD+N vs Output Power for PMP2

1

10

100

0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 13-4 THD+N vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 55 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

1W

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 13-5 THD+N vs Frequency for PMP0

Figure 13-6 THD+N vs Frequency for PMP1

100

10

100

10

1W

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

Frequency (Hz)

Figure 13-7 THD+N vs Frequency for PMP2

2000

20000

20

200

Frequency (Hz)

Figure 13-8 THD+N vs Frequency for PMP4

2000

20000

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 56 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PVDD = +24V

Load = 8Ω + 22µH

Output Power

Per Channel

PVDD = +24V

Load = 8Ω + 22µH

Output Power

Per Channel

0

10

20

30

40

50

0

10

20

Output Power (W)

Figure 13-10 PMP1 Efficiency (VDD+PVDD) vs Output Power

30

40

50

Output Power (W)

Figure 13-9 PMP0 Efficiency (VDD+PVDD) vs Output Power

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

10

20

30

40

50

0

10

20

Output Power (W)

Figure 13-11 PMP2 Efficiency (VDD+PVDD) vs Output Power

30

40

50

Output Power (W)

Figure 13-12 PMP4 Efficiency (VDD+PVDD) vs Output Power

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 57 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

1

100

10

1

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 13-13 Input Power vs Output Power for PMP0

Figure 13-14 Input Power vs Output Power for PMP1

100

10

1

100

10

1

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 13-15 Input Power vs Output Power for PMP2

Figure 13-16 Input Power vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 58 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

10

1

10

1

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

0,1

0,01

0,001

PMP1

10

PMP0

10

0,001

0,0001 0,001

0,01

0,1

1

100

0,0001 0,001

0,01

0,1

1

100

Output Power (W)

Figure 13-17 PVDD Current vs Output Power for PMP0

Figure 13-18 PVDD Current vs Output Power for PMP1

10

1

10

1

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

0,1

0,01

0,001

PMP4

PMP2

0,001

0,0001 0,001

0,01

Output Power (W)

Figure 13-20 PVDD Current vs Output Power for PMP4

0,1

1

10

100

0,0001 0,001

0,01

Output Power (W)

Figure 13-19 PVDD Current vs Output Power for PMP2

0,1

1

10

100

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 59 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 13-21 Gain vs Frequency for PMP0

Figure 13-22 Gain vs Frequency for PMP1

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

Frequency (Hz)

Figure 13-23 Gain vs Frequency for PMP2

2000

20000

20

200

Frequency (Hz)

Figure 13-24 Gain vs Frequency for PMP4

2000

20000

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 60 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

Ch1 to Ch0

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 13-25 Crosstalk vs Frequency for PMP0

Figure 13-26 Crosstalk vs Frequency for PMP1

0

-10

0

-10

Ch0 to Ch1

PVDD = +24V

Load = 8Ω + 22µH

PVDD = +24V

Load = 8Ω + 22µH

Ch1 to Ch0

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 13-27 Crosstalk vs Frequency for PMP2

Frequency (Hz)

Figure 13-28 Crosstalk vs Frequency for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 61 of 88

V 1.1

2022-02-09

14 Typical Characteristics (PVDD = +21V, Load = 4Ω + 22µH)

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

1

0,1

0,01

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

1

10

100

0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 14-1 THD+N vs Output Power for PMP0

Figure 14-2 THD+N vs Output Power for PMP1

100

10

100

10

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

1

0,1

0,01

0,001

0,01

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

Output Power (W)

Figure 14-4 THD+N vs Output Power for PMP4

1

10

100

0,001

0,01

0,1

Output Power (W)

Figure 14-3 THD+N vs Output Power for PMP2

1

10

100

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 62 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

1W

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 14-5 THD+N vs Frequency for PMP0

Figure 14-6 THD+N vs Frequency for PMP1

100

10

100

10

1W

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

Frequency (Hz)

Figure 14-7 THD+N vs Frequency for PMP2

2000

20000

20

200

Frequency (Hz)

Figure 14-8 THD+N vs Frequency for PMP4

2000

20000

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 63 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PVDD = +21V

Load = 4Ω + 22µH

Output Power

Per Channel

PVDD = +21V

Load = 4Ω + 22µH

Output Power

Per Channel

0

10

20

Output Power (W)

Figure 14-9 PMP0 Efficiency (VDD+PVDD) vs Output Power

30

40

50

60

70

0

10

20

Output Power (W)

Figure 14-10 PMP1 Efficiency (VDD+PVDD) vs Output Power

30

40

50

60

70

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

10

20

30

40

50

60

70

0

10

20

Output Power (W)

Figure 14-12 PMP4 Efficiency (VDD+PVDD) vs Output Power

30

40

50

60

70

Output Power (W)

Figure 14-11 PMP2 Efficiency (VDD+PVDD) vs Output Power

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 64 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

1

100

10

1

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 14-13 Input Power vs Output Power for PMP0

Figure 14-14 Input Power vs Output Power for PMP1

100

10

1

100

10

1

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

Output Power (W)

Figure 14-15 Input Power vs Output Power for PMP2

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 14-16 Input Power vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 65 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

10

1

10

1

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

0,1

0,01

0,001

0,01

0,001

PMP0

PMP1

0,0001 0,001 0,01

0,1

1

10

100 1000

0,0001 0,001 0,01

0,1

1

10

100 1000

Output Power (W)

Figure 14-17 PVDD Current vs Output Power for PMP0

Figure 14-18 PVDD Current vs Output Power for PMP1

10

1

10

1

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

0,1

0,01

0,001

0,01

PMP2

PMP4

0,001

0,0001 0,001 0,01

0,1

1

10

100 1000

0,0001 0,001 0,01

0,1

1

10

100 1000

Output Power (W)

Figure 14-19 PVDD Current vs Output Power for PMP2

Figure 14-20 PVDD Current vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 66 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

Frequency (Hz)

Figure 14-21 Gain vs Frequency for PMP0

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 14-22 Gain vs Frequency for PMP1

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

Frequency (Hz)

Figure 14-23 Gain vs Frequency for PMP2

2000

20000

20

200

Frequency (Hz)

Figure 14-24 Gain vs Frequency for PMP4

2000

20000

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 67 of 88

V 1.1

2022-02-09

BTL configuration; Load = 4Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

Ch1 to Ch0

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 14-25 Crosstalk vs Frequency for PMP0

Figure 14-26 Crosstalk vs Frequency for PMP1

0

-10

0

-10

Ch0 to Ch1

PVDD = +21V

Load = 4Ω + 22µH

PVDD = +21V

Load = 4Ω + 22µH

Ch1 to Ch0

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 14-28 Crosstalk vs Frequency for PMP4

Figure 14-27 Crosstalk vs Frequency for PMP2

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 68 of 88

V 1.1

2022-02-09

15 Typical Characteristics (PVDD = +21V, Load = 8Ω + 22µH)

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

1

0,1

0,01

0,001

0,01

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

1

10

100

0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 15-1 THD+N vs Output Power for PMP0

Figure 15-2 THD+N vs Output Power for PMP1

100

10

100

10

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

1

0,1

0,01

100Hz

1kHz

6kHz

100Hz

1kHz

6kHz

0,001

0,01

0,1

Output Power (W)

Figure 15-3 THD+N vs Output Power for PMP2

1

10

100

0,001

0,01

0,1

Output Power (W)

Figure 15-4 THD+N vs Output Power for PMP4

1

10

100

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 69 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

100

10

1W

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

2000

20000

Frequency (Hz)

Figure 15-5 THD+N vs Frequency for PMP0

Figure 15-6 THD+N vs Frequency for PMP1

100

10

100

10

1W

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

5W

10W

1

0,1

0,01

0,001

0,01

0,001

20

200

2000

20000

20

200

Frequency (Hz)

Figure 15-8 THD+N vs Frequency for PMP4

2000

20000

Frequency (Hz)

Figure 15-7 THD+N vs Frequency for PMP2

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 70 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

5

10

15

Output Power (W)

Figure 15-9 PMP0 Efficiency (VDD+PVDD) vs Output Power

20

25

30

35

40

0

5

10

15

Output Power (W)

Figure 15-10 PMP1 Efficiency (VDD+PVDD) vs Output Power

20

25

30

35

40

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0

5

10

15

Output Power (W)

Figure 15-12 PMP4 Efficiency (VDD+PVDD) vs Output Power

20

25

30

35

40

0

5

10

15

Output Power (W)

Figure 15-11 PMP2 Efficiency (VDD+PVDD) vs Output Power

20

25

30

35

40

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 71 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

100

10

1

100

10

1

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 15-13 Input Power vs Output Power for PMP0

Figure 15-14 Input Power vs Output Power for PMP1

100

10

1

100

10

1

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

Output Power

Per Channel

Output Power

Per Channel

0,1

0,0001 0,001

0,01

Output Power (W)

Figure 15-15 Input Power vs Output Power for PMP2

0,1

1

10

100

0,0001 0,001

0,01

0,1

1

10

100

Output Power (W)

Figure 15-16 Input Power vs Output Power for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 72 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

10

1

10

1

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

0,1

0,01

0,001

0,01

0,001

PMP0

10

PMP1

10

0,0001 0,001

0,01

0,1

1

100

0,0001 0,001

0,01

0,1

1

100

Output Power (W)

Figure 15-17 PVDD Current vs Output Power for PMP0

Figure 15-18 PVDD Current vs Output Power for PMP1

10

1

10

1

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

0,1

0,01

PMP2

PMP4

0,001

0,0001 0,001

0,01

Output Power (W)

Figure 15-19 PVDD Current vs Output Power for PMP2

0,1

1

10

100

0,0001 0,001

0,01

Output Power (W)

Figure 15-20 PVDD Current vs Output Power for PMP4

0,1

1

10

100

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 73 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

Frequency (Hz)

Figure 15-21 Gain vs Frequency for PMP0

2000

20000

20

200

Frequency (Hz)

Figure 15-22 Gain vs Frequency for PMP1

2000

20000

27

26,8

26,6

26,4

26,2

26

27

26,8

26,6

26,4

26,2

26

1W

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

5W

10W

25,8

25,6

25,4

25,2

25

25,8

25,6

25,4

25,2

25

20

200

2000

20000

20

200

Frequency (Hz)

Figure 15-24 Gain vs Frequency for PMP4

2000

20000

Frequency (Hz)

Figure 15-23 Gain vs Frequency for PMP2

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 74 of 88

V 1.1

2022-02-09

BTL configuration; Load = 8Ω + 22µH; Measurements carried out with APx 515 + AUX-0025 input filter; APx uses

AES17 brick-wall filter (20kHz).

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

Ch0 to Ch1

Ch1 to Ch0

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 15-25 Crosstalk vs Frequency for PMP0

Figure 15-26 Crosstalk vs Frequency for PMP1

0

-10

0

-10

Ch0 to Ch1

Ch1 to Ch0

PVDD = +21V

Load = 8Ω + 22µH

PVDD = +21V

Load = 8Ω + 22µH

Ch1 to Ch0

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

20

200

2.000

20.000

20

200

2.000

20.000

Frequency (Hz)

Figure 15-27 Crosstalk vs Frequency for PMP2

Figure 15-28 Crosstalk vs Frequency for PMP4

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 75 of 88

V 1.1

2022-02-09

16 Register map

For all register map:

“ f “ : Don’t Care condition

“ – “ : Reserved bits configured during factory settings.

Read / Write Access (Power Mode Settings):

Default

Address Address

Value

Description

Name

Bit(s)

Value

Function

Select manual Power Mode control. Default

the device will operate in automatic Power

Mode control. This bit can be set to 1 if manual

Power Mode control is required.

manualPM

6

- 0 1 1 - - - -

Manual selected power mode. These two bits

can be used selecting the Power Mode of the

device when it is in manual Power Mode

control.

Power Mode

Control

- 0 1 1 - - - -

0x00

0x3D

PM_man

5:4

- - 0 0 - - - -

- - 0 1 - - - -

- - 1 0 - - - -

- - 1 1 - - - -

Reserved

Power Mode 1

Power Mode 2

Power Mode 3

Threshold value for PM1=>PM2 change. This

value will set the threshold for when automatic

0 0 1 1 1 1 0 0 Power Mode changes from PM1 to PM2. It can

be programmed from 0 - 255; this maps to 0

output power – max output power.

Threshold for

Power Mode

change

0x01

0x02

0x03

0x3C

0x32

0x5A

Mthr_1to2

Mthr_2to1

Mthr_2to3

7:0

PM1=>PM2

Threshold value for PM2=>PM1 change. This

value will set the threshold for when automatic

0 0 1 1 0 0 1 0 Power Mode changes from PM2 to PM1. It can

be programmed from 0 - 255; this maps to 0

Threshold for

Power Mode

change

PM2=>PM1

output power – max output power.

Threshold value for PM2=>PM3 change. This

value will set the threshold for when automatic

0 1 0 1 1 0 1 0 Power Mode changes from PM2 to PM3. It can

be programmed from 0 - 255; this maps to 0

Threshold for

Power Mode

change

PM2=>PM3

output power – max output power.

Threshold value for PM3=>PM2 change. This

value will set the threshold for when automatic

0 1 0 1 0 0 0 0 Power Mode changes from PM3 to PM2. It can

be programmed from 0 - 255; this maps to 0

Threshold for

Power Mode

change

0x04

0x50

Mthr_3to2

7:0

PM3=>PM2

output power – max output power.

0x07

0x00

Disable DCU1 dcu1_disable

Disable DCU0 dcu0_disable

7

6

1 - - - - - - -

- 1 - - - - -

Disables CH0 of the amplifier

Disables CH1 of the amplifier

Enables soft-clipping. High to enable. Low to

disable.

Soft-clipping

and over-

current

protection

latching

lf_clamp_en

ocp_latch_en

7

1

0 - - - - - 0 -

0x0A

0xC

High to use permanently latching OCP.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 76 of 88

V 1.1

2022-02-09

Read / Write Access (Power Mode Profile Settings):

Default

Address Address

Value

Description

Name

Bit(s)

Value

Function

Power Mode Profile select. With this register

the user can selects the appropriate Power

Mode Profile.

f f f f f 0 0 0

- - - - - 0 0 0

- - - - - 0 0 1

- - - - - 0 1 0

- - - - - 0 1 1

- - - - - 1 0 0

- - - - - 1 0 1

f f 1 0 - - - -

- - 0 0 - - - -

- - 0 1 - - - -

- - 1 0 - - - -

- - 1 1 - - - -

f f - - 1 1 - -

- - - - 0 0 - -

- - - - 0 1 - -

- - - - 1 0 - -

- - - - 1 1 - -

f f - - - - 1 1

- - - - - - 0 0

- - - - - - 0 1

- - - - - - 1 0

- - - - - - 1 1

Power Mode Profile 0

Power Mode Profile 1

Power Mode Profile 2

Power Mode Profile 3

Select Power

Mode Profile

setting

0x1D

0x00

PMprofile

2:0

Power Mode Profile 4

Power Mode Profile 5 (custom profile)

Custom profile PM3 content

Assign scheme A to PM3

Assign scheme B to PM3

Assign scheme C to PM3

Assign scheme D to PM3

Custom profile PM2 content

Assign scheme A to PM2

Assign scheme B to PM2

Assign scheme C to PM2

Assign scheme D to PM2

Custom profile PM1 content

Assign scheme A to PM1

Assign scheme B to PM1

Assign scheme C to PM1

Assign scheme D to PM1

PM3_man

PM2_man

PM1_man

5:4

3:2

Power Mode

Profile

configuration

0x1E

0x2F

1:0

7

Over-current

protection

latch clear

Clears over current protection latch. A low to

high toggle clears the current OCP latched

condition.

ocp_latch_cle

ar

0x20

0x1F

0 - - - - - - -

Enables or disables DC protection. High to

enable. Low to disable.

0x26

0x2D

0x05

0x10

DC protection

Eh_dcShdn

eh_clear

2

f f f f - 1 - -

- - - - - 0 - -

Error handler

clear

Clears error handler. A low-to-high-to-low

toggle clears the error handler.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 77 of 88

V 1.1

2022-02-09

Read / Write Access (I2S format configuration)

Default

Address Address

Value

Description

Name

Bit(s)

Value

Function

0 0 0 0 0 0 0 0 i2s standard

0 0 0 0 0 0 0 1 Left justified

0 0 0 0 0 1 0 0 Right justified 16bits

0 0 0 0 0 1 1 0 Right justified 18bits

0 0 0 0 0 0 0 0 Right justified 20bits

0 0 0 0 0 1 1 1 Right justified 24bits

PCM word

format

0x35

0x01

i2s_format

2:0

Left PCM data word (of a simultaneously

sampled PCM data pair) is send first

0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 1

0 0 0 0 0 0 0 1

0 0 0 0 1 0 0 1

0 0 0 1 0 0 0 1

0 0 0 0 0 0 0 1

0 0 0 0 0 1 0 1

Left/right

order of PCM

words

i2s_rightfirst

i2s_framesize

i2s_order

5

4:3

2

Right PCM data word (of a simultaneously

sampled PCM data pair) is send first

64 serial clock (SCK) cycles are present in each

period of the word select signal (WS)

Number of

data bits per

frame

48 serial clock (SCK) cycles are present in each

period of the word select signal (WS)

32 serial clock (SCK) cycles are present in each

period of the word select signal (WS)

Most significant bit of the PCM data word is

transmitted first

Bit order of

PCM data

words

Least significant bit of the PCM data word is

transmitted first

0x36

0x01

First word of a simultaneously sampled PCM

0 0 0 0 0 0 0 1 data pair is transmitted while word select (WS)

is low

Pairing of

data words

i2s_ws_pol

1

First word of a simultaneously sampled PCM

0 0 0 0 0 0 1 1 data pair is transmitted while word select (WS)

is high

Serial data (SDX) and word select (WS) are

changing at rising edge of the serial clock signal

(SCK). The MA12070P will capture data at the

0 0 0 0 0 0 0 0

Clocking edge

of the serial

clock signal

(SCK)

falling edge of the serial clock signal SCK

i2s_sck_pol

0

Serial data (SDX) and word select (WS) are

changing at falling edge of the serial clock

0 0 0 0 0 0 0 1

signal (SCK). The MA12070P will capture data

at the rising edge of the serial clock signal SCK

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 78 of 88

V 1.1

2022-02-09

Read / Write Access (Volume control and limiter)

Default

Address Address

Value

Description

Name

Bit(s)

Value

Function

0 0 0 0 0 0 0 1 Slow attack time

0 1 0 0 0 0 0 1 Normal attack time

1 0 0 0 0 0 0 1 Fast attack time

0 0 0 0 0 0 0 1 Slow release time

0 0 0 1 0 0 0 1 Normal release time

0 0 1 0 0 0 0 1 Fast release time

0 0 0 0 0 0 01 Bypass the audio processor

0 0 0 0 1 0 01 Use the audio processor

1 0 0 0 0 0 0 1 Mute audio

Limiter attack audio_proc_rele

7:6

time control

ase

audio_proc_atta

ck

0x35

0x01

Limiter release

time

5:4

Processor bypass audio_proc_ena

3

7

6

mux

ble

audio_proc_mut

e

Mute mux control

0 0 0 0 0 0 0 1 Play audio

0x36

0x01

0 0 0 0 0 0 0 1 Bypass the limiter

0 1 0 0 0 0 0 1 Use the limiter

Limiter bypass audio_proc_limi

mux

terEnable

Control of integer value master dB volume

(see Table 8-9 for mapping overview)

Control of fractional value dB volume (see

Table 8-9 for mapping overview)

Control of integer value ch0L dB volume (see

Table 8-9 for mapping overview)

Control of integer value ch0R dB volume (see

Table 8-9 for mapping overview)

Control of integer value ch0L dB volume (see

Table 8-9 for mapping overview)

Control of integer value ch0R dB volume (see

Table 8-9 for mapping overview)

Control of fractional value ch0L dB volume

(see Table 8-9 for mapping overview)

Control of fractional value ch0R dB volume

(see Table 8-9 for mapping overview)

Control of fractional value ch1L dB volume

(see Table 8-9 for mapping overview)

Control of fractional value ch1R dB volume

(see Table 8-9 for mapping overview)

Control of integer value ch0L dBFS limiter

Master integer dB

volume

0x40

0x41

0x42

0x43

0x44

0x45

0x18

0x00

0x18

vol_db_master

7:0

1:0

7:0

1:0

3:2

5:4

7:6

7:0

1:0

0 0 0 1 1 0 0 0

f f f f f f 0 0

Master fract dB

volume

vol_lsb_master

vol_db_ch0

vol_db_ch1

vol_db_ch2

vol_db_ch3

vol_lsb_ch0

vol_lsb_ch1

vol_lsb_ch2

vol_lsb_ch3

thr_db_ch0

thr _db_ch1

thr _db_ch2

thr _db_ch3

thr _lsb_ch0

thr _lsb_ch1

thr _lsb_ch2

thr _lsb_ch3

Ch0L integer dB

volume

0 0 0 1 1 0 0 0

0 0 0 0 0 0 0 0

0 0 0 1 1 0 0 0

0 0 0 0 0 0 0 0

Ch0R integer dB

volume

Ch1L integer dB

volume

Ch1R integer dB

volume

Ch0L fract dB

volume

Ch0R fract dB

volume

0x46

0x00

Ch1L fract dB

volume

Ch0R fract dB

volume

Ch0L integer dBFS

limiter

0x47

0x48

0x49

0x4A

0x18

threshold (see section “Limiter”)

Ch0R integer dBFS

limiter

Control of integer value ch0R dBFS limiter

threshold (see section “Limiter”)

Ch1L integer dBFS

limiter

Control of integer value ch0L dBFS limiter

threshold (see section “Limiter)

Ch1R integer dBFS

limiter

Control of integer value ch0R dBFS limiter

threshold (see section “Limiter”)

Ch0L fract dBFS

limiter

Control of fractional value ch0L dBFS limiter

threshold (see section “Limiter”)

Ch0R fract dBFS

limiter

Control of fractional value ch0R dBFS limiter

threshold (see section “Limiter”)

0x4B

0x00

Ch1L fract dBFS

limiter

Control of fractional value ch1L dBFS limiter

threshold (see section “Limiter”)

Ch0R fract dBFS

limiter

Control of fractional value ch1R dBFS limiter

threshold (see section “Limiter”)

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 79 of 88

V 1.1

2022-02-09

Read Only Access (Volume control and limiter monitor)

Default

Address Address

Value

Description

Name

Bit(s)

Value

Function

Bit 4 high: limiter is active on channel 0L

Indicates if

limiters are

active

Bit 5 high: limiter is active on channel 0R

Bit 6 high: limiter is active on channel 1L

Bit 7 high: limiter is active on channel 0R

Bit 0 high: clipping is present on channel 0L

Bit 1 high: clipping is present on channel 0R

Bit 2 high: clipping is present on channel 1L

Bit 3 high: clipping is present on channel 0R

audio_proc_li

miter_mon

0x7E

0x00

7:4

0 0 0 0 0 0 0 0

Indicates if

clipping

occurs on the

VLP output

signals

audio_proc_c

lip_mon

0x7E

3:0

0 0 0 0 0 0 0 0

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 80 of 88

V 1.1

2022-02-09

Read Only Access (Monitor Channel 0 and Channel 1)

Default

Address Address

Value

Description

Name

Bit(s)

Value

Function

Frequency mode monitor channel 0. Register

to read out in which frequency mode channel 0

of the device is currently operating in.

Monitor

register

channel 0

(Frequency

and Power

Mode)

dcu_mon0.fr

eqMode

6:4

- 0 0 0 f f 0 0

0x60

0x00

Power mode monitor channel 0. Monitor to

read out in which Power Mode channel 0 of

the device is currently operating in.

dcu_mon0.P

M_mon

1:0

- - - - f f 0 0

dcu_mon0.m

ute

dcu_mon0.vd

d_ok

dcu_mon0.pv

dd_ok

Channel 0 mute monitor. Monitor to read out

if channel 0 is in mute or in unmute.

Channel 0 VDD monitor. Monitor to read out if

VDD for channel 0 is ok.

Channel 0 PVDD monitor. Monitor to read out

if PVDD for channel 0 is ok.

5

4

3

2

1

f f 0 0 0 0 0 0

Monitor

register

dcu_mon0.Vc

fly2_ok

Channel 0 Cfly2 protection monitor. Monitor to

read out if Cfly2 for channel 0 is ok.

0x61

0x00

channel 0

dcu_mon0.Vc

fly1_ok

Channel 0 Cfly1 protection monitor. Monitor to

read out if Cfly1 for channel 0 is ok.

Channel 0 over current protection monitor.

f f 0 0 0 0 0 0 Monitor to read out if an over current

protection event has occurred.

OCP Monitor

channel 0

0

Monitor

register

channel 0

(Modulation

Index)

Channel 0 modulation index monitor. Monitor

to read out live modulation index. Modulation

index from 0 to 1 maps on the 8-bits register

from 0 to 255.

dcu_mon0.M

_mon

0x62

0x64

0x00

7:0

0 0 0 0 0 0 0 0

Frequency mode monitor channel 1. Register

to read out in which frequency mode channel 1

of the device is currently operating in.

Monitor

register

channel 1

(Frequency

and Power

Mode)

dcu_mon1.fr

eqMode

6:4

1:0

- 0 0 0 f f 0 0

- - - - f f 0 0

Power mode monitor channel 1. Monitor to

read out in which Power Mode channel 1 of

the device is currently operating in.

dcu_mon1.P

M_mon

dcu_mon1.m

ute

Channel 1 mute monitor. Monitor to read out

if channel 1 is in mute or in unmute.

5

4

3

2

1

f f 0 0 0 0 0 0

dcu_mon1.vd

d_ok

Channel 1 VDD monitor. Monitor to read out if

VDD for channel 1 is ok.

dcu_mon1.pv

dd_ok

Channel 1 PVDD monitor. Monitor to read out

if PVDD for channel 1 is ok.

Monitor

register

0x65

0x00

dcu_mon1.Vc

fly2_ok

Channel 1 Cfly2 protection monitor. Monitor to

read out if Cfly2 for channel 1 is ok.

channel 1

dcu_mon1.Vc

fly1_ok

Channel 1 Cfly1 protection monitor. Monitor to

read out if Cfly1 for channel 1 is ok.

Channel 1 over current protection monitor.

f f 0 0 0 0 0 0 Monitor to read out if an over current

protection event has occurred.

OCP Monitor

channel 1

0

Monitor

register

channel 1

(Modulation

Index)

Channel 1 modulation index monitor. Monitor

to read out live modulation index. Modulation

index from 0 to 1 maps on the 8-bits register

from 0 to 255.

dcu_mon1.M

_mon

0x66

0x00

7:0

0 0 0 0 0 0 0 0

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 81 of 88

V 1.1

2022-02-09

Read Only Access (Error Register Monitoring):

Default

Address Address

Value

Description

Name

Bit(s)

Value

Error monitor register. Gives the accumulated

status of every potential error source. This

register should be cleared by using the error

handler clear register.

All bits will be 0 in default/normal operation

and 1 when triggered

Error

accumulated

register

Bit 0: flying capacitor over-voltage error

Bit 1: over-current protection

Bit 2: pll error

0x6D

0x00

error_acc

7:0

0 0 0 0 0 0 0 0

Bit 3: PVDD under-voltage protection

Bit 4: over-temperature warning

Bit 5: over-temperature error

Bit 6: pin-to-pin low impedance protection

Bit 7: DC protection

MSEL[2:0] monitor register. Monitor to read

out which output configuration the device is in:

BTL, SE, BTL/SE or PBTL

Monitor

MSEL register

0x75

0x7C

0x00

msel_mon

2:0

7:0

f f f f f 0 0 0

Error monitor register. Gives the live status of

every potential error source.

All bits will be 0 in default/normal operation

and 1 when triggered

Bit 0: flying capacitor over-voltage error

Bit 1: over-current protection

Bit 2: pll error

Error register

error

0 0 0 0 0 0 0 0

Bit 3: PVDD under-voltage protection

Bit 4: over-temperature warning

Bit 5: over-temperature error

Bit 6: pin-to-pin low impedance protection

Bit 7: DC protection

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 82 of 88

V 1.1

2022-02-09

17 Package Information

QFN pad-down 64-pin mechanical data

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 83 of 88

V 1.1

2022-02-09

18 Tape and Reel Information

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 84 of 88

V 1.1

2022-02-09

19 Revision History

Doc. Rev.

V 1.0

Date

Comments

July

2018

Initial release in Infineon format

Silicon update. Improve of DC offset in BTL, PBTL and 2.1 configurations. Correction of

known issues and limitations in errata sheet v1.0 in sections 1.1, 1.2 and 1.4.

Show power mode profile 5 value as “101” in 0X1D register address.

Show channel disable register 0x07.

Feb

2022

V 1.1

Running the DAC directly from the MCLK is not supported, delete functionality.

Amplifier gain modification is not supported, delete register.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 85 of 88

V 1.1

2022-02-09

20 Contents

Description

Applications

Features

1

Package

1

2

3

4

Ordering Information

2

3

4

Known Issues and Limitations

Typical Application Block Diagram

Pin Description

4.1

4.2

Pinout MA12070P

Pin Function

4

5

6

7

8

Absolute Maximum Ratings

7

8

Recommended Operating Conditions

Electrical and Audio Characteristics

Functional description

9

12

Multi-level modulation

Very low power consumption

Power Mode Management

Power Modes Profiles

Power supplies

12

13

14

15

16

17

19

20

21

22

23

24

25

26

Gate driver supplies

Digital core supply

Flying capacitors

Protection

Over-current protection on OUTXX nodes

Temperature protection

Power supply monitors

DC protection

Digital serial audio input

Volume and limiter processor (VLP)

Volume control

Limiter

VLP parameter interface

Clock system

MCU/Serial control interface

I2C write operation

I2C read operation

/CLIP pin and soft-clipping

/ERROR pin and error handling

9

Application Information

27

Input/Output Configurations

27

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 86 of 88

V 1.1

2022-02-09

Bridge Tied Load (BTL) Configuration

Single Ended (SE) Configuration

27

28

29

30

31

Combined SE and BTL Configuration

Parallel Bridge Tied Load (PBTL)

EMC output filter Considerations

Audio Performance Measurements

Thermal Characteristics and Test Signals

Start-up procedure

Shut-down / power-down procedure

Recommended PCB Design for MA12070P (EPAD-down package)

10

11

12

13

14

15

16

Typical Characteristics (PVDD = +26V, Load = 4Ω + 22µH)

Typical Characteristics (PVDD = +26V, Load = 8Ω + 22µH)

Typical Characteristics (PVDD = +24V, Load = 4Ω + 22µH)

Typical Characteristics (PVDD = +24V, Load = 8Ω + 22µH)

Typical Characteristics (PVDD = +21V, Load = 4Ω + 22µH)

Typical Characteristics (PVDD = +21V, Load = 8Ω + 22µH)

Register map

32

40

48

55

62

69

76

Read / Write Access (Power Mode Settings):

76

77

78

79

80

81

82

Read / Write Access (Power Mode Profile Settings):

Read / Write Access (I2S format configuration)

Read / Write Access (Volume control and limiter)

Read Only Access (Volume control and limiter monitor)

Read Only Access (Monitor Channel 0 and Channel 1)

Read Only Access (Error Register Monitoring):

17

18

19

20

Package Information

Tape and Reel Information

Revision History

83

84

85

86

Contents

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 87 of 88

V 1.1

2022-02-09

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information contained in this application note is For further information on the product, technology,

given as a hint for the implementation of the product delivery terms and conditions and prices please

only and shall in no event be regarded as a contact your nearest Infineon Technologies office

description or warranty of a certain functionality, (www.infineon.com).

condition or quality of the product. Before

Published by

Infineon Technologies AG

81726 Munich, Germany

implementation of the product, the recipient of this

application note must verify any function and other

technical information given herein in the real

application. Infineon Technologies hereby disclaims

any and all warranties and liabilities of any kind

(including without limitation warranties of non-

infringement of intellectual property rights of any

third party) with respect to any and all information

given in this application note.

WARNINGS

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about this

document?

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized

representatives

of

Infineon

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

Email: erratum@infineon.com

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

Document reference


型号：	MA12070P
厂家：	Infineon
描述：	2x80W 超高功效全集成式音频功放 IC，带 I2S 数字输入功效
文件：	总88页 (文件大小：2172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MA12070P [INFINEON]

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