MA2304PNS [INFINEON]
MERUS™ D 类音频放大器，2x37 W，10-20 V，超低待机功率，无电感工作，带音量控制和峰值限制器;
| 型号： | MA2304PNS |
| 厂家： | 
Infineon |
| 描述： | MERUS™ D 类音频放大器，2x37 W，10-20 V，超低待机功率，无电感工作，带音量控制和峰值限制器 限制器 放大器 音频放大器 |
| 文件： | 总43页 (文件大小：2064K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢁ×ꢂꢆ W, ꢀꢅ to ꢁꢅ V, Ultra‑Low Idle Power, MERUS™ Multilevel Switching
Class‑D Audio Amplifier with Inductor‑Less Operation
MAꢁꢂꢅꢃPNS
ꢀ FEATURES
ꢂ DESCRIPTION
MERUS™ multilevel switching technology
The MAꢁꢄꢉꢈPNS is a ꢁ×ꢄꢆ W audio amplifier with IꢁS/TDM
audio interface. It features the MERUS™ multilevel switch‑
ing amplifier technology enabling unmatched power ef‑
ficiency at both low and high output power. Multilevel
switching also relaxes EMI and enables inductor‑less appli‑
cations with lower cost and no compromise in audio perfor‑
mance or eꢅiciency. A high order internal feedback loop en‑
sures low THD for excellent audio performance. The ultra‑
low idle power consumption is at least five times lower than
the traditional class D audio amplifiers in the market, mak‑
ing MAꢁꢄꢉꢈPNS ideal for battery powered speaker appli‑
cations with extended battery life and/or reduced battery
cell cost. In mains‑powered multichannel applications, the
reduced and scalable EMI performance, enables otherwise
impossible industrial designs, without the necessity for a
heatsink or a traditional LC filter.
• ꢀ‑level voltage modulation for ultra‑low idle power con‑
sumption: ꢀꢁ mW @ ꢂꢃ PVDD (LPC mode) without the
need of complex dynamic rail‑tracking systems
• Inductor‑less application for reduced system cost without
output power limitations
• Reduced EMI emissions compared to traditional ꢁ and ꢄ
level class D audio amplifiers for fast time to market with‑
out compromises in audio performance or eꢅiciency
• High eꢅiciency at low output power: ꢆꢇ %, ꢁ×ꢂ W, ꢃ Ω
for extended battery life and easy thermal management
in multichannel products even in idle state
Flexible configuration and application
• BTL rated output: ꢁ×ꢄꢆ W, ꢂꢃ V, ꢈ Ω, ꢂꢉ% THD
• PBTL rated output: ꢂ×ꢆꢈ W, ꢂꢃ V, ꢁ Ω, ꢂꢉ% THD
• PVDD voltage range: ꢂꢉ V to ꢁꢉ V
ꢃ PRODUCT VALIDATION
Qualification standard: Standard
• High eꢅiciency at low output power: ꢆꢇ %, ꢁ×ꢂ W, ꢃ Ω
ꢄ TYPICAL APPLICATION
• Selectable power mode profiles: Low Power Consump‑
tion (LPC) or High Audio Performance (HAP)
1.8/3.3V
EMC ferrite
filter
PVDD
• Short circuit protection: ꢊ A peak (BTL) / ꢂꢁ A peak (PBTL)
• External closed‑loop feedback for improved THD
• Integrated DSP with limiters and volume control
VDD
FB0A
OUT0A
VDDIO
MSEL
PVDD
Audio so urce
I2S/TDM data
CH1
I2S_DI
I2S_SCK
I2S_WS
• Easy configuration over IꢁC‑bus with up to ꢊꢈ device ad‑
dresses
FB0B
OUT0B
FB1A
Audio sink
I2S_DO
I2S/TDM data
• ꢃ‑bit auxiliary ADC for internal temp. / PVDD monitoring
or sampling from external sources
I2C_SCL
I2C_SDA
NMUTE
ENABLE
NERR
OUT1A
CH2
• Configurable switching edge steepness and inter‑chip
PWM sync for multi‑device systems.
HOST/MCU
• No external heatsink required
NCLIP
FB1B
I2C_AD0
Set address: 0x20
Audio performance
I2C_AD1 OUT1B
• Output noise: ꢀꢁ μVrms (A‑weighted, HAP mode)
• Dynamic range: ꢂꢉꢊ dB (A‑weighted, HAP mode)
• THD+N: ꢉ.ꢉꢀ%, ꢀ W, ꢂ kHz
Efficiency VS output power
100
90
80
70
60
50
40
30
20
10
Audio I/O
• ꢄ‑wire digital audio interface (no MCLK required)
• ꢄꢁ, ꢈꢈ.ꢂ, ꢈꢃ, ꢃꢃ.ꢁ, ꢇꢊ, ꢂꢆꢊ.ꢈ, ꢂꢇꢁ kHz sample rates
• IꢁS and TDM formats supported
• Low input‑to‑output latency for echo cancellation
• Post‑DSP IꢁS output for chaining / echo cancellation
PVDD=18V
Load=8 +22µH
MERUS multilevel
Traditional class D
ꢁ TARGET APPLICATIONS
• Battery powered speakers
0.1
1
4
10
20
• Bluetooth/wireless/smart speakers and soundbars
• Conference speakers
Output power [W]
• Multichannel/multi‑room audio systems
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page ꢂ of ꢈꢁ
INTVꢁ.ꢂ.ꢇ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢇ Functional Application Block Diagram
VDD_IO
1 uF
1 µF
1 µF
VDD
PVDD
-
DVSS
VDD
PVDD
PVDD
PVSS
AUX
ADC
Temp
Low voltage
supplies and
reference
sensor
1 µF 10 µF
470 µF
1 µF
voltages
AVSS
FB0A
OUT0A
VFC0AP
VFC0AN
Audio
source / sink
DAC
DAC
I2S_DI
10 µF
I2S_DO
I2S_SCK
I2S_WS
CF0A
0L
Power
Amp
I2S/TDM data
FB0B
OUT0B
VFC0BP
VFC0BN
10 µF
CF0B
FB1A
OUT1A
VFC1AP
VFC1AN
Clock
Power
management
management
10 µF
CF1A
0R
Power
Amp
FB1B
OUT1B
VFC1BP
VFC1BN
Control and protection
10 µF
CF1B
EPAD: VSS
HW
setting
Figure ꢇ.ꢀ: Functional Application Block Diagram
Host system
Datasheet
page ꢁ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Contents
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢇ
ꢆ
ꢈ
ꢉ
FEATURES
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁ
ꢄ
ꢄ
ꢄ
TARGET APPLICATIONS
DESCRIPTION
PRODUCT VALIDATION
TYPICAL APPLICATION
Functional Application Block Diagram
Device Comparison Table
Pin Configuration
Pin List
ꢀꢅ Specifications
ꢆ
ꢆ
ꢆ
ꢆ
ꢃ
ꢂꢉ.ꢂ Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ꢂꢉ.ꢁ ESD and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ꢂꢉ.ꢄ Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ꢂꢉ.ꢈ Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ꢀꢀ Functional description
ꢀꢀ
ꢂꢂ.ꢂ MERUS™ Multilevel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢂ
ꢂꢂ.ꢂ.ꢂ Multilevel Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢂ
ꢂꢂ.ꢂ.ꢁ Reduced Inductor Ripple Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢂ
ꢂꢂ.ꢂ.ꢄ Ultra Low Power Consumption with Music . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢁ
ꢂꢂ.ꢂ.ꢈ EMI Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢁ
ꢂꢂ.ꢂ.ꢀ Power Mode Profiles (PMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢁ
ꢂꢂ.ꢁ Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢄ
ꢂꢂ.ꢁ.ꢂ Normal Operation / Shutdown (ENABLE pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢄ
ꢂꢂ.ꢁ.ꢁ Mute / Unmute (NMUTE pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢄ
ꢂꢂ.ꢁ.ꢄ Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢄ
ꢂꢂ.ꢄ BTL/PBTL Output Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢄ
ꢂꢂ.ꢈ Gain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢄ
ꢂꢂ.ꢀ Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢈ
ꢂꢂ.ꢀ.ꢂ Errors and Error Handling (NERR pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢈ
ꢂꢂ.ꢀ.ꢁ Output DC Protection (DCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢈ
ꢂꢂ.ꢀ.ꢄ Over‑Current Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢀ
ꢂꢂ.ꢀ.ꢈ PVDD Over/Under‑Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢀ
ꢂꢂ.ꢀ.ꢀ Over Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢀ
ꢂꢂ.ꢀ.ꢊ PLL Error and IꢁS Input Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢀ
ꢂꢂ.ꢀ.ꢆ Flying Capacitor Over/Under‑Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢀ
ꢂꢂ.ꢀ.ꢃ NCLIP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢊ
ꢂꢂ.ꢊ Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢊ
ꢂꢂ.ꢊ.ꢂ Supplies for Internal Analog/Digital Circuitry (VDD/VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢊ
ꢂꢂ.ꢊ.ꢁ Flying Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢊ
ꢂꢂ.ꢊ.ꢄ Power Stage Supply (PVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢊ
ꢂꢂ.ꢆ Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢆ
ꢂꢂ.ꢃ Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢆ
ꢂꢂ.ꢃ.ꢂ Digital Serial Audio Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢆ
ꢂꢂ.ꢃ.ꢁ Digital Serial Audio Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢆ
ꢂꢂ.ꢃ.ꢄ Input‑to‑Output Audio Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢆ
ꢂꢂ.ꢇ Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢆ
ꢂꢂ.ꢇ.ꢂ ROM Code / Static Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢆ
Datasheet
page ꢄ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢂꢂ.ꢇ.ꢁ Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢃ
ꢂꢂ.ꢇ.ꢄ Peak Limiter (ROM Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢃ
ꢂꢂ.ꢂꢉAuxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢃ
ꢂꢂ.ꢂꢂIꢁC Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢇ
ꢂꢂ.ꢂꢂ.ꢂ Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢂꢇ
ꢂꢂ.ꢂꢂ.ꢁ IꢁC Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢉ
ꢂꢂ.ꢂꢂ.ꢄ IꢁC Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢉ
ꢂꢂ.ꢂꢁEMI Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢉ
ꢂꢂ.ꢂꢁ.ꢂ Configurable Switching Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢉ
ꢂꢂ.ꢂꢁ.ꢁ PWM Synchronization for EMI Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢉ
ꢂꢂ.ꢂꢄPost‑Ferrite Filter Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢂ
ꢀꢁ Application Information
ꢁꢁ
ꢂꢁ.ꢂ EMC Ferrite Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢁ
ꢂꢁ.ꢂ.ꢂ Capacitor Value Impact on Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢁ
ꢂꢁ.ꢂ.ꢁ Ferrite Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢁ
ꢂꢁ.ꢂ.ꢄ Ferrite Filter Stability Under Light Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢄ
ꢂꢁ.ꢂ.ꢈ LC filter options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢄ
ꢂꢁ.ꢁ Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢄ
ꢂꢁ.ꢄ Start‑up Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢄ
ꢂꢁ.ꢈ Procedure for handling discontinuous audio clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢈ
ꢂꢁ.ꢀ Power‑down Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢈ
ꢂꢁ.ꢊ Recommended Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢈ
ꢂꢁ.ꢆ Evaluation Board as Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢀ
ꢀꢂ Typical Characteristics
ꢁꢆ
ꢂꢄ.ꢂ Eꢅiciency and power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢁꢆ
ꢂꢄ.ꢁ Thermal performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢄꢉ
ꢂꢄ.ꢄ Audio performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ꢄꢂ
ꢀꢃ Register map
ꢂꢃ
ꢃꢅ
ꢃꢁ
ꢀꢄ Package Information
ꢀꢇ Tape and Reel Information
Datasheet
page ꢈ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢆ Device Comparison Table
Table ꢀ: Device comparison
Device name
MAꢁꢄꢉꢈDNS
MAꢁꢄꢉꢈPNS
Functional variance
Fully configurable DSP, ꢂꢉ‑ꢁꢉ V
Audio limiter and volume control only, ꢂꢉ‑ꢁꢉ V
ꢈ Pin Configuration
FB0A
VFC0AN
OUT0A
VFC0AP
PVDD
1
2
3
4
5
6
7
8
9
30 FB1A
29 VFC1AN
28 OUT1A
27 VFC1AP
26 PVDD
25 PVDD
24 VFC1BP
23 OUT1B
22 VFC1BN
21 FB1B
Exposed thermal pad
on bottom side (EPAD):
PVDD
VSS
VFC0BP
OUT0B
VFC0BN
FB0B 10
Figure ꢈ.ꢀ: Package Overview ‑ ꢊxꢊ mm QFN‑ꢈꢉ pins
ꢉ Pin List
Table ꢁ: Pin List MAꢁꢄꢉꢈPNS
Pin Nr.
Name
FBꢉA
Type Description
ꢂ
ꢁ
ꢄ
ꢈ
ꢀ
ꢊ
ꢆ
ꢃ
I
Output channel ꢉA post‑ferrite feedback
Negative side flying capacitor for channel ꢉA
Audio output channel ꢉA
VFCꢉAN
OUTꢉA
VFCꢉAP
PVDD
P
O
P
P
P
P
O
Positive side flying capacitor for channel ꢉA
Power supply for power stage
PVDD
Power supply for power stage
VFCꢉBP
OUTꢉB
Positive side flying capacitor for channel ꢉB
Audio output channel ꢉB
Datasheet
page ꢀ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢇ
VFCꢉBN
FBꢉB
P
I
Negative side flying capacitor for channel ꢉB
Output channel ꢉB post‑ferrite feedback
Error indicator – open drain output. Use this pin as interrupt for host
microcontroller to read error register.
ꢂꢉ
ꢂꢂ
NERR
O
ꢂꢁ
ꢂꢄ
ꢂꢈ
ꢂꢀ
ꢂꢊ
ꢂꢆ
ꢂꢃ
ꢂꢇ
ꢁꢉ
ꢁꢂ
ꢁꢁ
ꢁꢄ
ꢁꢈ
ꢁꢀ
ꢁꢊ
ꢁꢆ
ꢁꢃ
ꢁꢇ
ꢄꢉ
ꢄꢂ
ꢄꢁ
ꢄꢄ
ꢄꢈ
NCLIP
I/O
O
I
Clipping indicator output (default) or PWM synchronization I/O
IꢁS/TDM digital audio data output
IꢁS_DO
IꢁS_WC
IꢁS_SCK
IꢁS_DI
IꢁC_SDA
IꢁC_SCL
NMUTE
ENABLE
FBꢂB
IꢁS/TDM digital audio word clock
I
IꢁS/TDM digital audio bit clock
I
IꢁS/TDM digital audio data input
I/O
I/O
I
IꢁC bus serial clock
IꢁC bus serial data
Mutes audio output when pulled low
I
Enables device when pulled high. Pulling this pin low shuts down the device.
Output channel ꢂB post‑ferrite feedback
Negative side flying capacitor for channel ꢂB
Audio output channel ꢂB
I
VFCꢂBN
OUTꢂB
VFCꢂBP
PVDD
P
O
P
P
P
P
O
P
I
Positive side flying capacitor for channel ꢂB
Power supply for power stage
PVDD
Power supply for power stage
VFCꢂAP
OUTꢂA
VFCꢂAN
FBꢂA
Positive side flying capacitor for channel ꢂA
Audio output channel ꢂA
Negative side flying capacitor for channel ꢂA
Output channel ꢂa post‑ferrite feedback
Auxiliary ADC input
ADC_IN
VDD_IO
AVSS
I
P
P
I
Digital I/O supply. Used for external resistor pull‑ups, e.g. for IꢁC bus.
Ground for internal analog circuitry
MSEL
Hardware select for BTL (pull high) or PBTL (pull low)
IꢁC bus address pin ꢂ. Use IꢁC_ADꢂ and IꢁC_ADꢉ to set IꢁC address: ꢉꢉ:ꢉxꢁꢉ,
ꢉꢂ:ꢉxꢁꢂ, ꢂꢉ:ꢉxꢁꢁ, ꢂꢂ:ꢉxꢁꢄ.
ꢄꢀ
ꢄꢊ
ꢄꢆ
IꢁC_ADꢂ
IꢁC_ADꢉ
CD_DIG
I
I
IꢁC bus address pin ꢉ
Internal digital core supply charge‑pump. Connect ꢂ μF between this pin and
DVDD_REG.
P
ꢄꢃ
ꢄꢇ
DVDD_REG
AVDD_REG
VDD
P
P
P
P
Internal regulated supply decoupling. Connect ꢂ μF between this pin and ground.
Internal regulated supply decoupling. Connect ꢂ μF between this pin and ground.
External low voltage supply.
ꢈꢉ
EPAD
VSS
Ground for internal digital circuitry and PVDD
Datasheet
page ꢊ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢅ Specifications
ꢀꢅ.ꢀ Absolute Maximum Ratings
NOTE: Usage outside the specifications stated in this table may cause permanent damage to the device and/or compromise
reliability.
Table ꢂ: Absolute Maximum Ratings
Parameter
VDD
Description
Min
‑ꢉ.ꢄ
‑ꢉ.ꢄ
‑ꢉ.ꢄ
‑ꢉ.ꢄ
Max
ꢀ.ꢀ
Unit
Low voltage supply
V
V
V
V
PVDD
Power amp supply
ꢁꢁ
VDD_IO
Vspeak
Digital I/O supply
ꢀ.ꢀ
Speaker node output pins
PVDD+ꢁ
IO and hardware setting pins (NERR, NCLIP, IꢁS_DO, IꢁS_WC, IꢁS_SCK,
IꢁS_DI, IꢁC_SDA, IꢁC_SCL, NMUTE, ENABLE, MSEL, IꢁC_ADꢉ, IꢁC_ADꢂ)
ADC_IN pin
VPIO
‑ꢉ.ꢄ
VDD_IO
V
VADC
TAMB
TJ
‑ꢉ.ꢄ
ꢂ.ꢀ
ꢃꢀ
V
Ambient operating temperature
‑ꢁꢀ.ꢉ
‑ꢁꢀ.ꢉ
‑ꢀꢀ.ꢉ
°C
°C
°C
Junction temperature
ꢂꢀꢉ
ꢂꢀꢉ
TSTORE
Storage temperature
ꢀꢅ.ꢁ ESD and Thermal Characteristics
Table ꢃ: ESD and Thermal Characteristics
Parameter
VESD,HB
Description
Min
‑ꢄꢉꢉꢉ
‑ꢂꢉꢉꢉ
Typ
Max
+ꢄꢉꢉꢉ
+ꢂꢉꢉꢉ
Unit
ESD Human Body Model
V
V
VESD,CD
ESD Charged Device Model
Thermal resistance, Junction‑to‑Ambient, ꢈ‑layer PCB
(EVAL_MAꢁꢄxx)
TθJA
TθJC
ꢁꢃ.ꢇ
ꢂ.ꢇ
°C/W
°C/W
Thermal resistance, Junction‑to‑Case (EPAD)
ꢀꢅ.ꢂ Recommended Operating Conditions
NOTE:Usageoutsidetherecommendedoperatingconditionsstatedinthistablemaycausethedevicetonotbehaveproperly.
This can lead to interrupted audio playback, protection features being triggered etc. This applies to DC+AC values outside the
min/max values.
Table ꢄ: Recommended Operating Conditions
Parameter
VDD
Description
Min
ꢂ.ꢊꢁ
ꢂꢉ.ꢉ
ꢂ.ꢊꢁ
Typ
ꢂ.ꢃ
ꢂꢃ
Max
ꢄ.ꢊꢀ
ꢁꢉ
Unit
Low voltage supply (DC+AC ripple)
Power amp supply (DC+AC ripple)
Digital I/O supply (DC+AC ripple)
Minimum required equivalent load inductance per output pin
for short circuit protection
V
V
V
PVDD
VDD_IO
ꢂ.ꢃ
ꢄ.ꢊꢀ
ILEQ
ꢉ.ꢀ
μH
Refer to sections ꢂꢂ.ꢀ and ꢂꢂ.ꢀ.ꢈ for more details on supply voltages and their protection mechanisms.
Datasheet
page ꢆ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢅ.ꢃ Electrical Characteristics
Conditions (unless specified otherwise): PVDD=ꢂꢃ V, VDD/VDD_IO=ꢄ.ꢄ V, Power Mode Profile: LPC, TAMB=ꢁꢀ °C, Load: ꢈ ohm +
ꢁꢁ μH, PCB: EVAL_AUDIO_MAꢁꢄxx (no output filter)
Table ꢇ: Electrical characteristics.
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
BTL Output Power
Load=ꢈΩ+ꢁꢁμH, sig=pink noise,
CF=ꢇdB; Thermal Warning
triggered
ꢂ
PCOUT,BTL
Continuous Output Power p/ch
ꢂꢁ
W
Load=ꢈΩ+ꢁꢁμH, sig=pink noise,
CF=ꢇdB, Thermal Error triggered
(device shuts down)
ꢂꢈ
W
Load=ꢃΩ+ꢁꢁμH, sig=ꢂ kHz sine,
THD+N=ꢂ%
ꢂꢆ
ꢁꢉ
ꢄꢉ
ꢄꢆ
ꢊꢉ
W
W
W
W
Load=ꢃΩ+ꢁꢁμH, sig=ꢂ kHz sine,
THD+N=ꢂꢉ%
Load=ꢈΩ+ꢁꢁμH, sig=ꢂ kHz sine,
THD+N=ꢂ%
ꢂ
PRMSOUT,BTL
RMS Output Power p/ch
Load=ꢈΩ+ꢁꢁμH, sig=ꢂ kHz sine,
THD+N=ꢂꢉ%
Instantaneous Peak Output
Load=ꢈΩ+ꢁꢁμH, sig=ꢂ kHz sine,
THD+N=ꢂ%
PIPOUT,BTL
IOUT,BTL
W
A
ꢂ
Power p/ch
ꢂ
Maximum Output Current p/ch
Case temperature on board at
ꢊ
PCB=EVAL_AUDIO_MAꢁꢄxx,
TCASE,BTL
’Continuous Output Power p/ch’
PBTL Output Power
ꢂꢂꢄ
°C
ꢁ
Load=ꢈΩ+ꢁꢁμH
Load=ꢈΩ+ꢁꢁμH, sig=pink noise,
CF=ꢇdB, Thermal Warning
triggered
ꢂ
PCOUT,PBTL
Continuous Output Power p/ch
ꢁꢈ
W
Load=ꢈΩ+ꢁꢁμH, sig=pink noise,
CF=ꢇdB, Thermal Error triggered
(device shuts down)
ꢁꢃ
W
Load=ꢁΩ+ꢁꢁμH, sig=ꢂkHz sine,
THD+N=ꢂ%
ꢂ
PRMSOUT,PBTL RMS Output Power p/ch
ꢊꢉ
W
Load=ꢁΩ+ꢁꢁμH, sig=ꢂkHz sine,
THD+N=ꢂꢉ%
ꢆꢈ
W
Instantaneous Peak Output
Load=ꢁΩ+ꢁꢁμH, sig=ꢂkHz sine,
THD+N=ꢂ%
PIPOUT,PBTL
IOUT,PBTL
TCASE,PBTL
Power stage
ꢂꢁꢉ
W
A
ꢂ
Power p/ch
ꢂ
Maximum Output Current p/ch
Case temperature on board at
ꢂꢁ
PCB=EVAL_AUDIO_MAꢁꢄxx,
ꢆꢃ
°C
ꢁ
’Continuous Output Power p/ch’
Load=ꢁΩ+ꢁꢁμH
POUT=ꢁxꢂꢉꢉmW,
ꢁ
η
Eꢅiciency (BTL)
ꢀꢆ
%
BTL
Load=ꢃΩ+ꢁꢁμH
POUT=ꢁxꢂW, Load=ꢃΩ+ꢁꢁμH
POUT=full scale, Load=ꢃΩ+ꢁꢁμH
POUT=ꢁxꢂꢉꢉmW,
ꢆꢇ
ꢇꢉ
%
%
ꢀꢈ
%
Load=ꢈΩ+ꢁꢁμH
POUT=ꢁxꢂW, Load=ꢈΩ+ꢁꢁμH
POUT=full scale, Load=ꢈΩ+ꢁꢁμH
BTL on‑resistance: ꢈx MOSFETS
in series + bond wires
ꢆꢄ
ꢃꢈ
%
%
Total on‑resistance of the
RON,BTL
ꢈꢉꢉ
mΩ
mΩ
ꢂ
internal power stage (BTL)
Total on‑resistance of the
PBTL on‑resistance: ꢁx BTL
power stages in parallel
LPC mode, low signal level
LPC mode, high signal level
RON,PBTL
fSW,FET
ꢁꢉꢉ
ꢂ
internal power stage (PBTL)
ꢂ
Internal MOSFET switching
ꢂꢁꢃ
ꢁꢀꢊ
kHz
kHz
frequency
Datasheet
page ꢃ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
HAP mode
ꢁꢀꢊ
ꢀꢂꢁ
kHz
kHz
kHz
kHz
ꢂ
fSW,LOAD
Switching frequency seen
diꢅerentially by the load
LPC mode, low signal level
LPC mode, high signal level
HAP mode
ꢂꢉꢁꢈ
ꢂꢉꢁꢈ
Power Consumption
Total idle power consumption for
PIDLE
PVDD=ꢂꢃV, LPC mode
ꢀꢁ
mW
ꢂ
VDD+PVDD+VDD_IO
(device enabled and unmuted)
PVDD=ꢂꢃV, HAP mode
PVDD=ꢂꢃV, LPC mode
PVDD=ꢂꢃV, HAP mode
VDD=ꢄ.ꢄ V, LPC mode
VDD=ꢂ.ꢃ V, LPCmode
VDD=ꢄ.ꢄ V, HAP mode
VDD=ꢂ.ꢃ V, HAP mode
VDD_IO = ꢄ.ꢄ V, No load on
IꢁS_DO
ꢆꢉ
ꢁ.ꢁ
ꢄ.ꢁ
ꢄ.ꢀ
ꢄ.ꢀ
ꢄ.ꢊ
ꢄ.ꢊ
mW
mA
mA
mA
mA
mA
mA
ꢂ
IPVDD,IDLE
Quiescent/idle current, PVDD
(device enabled and unmuted)
ꢂ
IVDD,IDLE
Quiescent/idle current, VDD
(device enabled and unmuted)
Quiescent/idle current, VDD_IO
Total power consumption in
ꢂ
IVDD_IO,IDLE
ꢁ.ꢄ
μA
VDD_IO = ꢂ.ꢃ V, No load on
IꢁS_DO
ꢁ.ꢄ
μA
PIDLE,STANDBY standby mode for
VDD+PVDD+VDD_IO
PVDD=ꢂꢃV, VDD=ꢂ.ꢃV
ꢁ.ꢃ
mW
ꢂ
PVDD=ꢂꢃV, VDD=ꢄ.ꢄV
ꢈ.ꢆ
mW
Audio Performance/IO
ꢁꢉ‑ꢁꢉkHz integrated noise,
A‑weighted, LPC mode
VNOISE
Output integrated noise level
ꢃꢁ
μV
ꢁꢉ‑ꢁꢉkHz integrated noise,
A‑weighted, HAP mode
ꢀꢁ
μV
DNR
Dynamic Range
‑ꢊꢉdBFS method, LPC mode
‑ꢊꢉdBFS method, HAP mode
ꢂꢉꢁ
ꢂꢉꢊ
dB
dB
Total Harmonic Distortion +
THD+N
POUT=ꢀW, sig=ꢂkHz, Load=ꢈΩ
ꢉ.ꢉꢀ
%
ꢂ
Noise
Output oꢅset voltage for low
pop/click‑noise
VOS
‑ꢁꢀ
‑/+ ꢄ
ꢁꢀ
mV
ꢄꢁ
ꢈꢈ.ꢂ
ꢈꢃ
Supported IꢁS/TDM input
fS
ꢃꢃ.ꢁ
ꢇꢊ
kHz
ꢂ
sampling rates
ꢂꢆꢊ.ꢈ
ꢂꢇꢊ
Propagation delay from audio
Sample rate = ꢈꢃ kHz, DSP
enabled running ROM code
tPD
ꢂꢈꢊ
ꢁꢀ
ꢂꢊ
ꢁ
μs
ꢂ
input to amplifier
Maximum supported bit clock on
IꢁS_SCKMAX
MHz
ꢂ
IꢁS_SCK pin
Maximum supported input
NCH,MAX,IN
ꢂ
IꢁS/TDM channels
Maximum supported output
NCH,MAX,OUT
G
ꢂ
IꢁS/TDM channels
ꢂ
Amplifier gain in dB (Vrms/FS)
pvdd_scale=ꢂꢂ, PVDD=ꢂꢃ V
pvdd_scale=ꢂꢉ, PVDD=ꢂꢀ V
pvdd_scale=ꢉꢂ, PVDD=ꢂꢁ V
pvdd_scale=ꢉꢉ, PVDD=ꢂꢉ V
ꢁꢁ.ꢀ
ꢁꢂ.ꢁ
ꢂꢇ
dB
dB
dB
dB
ꢂꢊ.ꢀ
Enable/Mute
Time from ENABLE=high until
TENABLE
ꢂꢀ
ms
ꢂ
ready for IꢁC communication
Unmute time delay until audio
TUNMUTE
ꢄꢉ
ms
ꢂ
output
Datasheet
page ꢇ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
IꢁC serial control interface
ꢂ
fSCL
IꢁC clock frequency
Standard Mode
Fast Mode
ꢂꢉꢉ
ꢈꢉꢉ
ꢄꢉ
kHz
kHz
%
ꢂ
VIL
Logic low voltage
Percentage of VDD_IO voltage
Percentage of VDD_IO voltage
Standard Mode
Standard Mode
Standard Mode
Standard Mode
Standard Mode
Standard Mode
Standard Mode
Fast Mode
ꢂ
VIH
Logic high voltage
ꢆꢉ
%
ꢂ
tr
SDA and SCL rise time
ꢂꢉꢉꢉ
ꢄꢉꢉ
ns
ꢂ
tf
SDA and SCL fall time
ns
ꢂ
tHIGH
tLOW
SCL clock high
ꢈ
ꢈ.ꢆ
ꢁꢀꢉ
ꢀ
μs
ꢂ
SCL clock low
μs
ꢂ
tSU;DAT
tHD;DAT
tBUF
Data, setup
ns
ꢂ
Data, hold
ns
ꢂ
Min. stop to start condition
ꢈ.ꢆ
ꢂ
μs
ꢂ
RPU,FM
RPU,SM
Protection
Pull‑up resistor for SDA/SCL
ꢈ.ꢆ
ꢀ.ꢊ
kΩ
kΩ
ꢂ
Pull‑up resistor for SDA/SCL
Standard Mode
ꢂ
PVDD undervoltage lock‑out
threshold (IꢁC interface
functional)
UVLOPVDD
ꢊ.ꢀ
V
PVDD over‑voltage error
threshold
OVPPVDD
PVDD rising
ꢁꢂ.ꢀ
V
PVDD falling while OVP error
triggered
OVPPVDD,CLR PVDD over‑voltage error clear
ꢁꢉ
V
OTETRIG
OTECLR
Over‑temperature error trigger
Over‑temperature error clear
Over‑temperature warning
trigger
Temperature rising
Temperature falling
ꢂꢈꢀ
ꢂꢈꢉ
°C
°C
OTWTRIG
OTWCLR
Temperature rising
Temperature falling
ꢂꢂꢀ
ꢂꢂꢉ
°C
°C
Over‑temperature warning clear
ꢂ
ꢁ
Guaranteed by design simulation.
Measured on EVAL_MAꢁꢄꢉꢈ evaluation kit PCB. Parameter may depend on application/layout/board stackup etc.
Datasheet
page ꢂꢉ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢀ Functional description
PVDD
Switching waveform
Fullscale sine output
ꢀꢀ.ꢀ MERUS™ Multilevel Switching
PVDD/2
0
MERUS™ multilevel switching features several benefits in
class D audio amplification compared to conventional ꢁ‑
level switching:
-PVDD/2
-PVDD
• Ultra low power consumption
• Unmatched power eꢅiciency
• Low electromagnetic emission
• Reduced system cost
Time (zoom in)
Switching waveform
PVDD
PVDD/2
0
-8 dB sine output
This chapter aims to explain these benefits in more detail.
ꢀꢀ.ꢀ.ꢀ Multilevel Topology
The integrated power stage of the MAꢁꢄꢉꢈPNS is a MERUS™
multilevel switching topology. It consists of two half‑
bridges with each four power MOSFETs and a flying capac‑
itor. An intermediate voltage supply is generated over the
flyingcapacitor’sterminals, which togetherwiththeswitch‑
ing scheme of the MOSFETs result in a ꢁ‑phase PWM output
with three voltage levels (ꢉV, ½PVDD and PVDD) rather than
the conventional two. This doubles the eꢅective switching
frequency seen at the PWM output.
-PVDD/2
-PVDD
Time (zoom in)
PVDD
PVDD/2
0
Switching waveform
Idle output (noise)
PVDD
PVDD
M1
M1
M2
M2
-PVDD/2
-PVDD
M3
M4
M3
M4
Time (zoom in)
Figure ꢀꢀ.ꢀ: BTL/PBTL configuration of two ꢄ‑level half
PVDD
PVDD/2
0
Switching waveform
bridges
Fullscale music output
In MAꢁꢄꢉꢈPNS, two half‑bridges are combined in a
BTL/PBTL configuration (Figure ꢂꢂ.ꢂ) with a relative phase
shiꢋ of ꢁꢆꢉ°achieving a ꢀ‑level switching scheme across
the load, eꢅectively quadrupling the switching frequency
seen at the load. This allows the internal MOSFETs to
be driven with lower switching frequency, thus reducing
power losses related to switching. Switching waveforms
are shown in Figure ꢂꢂ.ꢁ.
-PVDD/2
-PVDD
Time (zoom out)
Figure ꢀꢀ.ꢁ: Multilevel switching with various signals.
ꢀꢀ.ꢀ.ꢁ Reduced Inductor Ripple Current
The multilevel topology reduces the voltage magnitude
over the output filter inductor during switching, which in
turnreducestheripplecurrentandrelaxesfilterinductorre‑
quirements. At idle operation where the output signal level
is low, the MOSFETs are switched at ꢀꢉ % duty cycle, re‑
sulting in near‑zero ripple current. Hysteresis losses in the
inductor core material are therefore also greatly reduced
which improves overall power eꢅiciency. From Figure ꢂꢂ.ꢄ
itisclearthatꢀ‑levelswitchingprovidesgreatlyreducedrip‑
ple current over the entire duty cycle range compared to
conventional ꢁ‑level switching. In fact, it is not even nec‑
essary to use a standard LC filter for electromagnetic inter‑
Datasheet
page ꢂꢂ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Efficiency VS output power percentage
ference (EMI) suppression. The MAꢁꢄꢉꢈPNS can even oper‑
100
ate with a simple ferrite filter reducing both application cost
and size. See Section ꢂꢂ.ꢂ.ꢈ and ꢂꢁ for more information.
90
80
70
60
50
40
30
20
10
1
0.9
0.8
0.7
0.6
Traditional class D
3-level
5-level
0.5
0.4
0.3
0.2
0.1
0
MERUS multilevel
Traditional class D
Realistic Pavg limit for music
0.5
5
20
50
100
Sinusoid output power percentage [%]
Figure ꢀꢀ.ꢃ: MERUS™ multilevel modulation eꢅiciency
compared to traditional ꢁ‑level modulation
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output PWM duty cycle
Figure ꢀꢀ.ꢂ: Ripple current comparison
1
for multilevel compared to traditional class D. In addition,
MAꢁꢄꢉꢈPNS makes it possible to address EMC issues from
a soꢋware perspective with its PWM synchronization fea‑
ture as well as configurable switching edge steepness (slew
rate), all to reduce EMI in applications with many devices,
e.g. multi‑channel amplifiers.
ꢀꢀ.ꢀ.ꢂ Ultra Low Power Consumption with Music
MAꢁꢄꢉꢈPNS exhibits ultra low power consumption at low
and mid output power, which is ensured by low MOSFET
switching frequency, smaller voltage transitions when
switching and near zero‑ripple current. The low idle power
consumption can make battery‑powered applications last
significantly longer or reduce the amount of battery cells
required for a particular application.
ꢀꢀ.ꢀ.ꢄ Power Mode Profiles (PMP)
The MAꢁꢄꢉꢈPNS features two selectable power mode pro‑
files (PMP):
• Low Power Consumption (LPC) Mode
• High Audio Performance (HAP) Mode
Because of the low power consumption at lower output
power levels, the MAꢁꢄꢉꢈPNS is ideal for real applications
with dynamic signals like music/noise that exhibit a high
signal peak‑to‑RMS ratio (crest factor). Power eꢅiciency can
be as high as ꢃꢉ % at ꢂ W output power per channel, and be‑
cause of the low power losses MAꢁꢄꢉꢈPNS may run without
external heatsink in most applications. Figure ꢂꢂ.ꢈ shows
the diꢅerence in power eꢅiciency between multilevel and
traditional class D. From the figure it is clear that multilevel
operation yields superior results for lower playback levels,
which is the normal usage in common speaker products.
LPC mode keeps eꢅiciency as high as possible and mini‑
mizes idle losses by using a lower switching frequency for
low output levels. HAP mode improves noise by using a
higher switching frequency and therefore achieves a feed‑
back loop with higher bandwidth. Switching frequency is
dynamic for LPC mode and varies with output power with
no audible artifacts. Table ꢆ shows the general properties
of the two modes.
Table ꢆ: Power Mode Profiles
*PVDD=ꢂꢃ V, VDD/VDD_IO=ꢂ.ꢃ V, BTL, Load=ꢃ Ω+ꢁꢁ μH,
PCB=EVAL_AUDIO_MAꢁꢄxx
ꢀꢀ.ꢀ.ꢃ EMI Reduction
Parameter
LPC
HAP
Complying with EMC regulations is a typical challenge with
classDamplifiersduetothehighpowersquarewaveoutput
waveform. Traditional class D amplifiers have maximum
current ripple in the output filter inductor at ꢀꢉ % duty cycle
(idle operation) which gives rise to high amount of common
mode frequency content. However, MERUS™ multilevel op‑
eration exhibits minimal switching at idle which ensures
minimal common mode emission at idle operation. The
diꢅerential mode content at higher playback levels, when
switching activity is stronger, is also significantly reduced
as the transition between voltage levels is relatively small
Idle consumption*
Eꢅiciency ꢉ.ꢂ W*
Eꢅiciency ꢂ W*
Eꢅiciency ꢂꢉ W*
FET switch. freq.
ꢀꢁ mW
ꢀꢆ %
ꢆꢉ mW
ꢈꢆ %
ꢆꢇ %
ꢆꢇ %
ꢇꢄ %
ꢇꢄ %
ꢂꢁꢃ‑ꢁꢀꢊ kHz
ꢁꢀꢊ kHz
ꢂꢉꢁꢈ kHz
ꢉ.ꢉꢀ %
ꢀꢁ μV
Switch. freq. atload. ꢀꢂꢁ‑ꢂꢉꢁꢈ kHz
THD+N, ꢂ kHz, ꢀ W
Noise, A‑weighted
Dynamic Range
ꢉ.ꢉꢀ %
ꢃꢁ μV
ꢂꢉꢁ dB
ꢂꢉꢊ dB
Datasheet
page ꢂꢁ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢀ.ꢁ Modes of Operation
ꢂꢂ.ꢀ and ꢂꢂ.ꢊ for configuration diagrams.
ꢀꢀ.ꢁ.ꢀ Normal Operation / Shutdown (ENABLE pin)
PBTL mode dynamically enables the second output based
on the signal level so that idle power consumption can be
as low as possible when high output power is not needed.
The ENABLE pin (ꢁꢉ) controls the shutdown state of
MAꢁꢄꢉꢈPNS. When ENABLE is low, the device is in shutdown
mode. When ENABLE becomes high, the device exits shut‑
down state, boots up and enters normal operation. Refer to
specifications for ENABLE timing.
VDD_IO
FB0A
OUT0A
CH1
MSEL
Audio source
ꢀꢀ.ꢁ.ꢁ Mute / Unmute (NMUTE pin)
I2S_DI
I2S/TDM Data
(CH1,CH2)
NMUTE (ꢂꢇ) controls muting of the amplifier output and is
an active‑low pin, i.e. if NMUTE=high the output will be un‑
muted. Muting is instantaneous, but unmuting is a timed
function with a delay (refer to NMUTE timing)
FB0B
OUT0B
FB1A
I2S_SCK
I2S_WS
BITCLOCK
WORDCLOCK
OUT1A
CH2
Muting can also be performed with the mute_chꢉ/ꢂ register
for individual channels. Use mute_source to choose the
source of muting: NMUTE pin or register setting.
FB1B
OUT1B
In muted state, no audio content is present at the amplifier
output, but there will be some switching activity to balance
and pre‑charge the flying capacitors. If no switching activity
is desired the individual amplifier channels can be disabled
with the disable_chꢉ/ꢂ registers.
Figure ꢀꢀ.ꢄ: Bridge Tied Load (BTL) configuration
FB0A
ꢀꢀ.ꢁ.ꢂ Standby
OUT0A
CH1
MSEL
The device can be put in standby mode for lowest possible
power consumption while still maintaining a functional IꢁC
interface(towakethedeviceatalaterpoint). Standbymode
is controlled with the standby register.
Audio source
I2S_DI
I2S/TDM Data
(CH1,dummy)
FB0B
OUT0B
FB1A
I2S_SCK
I2S_WS
BITCLOCK
WORDCLOCK
ꢀꢀ.ꢂ BTL/PBTL Output Configurations
The amplifier output can be configured to operate in
• Bridge Tied Load (BTL)
OUT1A
FB1B
• Parallel Bridge Tied Load (PBTL)
OUT1B
Figure ꢀꢀ.ꢇ: Bridge Tied Load (PBTL) configuration. Note:
It is also possible to connect output pins A and B before the
ferrite filter in order to use two ferrites in total instead of
four.
Table ꢈ: BTL/PTBL properties
Parameter
PBTL
ꢂꢁ A
BTL
Min. current limit
Recommended load
MSEL pin tie‑oꢅ
ꢊ A
ꢁ‑ꢈ Ω
Ground
ꢈ‑ꢃ Ω
VDD_IO
The MSEL pin (ꢄꢈ) controls the output configuration and
must be set before the device powers up (when ENABLE=ꢂ).
Alternatively, the mode_pbtl register can be used to con‑
figure the output aꢋer the device has powered up. The
TBD_reg_ctrl register must also be set for the mode_pbtl
register to take eꢅect and override the hardware setting of
the MSEL pin.
ꢀꢀ.ꢃ Gain Configuration
MAꢁꢄꢉꢈPNS oꢅers diꢅerent gain configurations for match‑
ing full scale output with the desired PVDD voltage in an ap‑
plication. The gain is controlled with the pvdd_scale reg‑
ister. Reducing the amplifier gain to a lower value also re‑
duces output noise. Gain frequency response is shown in
Figure ꢂꢄ.ꢁꢃ. Changing gain settings while the power stage
is unmuted can result in significant pop/click and should be
avoided. The table below shows the recommended pvdd
scale setting for each diꢅerent typical PVDD supply level.
For a complete usable PVDD range in each pvdd scale set‑
ting refer to Figure ꢂꢄ.ꢄꢉ . Setting ꢂꢂ and ꢂꢉ can be used
BTL is best suited for standard current, two‑channel ap‑
plications, e.g. stereo speaker pairs and ꢁ‑way systems.
PTBL is a ꢂ‑channel configuration but with twice the output
power/current capability, which can be useful for sub‑
woofers and/or low impedance speakers. Refer to Figure
Datasheet
page ꢂꢄ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
from ꢂꢉV to ꢂꢃV, setting ꢉꢂ can be used from ꢂꢉV to ꢂꢊV and
setting ꢉꢉ can be used from ꢂꢉV to ꢂꢀV.
• errVect_acc.errVector_all__ꢉ (accumulated/sticky)
Individual channel errors:
• DC error
• Flying capacitor error
• Over‑current error
Table ꢉ: Gain options for recommended (guideline) PVDD
voltages.
pvdd_scale
Recommended PVDD
ꢉꢉ
ꢂꢉ V
ꢂꢁ V
ꢂꢀ V
ꢂꢃ V
ꢉꢂ
ꢂꢉ
The errors above can be read as individual bits in the follow‑
ing registers:
ꢂꢂ (default)
For additional noise characteristics as a function of gain
and PVDD, please see Figure ꢂꢄ.ꢁꢇ and ꢂꢄ.ꢄꢉ.
• errVect_acc.errVector_chꢉ (Channel ꢉ accumulated /
sticky errors)
Note that the power stage cannot operate at full scale above
ꢁꢉ kHz. HAP mode is preferred if out‑of‑band operation is
desired as its bandwidth is greater than LPC mode.
• errVect_acc.errVector_chꢂ (Channel ꢂ accumulated /
sticky errors)
Clearing errors
Errors can be cleared by toggling the reg.errTrig_reset
register from ꢉ to ꢂ and then back to ꢉ.
ꢀꢀ.ꢄ Protection
MAꢁꢄꢉꢈPNS oꢅers a range of protection features to avoid
damage to the device itself or attached speakers.
Error handling:
It is generally recommended to use to accumulated error
registers for error detection and handling. Normal error
handling procedure:
ꢀꢀ.ꢄ.ꢀ Errors and Error Handling (NERR pin)
The protection system in MAꢁꢄꢉꢈPNS monitors a range of
parameters to check if min/max thresholds are exceeded.
Exceeding the thresholds will trigger an error event in the
protection system and the NERR pin (pin ꢂꢂ) will change
from high to low. The NERR pin will only report errors
correctly aꢋer the first PLL lock which requires clocks
present on IꢁS_SCK and IꢁS_WC pins.
• Disregard errors during start‑up of the device defined
by TENABLE
.
• Clear errors immediately aꢋer start‑up.
• Monitor accumulated error registers (general + chan‑
nel) and take appropriate action if an error occurs.
The NERR pin can be used as an interrupt flag for an
external host control device, e.g. a system microcontroller.
Alternatively, the err_pin register can be used to monitor
the NERR pin as well. Once an error has been detected
by the host, the error type can be identified by reading
the error registers. Connect a ꢀꢂ kΩ resistor from NERR to
VDD_IO.
• Clear error register(s) aꢋer action has been taken to
again monitor for new errors.
VDD_IO
51 kΩ
51 kΩ
MCU/HOST
General device errors:
• Low temperature warning
• IꢁS input error
NERR
NCLIP
Figure ꢀꢀ.ꢆ: NERR/NCLIP schematic
• PLL error
• PVDD over‑voltage
• PVDD under‑voltage
• Over‑temperature error
• Over‑temperature warning
ꢀꢀ.ꢄ.ꢁ Output DC Protection (DCP)
The amplifier output can detect if a DC voltage is present
at the output terminals. If the output voltage stays above
the DCP threshold for too long, corresponding to a ꢂ Hz si‑
nusoid, the power stage will shut down, a DC error will be
reported to the channel error register and the power stage
will attempt to restart and resume operation. Each output
channel is monitored separately.
The errors above can be read as individual bits in the follow‑
ing registers:
• errVect_now.errVector_all__ꢉ (instantaneous)
Datasheet
page ꢂꢈ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢀ.ꢄ.ꢂ Over‑Current Protection (OCP)
ꢀꢀ.ꢄ.ꢄ Over Temperature Protection (OTP)
Over‑current (OC) events can be triggered by e.g. driving
low impedance loads with high PVDD and shorting speaker
terminals to each other or to ground. The current flowing in
each internal MOSFET in the output stage is monitored. If
the threshold is exceeded (refer to BTL threshold and PBTL
threshold) the power stage will shut down, an OCP error will
be reported to the error register and the power stage will at‑
tempt to restart and resume operation.
An internal temperature sensor eꢅectively safeguards the
device against a thermally induced failure due to overload‑
ing and/or insuꢅicient cooling. A high die temperature ini‑
tially causes an Over Temperature Warning (OTW). During
an OTW event, the device will continue to operate normally
but if the temperature rises further, the device will reach
Over Temperature Error (OTE). An OTE event will cause
the device to stop all output switching activity in order to
avoid permanent damage. The device will resume switch‑
ing when the temperature has dropped suꢅiciently. Both
OTW and OTE will report to the NERR pin and the error reg‑
isters. Refer to specifications for OTE and OTW trigger and
clear temperatures.
ꢀꢀ.ꢄ.ꢃ PVDD Over/Under‑Voltage Protection
PVDD features over‑voltage (OVP) and under‑voltage (UVP)
protection as well as under‑voltage lockout (UVLO). Thresh‑
old voltages can be found in specifications. Refer to Figure
ꢂꢂ.ꢃ for an overview of the voltage protection on PVDD.
ꢀꢀ.ꢄ.ꢇ PLL Error and IꢁS Input Error
PVDD voltage range
Functionality
PLL error will occur in case of lost clock signals on the
IꢁS_SCK and IꢁS_WC. The MAꢁꢄꢉꢈPNS relies on these clock
signals to operate properly and if they are not present or
faulty, the core will come to a halt state, reporting to the er‑
rorsystemthatthePLLisnotlocked. Whentheclocksignals
return, operation is resumed. In the event of bad audio in‑
put an error will also be reported to the error register on a
separate bit.
Above absolute maximum
OVP area
Device breakdown
Output muted
Recommended operating
conditions
Normal
operation
UVP area
Output muted
Device in reset
Figure ꢀꢀ.ꢈ: PVDD voltage protection overview
UVLO area
ꢀꢀ.ꢄ.ꢆ Flying Capacitor Over/Under‑Voltage Protec‑
tion
The flying capacitors connected to the VFCxxx pins are
essential for MERUS™ multilevel switching to function
properly. During normal operation an internal voltage
balancing circuit will generate a virtual PVDD/ꢁ supply
across the external flying capacitor. To protect the internal
MOSFETs against permanent damage the MAꢁꢄꢉꢈPNS
features over/under‑voltage protection (OVP/UVP) in case
of loop instability or flying capacitor balancing errors.
The flying capacitor voltage is monitored and OVP/UVP
is triggered if the voltage over the flying capacitors is
deviating too far from PVDD/ꢁ. In this event, the output
stage stops switching (output muted). When the flying
capacitor voltage has again been balanced the device starts
switching automatically (output unmuted).
OVP protects the MOSFETs in the output power stage
against permanent damage due to over‑voltage. If PVDD
voltage rises above OVPPVDD the power stage will stop
switching and the output will eꢅectively be muted (overrid‑
ing NMUTE pin). PVDD voltage must fall below OVPPVDD,CLR
voltage before the device exits muted state. OVP will not
protect the device against PVDD voltages rising above the
absolute maximum value.
UVP behaves similarly and also mutes the output (with‑
out audio artifacts) by stopping all switching in the output
power stageif PVDD voltage dropsbelow the recommended
operating conditions. In UVP state it is still possible to com‑
municate with the device but mute is sustained. UVP
should be considered a warning for low and/or unstable
PVDD.
Note that flying capacitor over/under‑voltage protection
will not trigger if the PVDD voltage is below ꢂꢄ V. The reason
is that the feature is designed to protect the internal MOS‑
FETs against over‑voltage conditions that could cause per‑
manent damage to the IC, and at lower PVDD voltages the
MOSFETs are no longer prone to this condition.
If PVDD is reduced further, falling below the UVLOPVDD
threshold, the deviceshutsdown. Power‑onresetisapplied
when raising PVDD above the rising threshold again. When
shut down, the device is not functional.
Datasheet
page ꢂꢀ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
VDD
OVP Vth
VDD
AVDD_REG
DVDD_REG
CD_DIG
1 µF
X5R/X7R
PVDD/2
Fly Cap voltage
3x
1 µF
X5R/X7R
UVP Vth
HIGH
VDD_IO
AVSS
MUTE
VDD_IO
1 µF
X5R/X7R
LOW
Figure ꢀꢀ.ꢉ: Flying capacitor protection behaviour
Figure ꢀꢀ.ꢀꢅ: Decoupling/supply capacitor schematic
with recommended specifications
ꢀꢀ.ꢄ.ꢈ NCLIP Pin
The NCLIP works as a clipping indicator and starts pulsing
from high to low at higher levels and becomes constant low
when near clipping. A system microcontroller can use this
pin as an indicator to decrease volume/gain if desired when
clipping occurs. Alternatively, the integrated DSP features
a configurable output limiter that can be used to prevent
clipping. Triggering NCLIP does not register as an error, but
the clip_pin register can be used monitor the state of NCLIP.
Connect a ꢀꢂ kΩ resistor from NCLIP to VDD_IO as shown in
Figure ꢂꢂ.ꢆ.
flying capacitor, with a positive and a negative ter‑
minal, VCFxxP and VCFxxN pins. The fly‑cap pins are
high power pins and care must be taken to reduce induc‑
tance/resistance in the PCB layout as the full output current
will flow through pins/caps. Keep the flying capacitors as
close to the device as possible with as short and wide PCB
traces as possible. Refer to Section ꢂꢁ for more information.
FB0A
OUT0A
VCF0AP
Flycap
ꢀꢀ.ꢇ Power Supplies
ꢀꢀ.ꢇ.ꢀ Supplies for Internal Analog/Digital Circuitry
(VDD/VDD_IO)
VCF0AN
FB0B
OUT0B
MAꢁꢄꢉꢈPNS generates its own internal analog/digital sup‑
plies from VDD with the use of external capacitors and the
AVDD_REG,DVDD_REGandCD_DIGpins. AVSSistheground
reference pin for the internal analog circuitry. MAꢁꢄꢉꢈPNS
is designed to work with common power supply voltages,
ꢂ.ꢃ V / ꢄ.ꢄ V, which are typically found in applications pow‑
ering the host device already. When VDD is power cycled,
theMAꢁꢄꢉꢈPNSregistersettingsareresettodefault. AllVDD
decoupling capacitors should be placed as close as possible
to the supply pins. The recommended capacitor specifica‑
tions are shown in Figure ꢂꢂ.ꢂꢉ.
Figure ꢀꢀ.ꢀꢀ: Flying capacitor schematic with
recommended specifications
When choosing flying capacitors, it is necessary to keep ca‑
pacitance derating vs. DC bias voltage in mind if multi‑
layer ceramic capacitors (MLCC) are used. The fly‑caps
are constantly charged to ½PVDD, which will derate the
expected capacitance. In general, high quality ꢂꢉ μF
ꢁꢀV XꢀR/XꢆR ꢉꢃꢉꢀ MLCCs are recommended (example:
CꢁꢉꢂꢁXꢀRꢂEꢂꢉꢊKꢂꢁꢀAB). The minimum eꢅective capaci‑
tance should be ꢈ.ꢉ μF at ½PVDD for correct operation.
VDD_IO is used for pull‑up resistors to I/O pins on the south
side of MAꢁꢄꢉꢈPNS (pins ꢂꢂ‑ꢂꢃ). These are NERR (ꢂꢂ),
NCLIP (ꢂꢁ), IꢁS_DO (ꢂꢄ), IꢁS_WC (ꢂꢈ), IꢁS_SCK (ꢂꢀ), IꢁS_DI
(ꢂꢊ), IꢁC_SDA (ꢂꢆ), IꢁC_SCL (ꢂꢃ), NMUTE (ꢂꢇ) and ENABLE
(ꢁꢉ). Note that the serial audio data output pin IꢁS_DO is
internally driven by the VDD_IO supply.
ꢀꢀ.ꢇ.ꢂ Power Stage Supply (PVDD)
PVDD supplies current to the output power stage to drive
the load. A bulk decoupling capacitor is recommended on
the PCB to keep the supply stable, e.g. aluminium elec‑
trolytic type capacitor. Capacitance value will depend on
the application (lowest playback frequency, ripple voltage
and maximum peak power requirements). In general, a ꢈꢆꢉ
μF aluminium electrolytic capacitor will be suꢅicient for
most applications.
For simplicity, VDD_IO and VDD can be tied to the same low
voltage supply in the application.
ꢀꢀ.ꢇ.ꢁ Flying Capacitors
The MAꢁꢄꢉꢈPNS power stage uses flying capacitors to
generate a ½PVDD supply voltage for multilevel operation.
Each output switch node pin OUTxx has a corresponding
Datasheet
page ꢂꢊ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
data line, making it ideal for multi‑channel applications
Capacitance
with multiple ICs.
100%
50%
By default, the internal audio receiver in MAꢁꢄꢉꢈPNS
will look for starting edge on the word clock and receive
packages based on the package slot size (also known as
frame width, see slot_size register), irrelevant of the frame
midpoint transition on the word clock. This means that
IꢁS (ꢁ‑channel) and TDM (multichannel) are processed
similarly by the receiver, the diꢅerence being the amount
of slot size packages received between two starting edges
of the word clock. For example, a ꢁ‑channel ꢄꢁ bit IꢁS audio
stream will have a ꢊꢈ bit audio frame cycle between word
clock starting edges, whereas a ꢈ‑channel ꢄꢁ bit TDM audio
stream will have ꢂꢁꢃ bit between starting edges (refer to
audio data configuration examples in Figures ꢂꢂ.ꢂꢀ and
ꢂꢂ.ꢂꢊ). In this way, MAꢁꢄꢉꢈPNS can automatically detect
if the format is ꢁ‑channel or multichannel (IꢁS/TDM) as
long as slot_size, data_size (bit depth), data_alignment,
sck_pol, ws_fs_rising and lsb_first registers are configured
to match for both the external transmitter (source) and the
MAꢁꢄꢉꢈPNS (sink).
Voltage
0%
0V
Figure ꢀꢀ.ꢀꢁ: Typical derating for multi‑layer ceramic
capacitors (MLCC) with diꢅerent package sizes
Todecouplefasttransitents, itcanbebeneficialtoplacetwo
low ESR capacitors with smaller capacitance value, e.g. ꢂ
μF and ꢂꢉ μF, close to the PVDD pins on each opposing side
of the MAꢁꢄꢉꢈPNS. Figure ꢂꢂ.ꢂꢄ shows the recommended
PVDD decoupling schematic.
Application
dependent
10 µF
1 µF
X5R/X7R X5R/X7R
5
6
26
PVDD
PVDD
PVDD
PVDD
Mirror
+
PVDD
25 PVDD caps
to this
To configure the input channel routing, refer to the
tdm_input_map register.
side also
Figure ꢀꢀ.ꢀꢂ: Typical derating for multi‑layer ceramic
capacitors (MLCC) with diꢅerent package sizes
ꢀꢀ.ꢈ.ꢁ Digital Serial Audio Output
MAꢁꢄꢉꢈPNS features a serial audio data output (pin ꢂꢄ:
IꢁS_DO) with the same audio format properties as the serial
audio input. To enable the audio output, the tx_enable
register must be enabled. By default (refer to ROM code),
the DSP output channels ꢂ and ꢁ (the signals received
by the amplifier) are routed to IꢁS_DO, but this can be
configured using the tdm_output_mapꢉ‑ꢂꢀ registers.
ꢀꢀ.ꢆ Clock System
MAꢁꢄꢉꢈPNS generates its own internal clock through a PLL
in the presence of a serial audio bit clock (IꢁS_SCK) and a
word clock (IꢁS_WC).
The frequency of the audio bit clock is auto‑detected and
clock frequencies up to ꢁꢈ.ꢀꢆꢊ MHz are supported. The au‑
dio bit clock frequency will depend on sampling frequency,
slot size (frame width) and the number of channels in the
audio stream according to Equation ꢂ.
ꢀꢀ.ꢈ.ꢂ Input‑to‑Output Audio Propagation Delay
MAꢁꢄꢉꢈPNS oꢅers a very low propagation delay from audio
input to amplified output, making it ideal for delay sensi‑
tive applications such as echo‑cancelling speaker phones
and conference equipment. Refer to specifications for more
info.
fSCK = fs · slot_size · NCH ≤ 24.576MHz
(ꢂ)
ꢀꢀ.ꢈ Audio Interface
ꢀꢀ.ꢈ.ꢀ Digital Serial Audio Input
ꢀꢀ.ꢉ Digital Signal Processor (DSP)
MAꢁꢄꢉꢈPNS has a single serial data audio input port that
consistsof the pins IꢁS_WC(wordclock), IꢁS_SCK (bitclock)
and IꢁS_DI (data in). The input port supports two‑channel
IꢁS and multi‑channel TDM audio formats with sampling
rates of ꢄꢁ, ꢈꢈ.ꢂ, ꢈꢃ, ꢃꢃ.ꢁ, ꢇꢊ, ꢂꢆꢊ.ꢈ and ꢂꢇꢁ kHz with data‑
words of ꢂꢊ, ꢁꢈ or ꢄꢁ bits in length. The format alignment
is configured in the data_alignment register. MAꢁꢄꢉꢈPNS is
always configured as an audio sink device (receiver). TDM
format is capable of up to ꢂꢊ audio channels on a single
ꢀꢀ.ꢉ.ꢀ ROM Code / Static Memory
The MAꢁꢄꢉꢈPNS contains ROM code (static memory) with a
preconfigured DSP program that includes volume control
and peak limiters. The ROM code is applied to the DSP by
default when MAꢁꢄꢉꢈPNS is reset.
Datasheet
page ꢂꢆ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
dsp_bypass*
MA2304
Power amps
CLK
Clock
system
tdm_input_map0-1*
OUT0
OUT1
2ch
I2S
input
SCK
Serial
2-16ch
16ch
DSP
audio
receiver
2ch
tdm_output_map0-15*
tx_loopback*
I2S/TDM
2ch
16ch
tx_enable*
I2S_DO
16ch
Serial audio
transmitter
2-16ch
I2S/TDM
*Refer to register map for description
Figure ꢀꢀ.ꢀꢃ: Audio routing
data_alignment
Two-channel audio data example
data_size
I2S delayed 1 bit
MSB
MSB
LSB
MSB
MSB
LSB
16 bit
24 bit
I2S
LJ
LSB
LSB
MSB
MSB
LSB
MSB
MSB
LSB
16 bit
24 bit
LSB
LSB
MSB
LSB
LSB
MSB
LSB
LSB
16 bit
24 bit
RJ
MSB
MSB
Le� channel / slot 0
Right channel / slot 1
slot_size: 32 bit
Audio frame: 64 bit (2 channels of 32 bit)
I2S_WC
Figure ꢀꢀ.ꢀꢄ: Audio data configuration/timing for two channels
ꢀꢀ.ꢉ.ꢁ Volume Control
DSP (ROM Code)
Volume can be controlled with the volume_ch register. The
audio volume is not applied instantly but ramped to avoid
audible click/pop artifacts. Volume ramping can be dis‑
abled by enabling the vol_instant register.
OUT0/1
I2S_DO
2ch
2ch
Audio TX
Volume
Peak Limiter
tx_enable*
ꢀꢀ.ꢉ.ꢂ Peak Limiter (ROM Code)
*Refer to register map for description
Figure ꢀꢀ.ꢀꢆ: DSP ROM code
The peak limiters in the ROM code can be configured with
attack_ch, release_ch and threshold_ch registers, which
control the attack and release times as well as the threshold
for limiting. The attack and release times are sample rate
dependent in the way that a higher register value should
be chosen for higher sample rates to achieve an equivalent
attack/release time.
The ROM code can be disabled by disabling the DSP entirely
in the dsp_enable register. Alternatively, the DSP can be
bypassed with the dsp_bypass register. The output signal
would be identical using either method, but the power con‑
sumption is slightly reduced by disabling the DSP instead of
bypassing.
ꢀꢀ.ꢀꢅ Auxiliary ADC
MAꢁꢄꢉꢈPNS features an ꢃ‑bit auxiliary ADC. The ADC can
sample from the power stage supply PVDD, the internal
Datasheet
page ꢂꢃ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
data_alignment
Four-channel audio data example (TDM)
I2S delayed 1 bit
(Equal to LJ + 1 bit shi�)
data_size
MSB
MSB
LSB
MSB
MSB
LSB
MSB
MSB
LSB
MSB
MSB
LSB
16 bit
24 bit
I2S
LJ
LSB
LSB
LSB
LSB
MSB
MSB
LSB
MSB
MSB
LSB
MSB
MSB
LSB
MSB
MSB
LSB
16 bit
24 bit
LSB
LSB
LSB
LSB
MSB
LSB
LSB
MSB
LSB
LSB
MSB
LSB
LSB
MSB
LSB
LSB
16 bit
24 bit
RJ
MSB
MSB
MSB
MSB
Channel/slot 0
Channel/slot 1
Channel/slot 2
Channel/slot 3
slot_size: 32 bit
Audio frame: 128 bit (4 channels of 32 bit)
I2S_WC
Figure ꢀꢀ.ꢀꢇ: Audio data configuration/timing for four channels. Note that choosing ’IꢁS’ in data_alignment for
MAꢁꢄꢉꢈPNS does not restrict the data stream to only two channels. ’IꢁS’ in data_alignment just refers to the data being
aligned to the leꢋ and delayed by one bit.
Device address Register address
ꢆ bits + R/W bit ꢂꢊ bits
Data
ꢃ bits
temperature sensor or a voltage on the ADC_IN pin from an
external source. The sampled data is available in registers
pvdd_chip, temp_chip and adc_pin. The ADC_IN pin
voltage range is ꢉ V (min) to ꢂ V (max).
Please see Section ꢂꢂ.ꢂꢂ.ꢁ and ꢂꢂ.ꢂꢂ.ꢄ for device address‑
ing and write/read commands.
The ADC can be useful for general purpose monitoring, e.g.
keeping temperature below a specified point by adjusting
volume if temperature readings become too high according
to the application specification. The ADC is not designed for
tasks with high precision.
The SDA and SCL lines must be pulled high once per
application to the voltage supplying VDD_IO through a
resistor, e.g. ꢁ.ꢁ kΩ, to ensure correct IꢁC functionality. The
minimum and maximum recommended pull‑up resistor
value is shown in specifications.
ꢀꢀ.ꢀꢀ IꢁC Serial Control Interface
Please refer to the original IꢁC bus specification and user
manual provided by NXP Semiconductors for more detailed
information on IꢁC communication.
MAꢁꢄꢉꢈPNS oꢅers a serial control interface through the
standard ꢁ‑wire IꢁC protocol using IꢁC_SDA (data) and
IꢁC_SCL (clock) lines. An application host device may then
access the register map to configure the MAꢁꢄꢉꢈPNS.
ꢀꢀ.ꢀꢀ.ꢀ Device Address
Device addresses for IꢁC communication can be set by
pulling the IꢁC_ADꢉ (pin ꢄꢊ) and IꢁC_ADꢂ (pin ꢄꢀ) pins to
VDD_IO(high)orground(low). Thisgivesfouruniquedevice
addresses for applications with up to eight BTL channels.
ThepinconfigurationonIꢁC_ADꢉandIꢁC_ADꢂareonlyread
once during start‑up of the device.
VDD_IO
MA23xx
Host device
(Microcontroller)
2.2 kꢀ
2.2 kꢀ
I2C_SDA (17)
I2C_SCL (18)
SDA
SCL
Table ꢀꢅ: Device addresses combinations
Figure ꢀꢀ.ꢀꢈ: IꢁC serial control interface block diagram
IꢁC address
ꢉxꢁꢉ
IꢁC_ADꢀ
Low
IꢁC_ADꢅ
Low
ꢉxꢁꢂ
Low
High
MAꢁꢄꢉꢈPNS uses ꢂꢊ bit register adresses for its internal
register map (example: ꢉxꢉꢉꢉꢂ). The SDA line is sampled
on the rising edge of the SCL line and the IꢁC command is
shiꢋed/sampled with MSB first.
ꢉxꢁꢁ
High
Low
ꢉxꢁꢄ
High
High
If four device addresses are not suꢅicient, hardware resis‑
tor programming can be used for the IꢁC_ADꢉ and IꢁC_ADꢂ
pins to enable up to ꢊꢈ unique device addresses. The pins
must be connected to ground through a resistor of a spe‑
Communicating properly with the MAꢁꢄꢉꢈPNS to access a
single register must contain the following IꢁC sequence:
Datasheet
page ꢂꢇ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
cific value as shown in Figure ꢂꢂ.ꢂꢇ. Table ꢂꢂ illustrates the
combination of resistors to yield a specific address.
command to the IꢁC address (bit ꢃ, write=ꢂ), followed by
the device address to read from.
The device will acknowledge the two bytes and data can
now be read from the device by sending a repeated start,
followed by an IꢁC read command (bit ꢃ, read=ꢂ).
I2C_AD1
I2C_AD0
R1
R2
The device will acknowledge the read request and start to
drive the SDA bus with the bits from the requested register
bank address.
Figure ꢀꢀ.ꢀꢉ: Resistor programming schematic
If the user tries to read in a non‑existing address, acknowl‑
edge will be sent anyway but read will be ignored internally
(ꢉxꢉꢉ will be sent to the IꢁC read requester).
Table ꢀꢀ: Device addresses using resistor programming.
Addresses are shown in decimal format
The read transaction continues until the IꢁC source does
not acknowledge the ꢇth bit of the data read byte transac‑
tion and sends a stop condition (rising edge on SDA during
SCL kept high).
Rꢁ
ꢀꢄꢅk ꢀꢅꢅk ꢇꢈk ꢃꢆk ꢂꢂk ꢁꢁk ꢀꢄk ꢀꢅk
Rꢀ
ꢀꢄꢅk
ꢀꢅꢅk
ꢇꢈk
ꢃꢆk
ꢂꢂk
ꢁꢁk
ꢀꢄk
ꢀꢅk
ꢉ
ꢂ
ꢁ
ꢄ
ꢈ
ꢀ
ꢊ
ꢆ
ꢃ
ꢇ
ꢂꢉ
ꢂꢃ
ꢁꢊ
ꢄꢈ
ꢈꢁ
ꢀꢉ
ꢀꢃ
ꢂꢂ
ꢂꢇ
ꢁꢆ
ꢄꢀ
ꢈꢄ
ꢀꢂ
ꢀꢇ
ꢂꢁ
ꢁꢉ
ꢁꢃ
ꢄꢊ
ꢈꢈ
ꢀꢁ
ꢊꢉ
ꢂꢄ
ꢁꢂ
ꢁꢇ
ꢄꢆ
ꢈꢀ
ꢀꢄ
ꢊꢂ
ꢂꢈ
ꢁꢁ
ꢄꢉ
ꢄꢃ
ꢈꢊ
ꢀꢈ
ꢊꢁ
ꢂꢀ
ꢁꢄ
ꢄꢂ
ꢄꢇ
ꢈꢆ
ꢀꢀ
ꢊꢄ
Refer to Figure ꢂꢂ.ꢁꢉ for read sequence.
ꢂꢊ
ꢁꢈ
ꢄꢁ
ꢈꢉ
ꢈꢃ
ꢀꢊ
ꢂꢆ
ꢁꢀ
ꢄꢄ
ꢈꢂ
ꢈꢇ
ꢀꢆ
Read Operation without Write Start
To read data from the device register bank, the IꢁC source
can send a read transaction without write command first,
meaning an IꢁC read command consisting of a byte with
the device IꢁC address and the R/W bit set. The device will
acknowledge the read request and start to drive the SDA
bus with the bits from the last requested register bank ad‑
dress+ꢂ.
ꢀꢀ.ꢀꢀ.ꢁ IꢁC Write Operation
Each IꢁC transaction is initiated from an IꢁC transmitter
by sending an IꢁC start condition followed by the ꢆ‑bit IꢁC
device address and the read/write bit (bit ꢃ, write=ꢉ).
ꢀꢀ.ꢀꢁ EMI Mitigation
In addition to the inherently low EMI levels from the
MERUS™ multilevel switching output, MAꢁꢄꢉꢈPNS features
ways to mitigate EMI further, which can be useful for appli‑
cations with multiple devices.
If the transmitted IꢁC address matches the configured
address of the device, the device will acknowledge the
request by pulling the SDA line to ground (bit ꢇ). The IꢁC
transmitter samples the acknowledged bit from the device
on the next rising edge of SCL.
ꢀꢀ.ꢀꢁ.ꢀ Configurable Switching Edge
To complete the write operation, the IꢁC transmitter must
continue transmitting the address and at least one data
byte. The device continues to acknowledge each byte
received on the ꢇth SCL rising edge. Each additional data
byte written to the device is written to the next address in
the register bank.
Fast square wave switching transients usually increase the
amount of unwanted high frequency EMI. The switching
edge steepness (slew rate) can be controlled in the gd_dVdt
register which can be used as a tool for tuning applications
forEMIcompliance. Thecompromiseis eꢅiciency, asslower
transients will result in higher switching losses). Additional
EMI suppression can be achieved by reducing the switching
edge steepness (tested using the MAꢁꢄꢉꢈPNS EVK).
The write transaction is terminated when the IꢁC transmit‑
ter sends a stop condition to the device (rising edge on SDA
during SCL kept high).
ꢀꢀ.ꢀꢁ.ꢁ PWM Synchronization for EMI Reduction
Block writing large amounts of data is also supported.
Refer to Figure ꢂꢂ.ꢁꢉ for write sequence.
ꢀꢀ.ꢀꢀ.ꢂ IꢁC Read Operation
In multi‑channel systems with multiple MAꢁꢄꢉꢈPNS de‑
vices, it can be increasingly necessary to suppress EMI. The
NCLIP pin (ꢂꢁ) can be used as an input/output to synchro‑
nize PWM signals of multiple devices and allow them to be
driven out of phase which can have an influence on EMI per‑
formance. PWMsyncisconfiguredaccordingtoFigureꢂꢂ.ꢁꢄ
as follows:
To read data from the device register bank, the read trans‑
action is started by the IꢁC transmitter, sending a write
Datasheet
page ꢁꢉ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
I2C rite singlebyte:
S
Device addr [6:0] W
A
A
Register addr [15:8]
Register addr [15:8]
Register addr [15:8]
A
A
A
Register addr [7:0]
Register addr [7:0]
Register addr [7:0]
A
A
A
Data [7:0]
Data [7:0]
S
A
A
S
S
I2C write multiple bytes:
Device addr [6:0] W
S
Data [7:0]
A
...
S
I2C read single byte:
S
Device addr [6:0] W
A
A
S
Device addr [6:0]
R
Data [7:0]
A
S
A
W
R
Acknowledge
Write
I2C read multiple bytes:
S
Device addr [6:0] W
A
A
Register addr [15:8]
Data [7:0]
A
Register addr [7:0]
A
S
Read
S
Device addr [6:0]
R
A
Data [7:0]
A
...
S
S
Start/stop
Figure ꢀꢀ.ꢁꢅ: IꢁC write and read sequences
VDD_IO
10 kΩ
I2S_WC
NCLIP
AUDIO
HOST
MA23xx
PWM source
Figure ꢀꢀ.ꢁꢀ: Configurable PWM switching edges to
I2S_SCK
(output)
reduce high frequency EMI content
I2S_WC
NCLIP
MA23xx
PWM sink
Efficiency vs. gd_dVdt settings
90
I2S_SCK
(input)
85
80
75
70
65
I2S_WC
NCLIP
MA23xx
PWM sink
I2S_SCK
(input)
Figure ꢀꢀ.ꢁꢂ: PWM synchronization for multiple
MAꢁꢄꢉꢈPNS devices
sink devices by setting time lag in reg.pwm_phase
gd_dVdt=11
gd_dVdt=10
gd_dVdt=01
gd_dVdt=00
60
55
50
PMP=LPC
NCLIPmustbepulleduptoVDD_IOthroughaꢂꢉkΩresistor.
The clock signals IꢁS_SCK and IꢁS_WC in the audio stream
must be the same for all devices.
0.1
1
10
30
Output Power p/ch [W]
Figure ꢀꢀ.ꢁꢁ: Eꢅiciency for diꢅerent gd_dVdt settings
ꢀꢀ.ꢀꢂ Post‑Ferrite Filter Feedback
MAꢁꢄꢉꢈPNS can include an output filter ferrite in the inter‑
nal control loop to compensate for the non‑linearities in
the ferrite material and as such improve audio performance
in terms of THD+N. This relaxes the requirements for high
quality ferrites and can therefore minimize cost of the
output filter.
ꢂ. Configure NCLIP pin to act as PWM input/output
gpio_sync_zclip
ꢁ. Configure PWM source device by setting
sync_out_enable
The feedback pins (FBXA and FBXB) must always be con‑
nected for loop stability. If post‑ferrite feedback is not
desired, the feedback pins must be directly connected to
the OUTXA and OUTXB pins, respectively as shown in Figure
ꢂꢂ.ꢁꢀ.
ꢄ. Configure PWM sink devices by setting sync_in_enable
ꢈ. Control PWM phase relationship in either source or
Datasheet
page ꢁꢂ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Post Ferrite Filter Feedback
FB0A
OUT0A
Amp only (no filter)
Pre-filter feedback
Post-filter feedback
Ferrite: BLM31KN471SH1L
Config:BTL
FB
FB
10
1
Cf
Cf
Load: 4 +22µH
Signal:1kHz
FB0B
OUT0B
Figure ꢀꢁ.ꢀ: EMC ferrite output filter
0.1
0.01
Table ꢀꢁ: EMC ferrite filter recommendation
Ferrite
Capacitor
ꢁꢁꢉ pF
NFZꢁMSDꢂꢀꢉSNꢂꢉL
NFZꢁMSDꢄꢉꢂSZꢂꢉL
0.01
0.1
1
10
ꢁꢁꢉ pF
Output power [W]
Figure ꢀꢀ.ꢁꢃ: Example of the post‑ferrite filter feedback
PCB layout for the output filter should be tight and with
the smallest possible current return path for optimal EMI
performance. In an application, cables connected from
speaker terminals to the PCB should be twisted if possible
for the same reason.
eꢅect on distortion characteristics
Post-ferrite
Pre-ferrite
FBXA
FBXA
ꢀꢁ.ꢀ.ꢀ Capacitor Value Impact on Power Consumption
OUTXA
OUTXA
The filter capacitor can have a significant impact on the
MAꢁꢄꢉꢈPNS power consumption and must be of relatively
low capacitance value, e.g. ꢂꢉꢉ‑ꢁꢁꢉ pF for minimal impact.
For a ꢁꢁꢉ pF capacitor on each output channel in a BTL
configuration results in approximately ꢂꢉ‑ꢁꢉ mW additional
power consumption at idle operation. Higher capacitance
values will increase power consumption further, but also
provide a lower corner frequency with improved suppres‑
sion of EMI. The capacitor value should be balanced for the
target application, however, no more than ꢂ nF should be
used.
FBXB
OUTXB
FBXB
OUTXB
Figure ꢀꢀ.ꢁꢄ: Post‑ferrite filter feedback schematic
It is not recommended to use an LC filter with post‑ferrite
filter feedback because the phase introduced by the LC fil‑
ter can cause loop instability. If an LC filter is desired in the
application, pre‑ferrite feedback should be used.
Please refer to MAꢁꢄꢉꢈPNS application notes for more infor‑
mation and EMI measurement results.
ꢀꢁ.ꢀ.ꢁ Ferrite Filter Selection
ꢀꢁ Application Information
The most important factor in EMI suppression is the output
filter ferrite bead. Ferrite bead performance may vary
greatly in terms of eꢅective frequency region and suppres‑
sion magnitude. This means that one ferrite part cannot
necessarily replace another directly, and must be tested
at an EMC lab for verification of compliance with regula‑
tions. An important characteristic is saturation current of
ferrite material, which must comply with the maximum
application output current in order to be eꢅective at high
output levels. Ferrites in ꢉꢃꢉꢀ/ꢂꢁꢉꢊ SMD packages will
usually provide suꢅicient specifications. The NFZ‑series
from Murata yields good results, e.g. NFZꢁMSDꢄꢉꢂSZꢂꢉL
and NFZꢁMSDꢂꢀꢉSNꢂꢉL.
ꢀꢁ.ꢀ EMC Ferrite Output Filter
The MAꢁꢄꢉꢈPNS allows for inductor‑less operation while
achieving EMI compliance. This is mainly due to the
MERUS™ multilevel switching technology which reduces
the magnitude of the switching waveform at all output lev‑
els. A simple and inexpensive ferrite‑capacitor output filter
can be used to suppress the emissions from the amplifier
output. The filter schematic is shown in Figure ꢂꢁ.ꢂ and rec‑
ommended filter component values are shown in Table ꢂꢁ.
Datasheet
page ꢁꢁ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Table ꢀꢄ: Power and noise performance characteristics for
ꢀꢁ.ꢀ.ꢂ Ferrite Filter Stability Under Light Loads
recommended LC filter designs.
Operating the MAꢁꢄꢉꢈPNS under very light output loads
above ꢀꢉꢉ Ω can result in the amplifier’s feedback loop be‑
coming unstable, which can be a real scenario if the load is
planned to be disconnected from time to time. If the load
is planned to be disconnected during normal operation, it
is recommended to use an RC damping network (snubber)
similar to the damping network using an LC filter (Refer to
Sectionꢂꢁ.ꢂ.ꢈ). StartingpointRCvaluescanbeR<ꢀꢉꢉΩand
C=ꢁꢁ nF but they need to be tuned to the specific applica‑
tion. The RC network will help maintain loop stability when
the load is removed.
*Ref: Reference using no filter. Same device and board
(EVK) was used to test all filter designs including reference.
**LPC mode was not applicable with high capacitance filter
components.
Idle power
LPC
Output noise
Design
HAP
LPC
HAP
Ref*
#ꢂ
ꢈꢇ mW
ꢆꢀ mW
ꢆꢊ mW
ꢆꢉ mW
N/A**
ꢆꢈ mW
ꢂꢉꢊ mW
ꢇꢊ mW
ꢃꢁ mW
ꢊꢇ mW
ꢇꢉ μV
ꢂꢁꢉ μV
ꢂꢉꢂ μV
ꢇꢀ μV
N/A**
ꢀꢈ μV
ꢊꢉ μV
ꢀꢀ μV
ꢀꢈ μV
ꢀꢄ μV
#ꢁ
#ꢄ
#ꢈ
ꢀꢁ.ꢀ.ꢃ LC filter options
ꢀꢁ.ꢁ Thermal Design
The MAꢁꢄꢉꢈPNS is designed to be used in applications
without external heatsink. A well‑designed ꢈ‑layer PCB
can act as a heatsink. The bottom thermal pad (EPAD) of
the IC package should be thermally well‑connected to the
top layer copper with as many vias as possible to the other
layers. It is recommended to keep routed traces in the
middle layers to a minimum, avoiding any routing at all
if possible. Let the bottom layer only be used for routing
traces between layers. Deadspace in all layers should
be filled with copper connected to ground to maintain
unhindered thermal flow away from the IC. Refer to Figure
ꢂꢁ.ꢃ for PCB layout reference.
MAꢁꢄꢉꢈPNS can also operate with a LC filter for even
higher EMI suppression. An LC filter can provide additional
suppression of EMI, but will usually be higher cost and
footprint size on board than a ferrite filter.
FB0A
OUT0A
L
Cd
Rd
Cf
Cf
Rd
Cd
FB0B
OUT0B
L
Heat is generated primarily in the on‑resistance of the in‑
ternal MOSFETs, as well as the bond wires from the sili‑
con to the IC pins, and will be dependent on load current.
The losses due to heat will be more severe with lower load
impedances, as conduction losses in the IC will dominate
with increasing current. A comparison between load and
output configuration (BTL/PBTL) is shown in Figure ꢂꢄ.ꢂꢁ
and ꢂꢄ.ꢂꢄ.
Table ꢀꢂ: LC filter schematic
The LC filter has to be carefully designed and tested to
properly avoid instability with MAꢁꢄꢉꢈPNS. Stability issues
can occur if the filter corner frequency is too low and
non‑suꢅicient EMI suppression may occur if the corner
frequency is too high. The LC filter should consist of a
filtering part (L and Cf) and a damping network (Cd and
Rd) as shown in Figure ꢂꢄ. Typical recommended LC filter
component values are shown in Table ꢂꢈ.
ꢀꢁ.ꢂ Start‑up Procedure
The recommended procedure for proper start‑up of the de‑
vice:
ꢂ. Keep the device disabled and muted: ENABLE = ꢉ,
NMUTE = ꢉ.
Table ꢀꢃ: Recommended LC filter component values
Design
#ꢂ
L
Cf
Cd + Rd
ꢁ. Ensure MSEL, ADꢉ and ADꢂ pins are configured cor‑
rectly.
ꢄ.ꢄ μH
ꢈ.ꢆ μH
ꢊ.ꢃ μH
ꢂꢉ μH
ꢈꢆꢉ pF
ꢂ nF
ꢂ nF + ꢁꢁꢉ Ω
ꢂꢉ nF + ꢂꢉꢉ Ω
ꢂꢉꢉ nF + ꢁꢁ Ω
ꢂ μF + ꢂꢉ Ω
#ꢁ
#ꢄ
ꢂꢉ nF
ꢁꢁꢉ nF
ꢄ. Enable VDD, VDD_IO and PVDD supplies and wait for
them to become stable.
#ꢈ
ꢈ. Ensure IꢁS bit clock and frame clock are present.
ꢀ. Enable device: ENABLE = ꢂ.
Table ꢂꢀ shows the diꢅerence in output noise (A‑weighted)
and idle power consumption as a function of the LC filter
components and Power Mode Profile. All characteristics
shown in the table are derived from the same device on the
same board (EVK).
ꢊ. Wait TENABLE until the device has started up in order to
readtheNERRpinstatusandstartcommunicatingwith
IꢁC.
Please refer to MAꢁꢄꢉꢈPNS application notes for more infor‑
mation and EMI measurement results.
ꢆ. Program/initialize the device via IꢁC (if needed)
Datasheet
page ꢁꢄ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢃ. Unmute device: NMUTE = ꢂ. When NMUTE time has
elapsed, the device is ready for audio playback.
• Fly‑caps: Flying capacitors for VFCxxx pins must be
kept as close to the device as possible and care must
be taken to keep the current loop tight and short to en‑
sure multilevel switching stability.
ꢇ. The device is now in normal operation state (idle) and
ready to play audio.
• PCB layers: A PCB with four layers is recommended
to achieve power output performance stated in the
electrical characteristics. Via stitching/array between
board layers is encouraged on the ground net (GND),
especially below the bottom thermal pad of the de‑
vice which uses the PCB as a heatsink to dissipate heat.
In general, the unused copper (deadspace) in all lay‑
ers should be connected to ground for optimal thermal
and EMI performance. Avoid breaking up the ground
planes with any routing traces in all layers as much as
possible to ensure good thermal connection through‑
out all PCB layers.
ꢀꢁ.ꢃ Procedure for handling discontinuous
audio clock
In some applications the audio clocks may be stopped by
the transmitter side from time to time, which will also
halt the MAꢁꢄꢉꢈPNS audio playback. When the clocks re‑
turn, MAꢁꢄꢉꢈPNS will continue operation once the PLL has
locked again. MAꢁꢄꢉꢈPNS is designed to handle loss of
clocks without any audio artifacts without muting. For op‑
timal performance, it is recommended to follow this proce‑
dure:
ꢂ. The device is in normal operation and audio clocks are
present.
• Output filter: The traces from the output to the filter
should be kept as short as possible for optimal EMI per‑
formance.
ꢁ. Mute the device: NMUTE=ꢉ. Alternatively, put the de‑
vice in standby mode.
• RC filter on IꢁS: Digital audio/control lines (IꢁS/IꢁC)
can have an impact on EMI performance. It is sug‑
gested to implement a RC first order lowpass filter
close to the source on these lines to slow the transients
and hence avoiding high frequency EMI. Values for the
resistor and capacitor in the lowpass filter will be ap‑
plication dependent, but a good starting point could
be ꢄꢄ Ω and ꢂꢃꢉ pF.
ꢄ. Disable the audio clocks from the transmitting side.
The device is now only operational through IꢁC. PLL er‑
ror is reported to the error register internally.
ꢈ. When audio playback is required again, enable the au‑
dio clocks, wait for the PLL to lock and the device to be
fully operational again (see timing for TENABLE
)
• Output cables placement: Keep output speaker ter‑
minals/cables on the opposite side of the PCB from
PVDD for EMI reasons. Radiated emission from the out‑
put switching waveform can couple from the output
cables to the PVDD traces/cables and influence con‑
ducted emission performance significantly.
ꢀ. Unmute the device: NMUTE=ꢂ. Alternatively, put the
device out of standby mode.
ꢊ. The device is now in normal operation again and ready
to play audio.
ꢀꢁ.ꢄ Power‑down Procedure
The recommended procedure for proper power‑down de‑
scribed below:
ꢂ. The device is in normal operation state.
ꢁ. Mute device: NMUTE = ꢉ.
ꢄ. Disable device: ENABLE = ꢉ.
ꢈ. The device is now in power‑down state.
ꢀ. (Optional: Bring down VDD, VDD_IO and PVDD sup‑
plies.)
ꢀꢁ.ꢇ Recommended Layout
The recommended application/PCB layout is shown in Fig‑
ure ꢂꢁ.ꢃ:
• Decoupling: Decoupling capacitors for power sup‑
plies VDD, AVDD_REG, DVDD_REG, CD_DIG, PVDD and
VDD_IO must be kept as close to the device as possible.
The smallest value capacitors should be placed closest
to the device to handle fast transients.
Datasheet
page ꢁꢈ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢁ.ꢆ Evaluation Board as Reference
The EVAL_AUDIO_MAꢁꢄꢉꢈPNS evaluation board can be used as reference when designing an application. The evaluation
board layout has specifically been optimized to achieve best possible thermal performance without an external heatsink.
Refer to Figures ꢂꢁ.ꢁ through ꢂꢁ.ꢆ and/or refer to design files on infineon.com
Figure ꢀꢁ.ꢂ: Evaluation board bottom side
Figure ꢀꢁ.ꢁ: Evaluation board top side
Figure ꢀꢁ.ꢃ: Top Layer
Figure ꢀꢁ.ꢄ: Mid Layer ꢂ
Figure ꢀꢁ.ꢇ: Mid Layer ꢁ
Figure ꢀꢁ.ꢆ: Bottom Layer
Datasheet
page ꢁꢀ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Bottom thermal pad: VSS (ground)
West side:
North side:
PVDD input and amplifier output
Power suppliesand static tie-offs
Connect VSS topower ground with via
array/stitching good thermal
performance
VDD_IO or GND
or resistors
Supply
decoupling
caps close
to IC
GND: PBTL
VDD_IO: BTL
0402
X5R
1uF
0402
X5R
1uF
6.3V
6.3V
VDD_IO
VDD
ADC input
1V=0dB
0402
X5R
1uF
0402
X5R
1uF
6.3V
6.3V
VDD
FB0A
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
FB1A
OUT0B
OUT0A
VFC0AN
OUT0A
VFC0AP
PVDD
VFC1AN
OUT1A
VFC1AP
PVDD
0603
X5R
1uF
25V
PVDD
PVDD
VFC0BP
OUT0B
VFC0BN
VFC1BP
OUT1B
VFC1BN
FB1B
10 FB0B
0805
10uF
25V
0402
0402
51kΩ
South side:
DigitalI/O
X5R
Via to GND
51kΩ
PCB copper layer stack (4-layer)
Top
Layer
Signallayer. Fill deadspace with ground.
Mid
Layer 1
Ground layer. Avoid any traces in this layer
for best thermalperformance.
Mid
Layer 2
Ground layer. Avoid any traces in this layer
for best thermalperformance.
Bottom Ground layer. Place traces to a minimal
Layer extend only. Avoid long traces in this layer.
Figure ꢀꢁ.ꢈ: Recommended application/PCB layout for best performance
Datasheet
page ꢁꢊ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢂ Typical Characteristics
Note that some characteristics are based on interpolated/averaged data.
ꢀꢂ.ꢀ Eꢊiciency and power consumption
Efficiency VS output power
Efficiency VS output power
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
PVDD=18V
Signal=1kHz
PVDD=18V
Signal=1kHz
BTL 4 +22µH HAP
BTL 4 +22µH LPC
BTL 8 +22µH HAP
BTL 8 +22µH LPC
0.01
0.1
1
10
40
0.01
0.1
1
10
40
Output power p/ch [W]
Output power p/ch [W]
Figure ꢀꢂ.ꢀ
Figure ꢀꢂ.ꢁ
Efficiency VS output power
Efficiency VS output power
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
PVDD=18V
Signal=1kHz
PVDD=18V
Signal=1kHz
PBTL 2 +22µH HAP
PBTL 2 +22µH LPC
PBTL 4 +22µH HAP
PBTL 4 +22µH LPC
0.01
0.1
1
10
40
0.01
0.1
1
10
40
Output power p/ch [W]
Output power p/ch [W]
Figure ꢀꢂ.ꢂ
Figure ꢀꢂ.ꢃ
Datasheet
page ꢁꢆ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Efficiency VS output power
100
Efficiency VS output power
100
90
80
70
60
50
40
30
20
10
90
80
70
60
50
PVDD=18V
PVDD=18V
Signal=1kHz
Signal=1kHz
40
BTL 4 +22µH LPC
BTL 4 +22µH HAP
BTL 8 +22µH HAP
PBTL 2 +22µH HAP
PBTL 4 +22µH HAP
30
BTL 8 +22µH LPC
PBTL 2 +22µH LPC
20
PBTL 4 +22µH LPC
10
0.01
0.1
1
10
40
0.01
0.1
1
10
40
Output power p/ch [W]
Output power p/ch [W]
Figure ꢀꢂ.ꢄ
Figure ꢀꢂ.ꢇ
Input power VS output power
Input power VS output power
40
10
40
10
1
1
0.1
PVDD=18V
PVDD=18V
0.1
Signal=1kHz
Signal=1kHz
BTL 4 +22µH LPC
BTL 4 +22µH HAP
BTL 8 +22µH LPC
BTL 8 +22µH HAP
0.01
0.01
0.01
0.1
1
10
40
0.01
0.1
1
10
40
Output power [W]
Output power [W]
Figure ꢀꢂ.ꢆ
Figure ꢀꢂ.ꢈ
Input power VS output power
Input power VS output power
40
10
40
10
1
0.1
1
0.1
PVDD=18V
Signal=1kHz
PVDD=18V
Signal=1kHz
PBTL 2 +22µH LPC
PBTL 2 +22µH HAP
PBTL 4 +22µH LPC
PBTL 4 +22µH HAP
0.01
0.01
0.01
0.1
1
10
40
0.01
0.1
1
10
40
Output power [W]
Output power [W]
Figure ꢀꢂ.ꢉ
Figure ꢀꢂ.ꢀꢅ
Datasheet
page ꢁꢃ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Total idle power consumption vs PVDD voltage
VDD=1.8V, LPC
VDD=1.8V, HAP
80
VDD=3.3V, LPC
VDD=3.3V, HAP
70
60
50
40
Config=BTL
Load=4 +22µH
30
20
Output filter=None
Output unmuted
10
11
12
13
14
15
16
17
18
PVDD [V]
Figure ꢀꢂ.ꢀꢀ
Datasheet
page ꢁꢇ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢂ.ꢁ Thermal performance
Thermal Curves
Thermal Curves
150
150
140
130
120
110
100
90
Temp Error
Temp Error
140
130
120
Temp Warning
Temp Warning
110
100
90
80
80
70
70
60
60
2 ohm + 22 uH - 2x6W
50
40
30
50
PVDD=18V
Config=BTL
PVDD=18V
4 ohm + 22 uH - 2x12W
8 ohm + 22 uH - 2x20W
2 ohm + 22 uH - 1x24W
4 ohm + 22 uH - 1x30W
Config=PBTL
40
30
0
2
4
6
8
10
0
2
4
6
8
10
Time [min]
Time [min]
Figure ꢀꢂ.ꢀꢁ
Figure ꢀꢂ.ꢀꢂ
Figure ꢀꢂ.ꢀꢃ: Thermal photo of EVAL_AUDIO_MAꢁꢄꢉꢈPNS Figure ꢀꢂ.ꢀꢄ: Thermal photo of EVAL_AUDIO_MAꢁꢄꢉꢈPNS
at ꢁxꢂ W, ꢈ Ω
EVK at ꢁxꢂꢁ W, ꢈ Ω
75
70
65
60
55
50
45
40
35
30
25
20
15
BTL 4 +22 µH
PBTL 2 +22 µH
BTL 8 / PBTL 4
will not trigger OTE
on evaluation board
10
10
30
100
300
600
Time elapsed before Temperature Error [s]
Figure ꢀꢂ.ꢀꢇ
Datasheet
page ꢄꢉ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢂ.ꢂ Audio performance
THD+N vs Power
10
THD+N vs Power
10
1
4
8
4
8
+22µH LPC
+22µH LPC
+22µH HAP
+22µH HAP
2
4
2
4
+22µH LPC
Config:BTL
Signal:1kHz
Config:PBTL
Signal:1kHz
+22µH LPC
+22µH HAP
+22µH HAP
1
0.1
0.1
0.01
0.0001
0.01
0.0001
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
Output power [W]
Output power [W]
Figure ꢀꢂ.ꢀꢆ
Figure ꢀꢂ.ꢀꢈ
THD+N vs Power
THD+N vs Power
10
1
10
1
4
8
4
8
+22µH LPC
2
4
2
4
+22µH LPC
Config:BTL
Config:PBTL
+22µH LPC
+22µH HAP
+22µH HAP
+22µH LPC
+22µH HAP
+22µH HAP
Signal:6.3 kHz
Signal:6.3 kHz
0.1
0.1
0.01
0.0001
0.01
0.0001
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
Output power [W]
Output power [W]
Figure ꢀꢂ.ꢀꢉ
Figure ꢀꢂ.ꢁꢅ
THD+N vs Frequency
THD+N vs Frequency
10
1
10
1
LPC 4 +22µH
LPC 8 +22µH
HAP 4 +22µH
HAP 8 +22µH
LPC 2 +22µH
LPC 4 +22µH
HAP 2 +22µH
HAP 4 +22µH
Config=BTL
5W p/ch
Config=PBTL
5W p/ch
0.1
0.1
0.01
0.01
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency [Hz]
Frequency [Hz]
Figure ꢀꢂ.ꢁꢀ
Figure ꢀꢂ.ꢁꢁ
Datasheet
page ꢄꢂ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Output power VS PVDD
40
Output power VS PVDD
25
20
15
10
5
Config: BTL
Config: BTL
Load: 8 + 22 µH
35
30
25
20
15
10
5
Load: 4 + 22 µH
1% THD
1% THD
10% THD
10% THD
0
10
0
10
11
12
13
14
15
16
17
18
11
12
13
14
15
16
17
18
PVDD [V]
PVDD [V]
Figure ꢀꢂ.ꢁꢂ
Figure ꢀꢂ.ꢁꢃ
Output power VS PVDD
Output power VS PVDD
80
70
60
50
40
30
20
10
40
35
30
25
20
15
10
Config: PBTL
Load: 2 + 22 µH
Config: PBTL
Load: 4 + 22 µH
1% THD
1% THD
10% THD
10% THD
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
PVDD [V]
PVDD [V]
Figure ꢀꢂ.ꢁꢄ
Figure ꢀꢂ.ꢁꢇ
Datasheet
page ꢄꢁ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Noise spectrum
-40
Gain vs frequency
24
23
22
21
20
19
18
17
16
15
14
13
12
LPC mode
HAP mode
Load=4 +22 uH
Config=BTL
-60
Signal=1kHz -60dBFS
Filter=10Hz-20kHz
Averages=20
-80
-100
pvdd_scale=00
PMP=HAP
pvdd_scale=01
pvdd_scale=10
pvdd_scale=11
Signal=1kHz
Level=-17dBFS
-120
-140
20
100
1k
10k 20k
10
100
1k
10k
80k
Frequency [Hz]
Frequency [Hz]
Figure ꢀꢂ.ꢁꢆ
Figure ꢀꢂ.ꢁꢈ
Noise VS PVDD (LPC mode)
Noise VS PVDD (HAP mode)
110
100
90
110
100
90
pvdd_scale=00
pvdd_scale=00
PMP=LPC
PMP=HAP
pvdd_scale=01
pvdd_scale=10
pvdd_scale=11
pvdd_scale=01
pvdd_scale=10
pvdd_scale=11
Signal=1kHz -60dBFS
Weighting=A-wgt
Filter=10Hz-20kHz
Signal=1kHz -60dBFS
Weighting=A-wgt
Filter=10Hz-20kHz
80
80
70
70
60
60
50
50
40
40
30
10
30
10
11
12
13
14
15
16
17
18
11
12
13
14
15
16
17
18
PVDD voltage [V]
PVDD voltage [V]
Figure ꢀꢂ.ꢁꢉ
Figure ꢀꢂ.ꢂꢅ
Datasheet
page ꢄꢄ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢃ Register map
Legend:
Red: Bits in the register which correspond to the specific Name/Function.
pa
Address Reset Name/Function
Bits
Value
Description
Power Mode Profile selection
ꢁ:ꢉ ꢉꢉꢂꢂꢉꢉꢂꢉ ꢉꢂꢉ: LPC mode
ꢂꢉꢉ: HAP mode
Output channel configuration
ꢉꢉꢂꢂꢉꢉꢂꢉ ꢉ: BTL mode
ꢉxꢉꢉꢉꢉ
ꢉxꢄꢁ PMP_select
mode_pbtl
ꢄ
ꢂ: PBTL mode
Gain scaling.
ꢉꢉ: Optimized for PVDD=ꢂꢉV
pvdd_scale
ꢀ:ꢈ ꢉꢉꢂꢂꢉꢉꢂꢉ ꢉꢂ: Optimized for PVDD=ꢂꢁV
ꢂꢉ: Optimized for PVDD=ꢂꢀV
ꢂꢂ: Optimized for PVDD=ꢂꢃV
Override pin/hardware programmed settings
with register stettings
TBD_reg_ctrl
ꢊ
ꢉꢉꢂꢂꢉꢉꢂꢉ
ꢉ: Hardware settings are chosen
ꢂ: Register settings are chosen
Gate drive strength (dV/dt)
ꢉꢉ: Lowest
ꢉxꢉꢉꢉꢂ
ꢉxꢉꢄ gd_dVdt
ꢂ:ꢉ ꢉꢉꢉꢉꢉꢉꢂꢂ ꢉꢂ: Low
ꢂꢉ: High
ꢂꢂ: Highest
Mute channel ꢉ (mute_source must be set first)
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: Unmute
ꢂ: Mute
Mute channel ꢂ (mute_source must be set first)
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: Unmute
ꢉxꢉꢉꢉꢁ
ꢉxꢉꢉ mute_chꢉ
ꢉ
mute_chꢂ
ꢂ
ꢂ: Mute
ꢉ: Channel ꢉ is enabled
ꢂ: Channel ꢉ is disabled
ꢉ: Channel ꢂ is enabled
ꢂ: Channel ꢂ is disabled
ꢉ: Disable standby
disable_chꢉ
disable_chꢂ
standby
ꢁ
ꢄ
ꢈ
ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢂ: Enable standby
Select source for the internal mute signal
mute_source
ꢀ
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: NMUTE pin
ꢂ: mute_chꢉ/ꢂ register settings
Channel ꢉ volume setting. Step size: ‑ꢉ.ꢆꢀ dB
per register value increment.
ꢉxꢉꢉ: +ꢁꢈ dB
ꢉxꢉꢂ: +ꢁꢄ.ꢁꢀ dB
..
ꢉxꢉꢉꢉꢄ
ꢉxꢁꢉ volume_chꢉ
ꢆ:ꢉ ꢉꢉꢂꢉꢉꢉꢉꢉ
ꢉxꢂF: +ꢉ.ꢆꢀ dB
ꢉxꢁꢉ: +ꢉ.ꢉꢉ dB (default)
ꢉxꢁꢂ: ‑ꢉ.ꢆꢀ dB
..
ꢉxFF: ‑ꢂꢊꢆ.ꢁꢀ dB
Channel ꢂ volume setting. See volume_chꢉ for
more information.
ꢉxꢉꢉꢉꢈ
ꢉxꢁꢉ volume_chꢂ
ꢆ:ꢉ ꢉꢉꢂꢉꢉꢉꢉꢉ
Enable digital audio processor (DSP)
ꢉxꢉꢉꢉꢀ
ꢉxꢉꢉ dsp_enable
ꢂ
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: DSP disabled
ꢂ: DSP enabled
Datasheet
page ꢄꢈ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Audio routing bypasses DSP
dsp_bypass
ꢄ
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: Audio is routed through DSP
ꢂ: Audio is routed directly to amplifier
Volume control ramp disable
vol_instant
ꢉ
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: Volume is ramped
ꢂ: Volume is applied instantly ‑ no ramp
NCLIP pin function select
ꢉ: NCLIP is output pin indicating amp clipping
ꢂ: NCLIP pin is used for inter‑IC PWM
ꢉꢉꢉꢉꢉꢉꢉꢉ
gpio_sync_zclip
ꢈ
synchronization (use sync_in_enable and
sync_out_enable registers to select if NCLIP is
input/output)
State of the clip signal driving the NCLIP pin
(read‑only)
ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉxꢉꢉꢉꢊ
ꢉxꢉꢉ clip_pin
ꢉ
ꢉ: No clipping
ꢂ: Clipping
State of the error signal driving the NERR pin
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: No error
err_pin
ꢂ
ꢂ: Error
ADC reading from ADC_IN pin spanning
ꢉxꢉꢉꢉꢆ
ꢉxꢉꢉꢉꢃ
ꢉxꢉꢉꢉꢇ
ꢉxꢉꢉ adc_pin
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
between ꢉ V (min) and ꢂ V (max)
Read internal temperature sensor. Resolution is
ꢂ °C per increment with ꢉxꢉꢉ=‑ꢀꢉ °C
Read internal PVDD sensor. Resolution is ꢂꢁꢀ
mV per increment
ꢉxꢉꢉ temp_chip
ꢉxꢉꢉ pvdd_chip
Channel ꢂ attack time for peak limiter (ROM
code). Sample rate dependent. At ꢈꢃ kHz:
ꢉxꢉꢉ: ꢉ ms/ꢂꢉ dB (default)
ꢉxꢉꢃ: ꢂ ms/ꢂꢉ dB
ꢉxꢉꢇ: ꢁ ms/ꢂꢉ dB
ꢉxꢉꢉꢉB
ꢉxꢉꢉ attack_chꢂ
ꢈ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉxꢉA: ꢈ ms/ꢂꢉ dB
ꢉxꢉB: ꢃ ms/ꢂꢉ dB
ꢉxꢉC: ꢂꢊ ms/ꢂꢉ dB
ꢉxꢉD: ꢄꢁ ms/ꢂꢉ dB
ꢉxꢉE: ꢊꢈ ms/ꢂꢉ dB
ꢉxꢉF: ꢂꢁꢃ ms/ꢂꢉ dB
Channel ꢉ attack time for peak limiter (ROM
ꢉxꢉꢉꢉA
ꢉxꢉꢉ attack_chꢉ
ꢈ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢈ:ꢉ ꢉꢉꢉꢂꢉꢉꢂꢉ
ꢈ:ꢉ ꢉꢉꢉꢂꢉꢉꢂꢉ
code). See attack_chꢉ for more information.
Channel ꢉ release time for peak limiter (ROM
code). Sample rate dependent. At ꢈꢃ kHz:
ꢉxꢉC: ꢂꢊ ms/ꢂꢉ dB
ꢉxꢉD: ꢄꢁ ms/ꢂꢉ dB
ꢉxꢉE: ꢊꢈ ms/ꢂꢉ dB
ꢉxꢉꢉꢉC
ꢉxꢂꢁ release_chꢉ
ꢉxꢉF: ꢂꢁꢃ ms/ꢂꢉ dB
ꢉxꢂꢉ: ꢁꢀꢊ ms/ꢂꢉ dB
ꢉxꢂꢂ: ꢀꢂꢁ ms/ꢂꢉ dB
ꢉxꢂꢁ: ꢂꢉꢁꢈ ms/ꢂꢉ dB (default)
ꢉxꢂꢄ: ꢁꢉꢈꢃ ms/ꢂꢉ dB
Channel ꢂ release time for peak limiter (ROM
code). See release_chꢉ for more information.
ꢉxꢉꢉꢉD ꢉxꢂꢁ release_chꢂ
Datasheet
page ꢄꢀ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Channel ꢉ threshold for peak limiter (ROM
code). Step size: ‑ꢉ.ꢆꢀ dB per register value
increment.
ꢉxꢉꢉ: +ꢁꢈ dB
ꢉxꢉꢂ: +ꢁꢄ.ꢁꢀ dB
ꢉxꢉꢉꢉE
ꢉxꢉꢉ threshold_chꢉ
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ..
ꢉxꢂF: +ꢉ.ꢆꢀ dB
ꢉxꢁꢉ: +ꢉ.ꢉꢉ dB (default)
ꢉxꢁꢂ: ‑ꢉ.ꢆꢀ dB
..
ꢉxFF: ‑ꢂꢊꢆ.ꢁꢀ dB
Channel ꢂ threshold for peak limiter (ROM
code). See threshold_chꢉ for more information.
ꢉxꢉꢉꢉF
ꢉxꢉꢉ threshold_chꢂ
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
iꢁs_tdm
Address Reset Name/Function
Bits
Value
Description
IꢁS/TDM data alignment
ꢉꢉ: IꢁS
ꢉxꢉꢉꢂꢉ
ꢉxꢂꢉ data_alignment
ꢂ:ꢉ ꢉꢉꢉꢂꢉꢉꢉꢉ
ꢉꢂ: Leꢋ Justified
ꢂꢉ: Right Justified
IꢁS/TDM clock polarity
sck_pol
ꢈ
ꢉꢉꢉꢂꢉꢉꢉꢉ ꢉ: Data changes on rising edge of SCK
ꢂ: Data changes on falling edge of SCK
IꢁS/TDM channel slot size (frame width)
ꢉꢉ: ꢄꢁ bit
slot_size
ꢊ:ꢀ ꢉꢉꢉꢂꢉꢉꢉꢉ
ꢉꢂ: ꢁꢈ bit
ꢂꢉ: ꢂꢊ bit
IꢁS/TDM word/frame clock polarity
ws_fs_rising
ꢆ
ꢉꢉꢉꢂꢉꢉꢉꢉ ꢉ: Word/frame starts at falling edge
ꢂ: Frame starts at rising edge
Data size / bit depth
ꢉꢉ: ꢁꢈ bit
data_size
ꢄ:ꢁ ꢉꢉꢉꢂꢉꢉꢉꢉ ꢉꢂ: ꢁꢉ bit
ꢂꢉ: ꢂꢃ bit
ꢂꢂ: ꢂꢊ bit
IꢁS/TDM word order
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: MSB is transmitted first
ꢉxꢉꢉꢂꢂ
ꢉxꢉꢉ lsb_first
ꢉ
ꢂ: LSB is transmitted first
Select channel (ꢉ‑ꢂꢊ) in received IꢁS/TDM
stream to pass on to DSP/amp channel ꢉ.
ꢉꢉꢉꢉꢉ: Channel ꢉ
ꢉxꢉꢉꢂꢁ
ꢉxꢉꢉ tdm_input_mapꢉ
ꢈ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉꢉꢉꢉꢂ: Channel ꢂ
..
ꢉꢂꢂꢂꢉ: Channel ꢂꢈ
ꢉꢂꢂꢂꢂ: Channel ꢂꢀ
Select channel (ꢉ‑ꢂꢊ) in received IꢁS/TDM
stream to pass on to DSP/amp channel ꢂ. See
tdm_input_mapꢉ register description for more
information.
ꢉxꢉꢉꢂꢄ
ꢉxꢉꢂ tdm_input_mapꢂ
ꢈ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢂ
Audio channel transmitted to IꢁS_DO pin in slot
ꢉ of IꢁS/TDM stream.
ꢉꢉꢉ: Zero
ꢉxꢉꢉꢂꢊ
ꢉxꢂA tdm_output_mapꢉ
ꢁ:ꢉ ꢉꢉꢉꢂꢂꢉꢂꢉ
ꢉꢉꢂ: High‑Z
ꢉꢂꢉ: DSP output channel ꢉ
ꢉꢂꢂ: DSP output channel ꢂ
Audio channel transmitted to IꢁS_DO pin in slot
tdm_output_mapꢂ
ꢀ:ꢄ ꢉꢉꢉꢂꢂꢉꢂꢉ ꢂ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
Datasheet
page ꢄꢊ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Audio channel transmitted to IꢁS_DO pin in slot
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢁ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
ꢉxꢉꢉꢂꢆ
ꢉxꢉꢉꢂꢃ
ꢉxꢉꢉꢂꢇ
ꢉxꢉꢉꢂA
ꢉxꢉꢉꢂB
ꢉxꢉꢉꢂC
ꢉxꢉꢉ tdm_output_mapꢁ
Audio channel transmitted to IꢁS_DO pin in slot
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢄ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
tdm_output_mapꢄ
Audio channel transmitted to IꢁS_DO pin in slot
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢈ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
ꢉxꢉꢉ tdm_output_mapꢈ
Audio channel transmitted to IꢁS_DO pin in slot
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢀ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
tdm_output_mapꢀ
Audio channel transmitted to IꢁS_DO pin in slot
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢊ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
ꢉxꢉꢉ tdm_output_mapꢊ
Audio channel transmitted to IꢁS_DO pin in slot
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢆ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
tdm_output_mapꢆ
Audio channel transmitted to IꢁS_DO pin in slot
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢃ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
ꢉxꢉꢉ tdm_output_mapꢃ
Audio channel transmitted to IꢁS_DO pin in slot
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢇ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
tdm_output_mapꢇ
Audio channel transmitted to IꢁS_DO pin in slot
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢂꢉ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
ꢉxꢉꢉ tdm_output_mapꢂꢉ
Audio channel transmitted to IꢁS_DO pin in slot
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢂꢂ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
tdm_output_mapꢂꢂ
Audio channel transmitted to IꢁS_DO pin in slot
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢂꢁ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
ꢉxꢉꢉ tdm_output_mapꢂꢁ
Audio channel transmitted to IꢁS_DO pin in slot
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢂꢄ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
tdm_output_mapꢂꢄ
Audio channel transmitted to IꢁS_DO pin in slot
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢂꢈ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
ꢉxꢉꢉꢂD ꢉxꢉꢉ tdm_output_mapꢂꢈ
Audio channel transmitted to IꢁS_DO pin in slot
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ ꢂꢀ of IꢁS/TDM stream. Setup is similar to
tdm_output_mapꢉ.
tdm_output_mapꢂꢀ
Selects if transmitted audio data should be a
copy of the received data.
ꢉxꢉꢉꢁꢊ
ꢉxꢉA tx_loopback
ꢉ
ꢁ
ꢂ
ꢄ
ꢉꢉꢉꢉꢂꢉꢂꢉ
ꢉ: IꢁS_DO is configured by tdm_output_map
ꢂ: IꢁS_DO is a copy of IꢁS_DI
IꢁS/TDM transmitter enable
tx_enable
ꢉꢉꢉꢉꢂꢉꢂꢉ ꢉ: Disabled
ꢂ: Enabled
IꢁS/TDM receiver enable (necessary to play
audio)
rx_enable
ꢉꢉꢉꢉꢂꢉꢂꢉ
ꢉ: Disabled
ꢂ: Enabled
Drive strength for IꢁS_DO pin
tx_strong_drive
ꢉꢉꢉꢉꢂꢉꢂꢉ ꢉ: Normal
ꢂ: Strong
Datasheet
page ꢄꢆ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Configure NCLIP pin as input for PWM
synchronization
ꢉxꢉꢉꢁꢆ
ꢉxꢉꢈ sync_in_enable
sync_out_enable
fast_sync
ꢉ
ꢉꢉꢉꢉꢉꢂꢉꢉ
ꢉ: Disable
ꢂ: Enable
Configure NCLIP pin as output (open‑drain) for
ꢂ
ꢉꢉꢉꢉꢉꢂꢉꢉ PWM synchronization.
ꢉ: Disable ꢂ: Enable
Select frequency of the PWM synchronization
signal
ꢁ
ꢉꢉꢉꢉꢉꢂꢉꢉ
ꢉ: Slow (fs/ꢂꢁꢁꢃꢃ)
ꢂ: Fast (fs/ꢂꢁ)
pmc
Value
Address Reset Name/Function
ꢉxꢉꢉBD ꢉxꢉꢉ PM_chꢉ
PM_chꢂ
Bits
Description
ꢁ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ Current selected Power Mode for channel ꢉ
ꢀ:ꢄ ꢉꢉꢉꢉꢉꢉꢉꢉ Current selected Power Mode for channel ꢂ
Channel ꢉ modulation index M detector output.
If register value is ꢉ, modulation index is ꢉ.ꢉ
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉxꢉꢉBE ꢉxꢉꢉ Mdetector_chꢉ
(minimum). If register value is ꢁꢀꢀ, modulation
index is ꢂ.ꢉ (full modulation)
Channel ꢂ modulation index M detector output.
If register value is ꢉ, modulation index is ꢉ.ꢉ
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉxꢉꢉBF
ꢉxꢉꢉ Mdetector_chꢂ
(minimum). If register value is ꢁꢀꢀ, modulation
index is ꢂ.ꢉ (full modulation)
prot_sys
Address Reset Name/Function
Bits
Value
Description
Error register reset
ꢉꢉꢉꢉꢉꢉꢉꢉ ꢉ: Do not reset error trigger
ꢂ: Reset error trigger
ꢉxꢉꢂꢉꢇ
ꢉxꢉꢉ reg.errTrig_reset
ꢂ
Instantaneous error vector ꢉ.
Bit ꢆ: Low temperature warning
Bit ꢊ: IꢁS input error
Bit ꢀ: PLL not locked
ꢉxꢉꢂꢂA
ꢉxꢉꢉ errVect_now.errVector_all__ꢉ
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ Bit ꢈ: PVDD over‑voltage
Bit ꢄ: Reserved
Bit ꢁ: PVDD under‑voltage
Bit ꢂ: Over‑temperature error
Bit ꢉ: Over‑temperature warning
Accumulated channel ꢉ error vector.
Bit ꢈ: Reserved
Bit ꢄ: DC error
ꢉxꢉꢂꢂC
ꢉxꢉꢉ errVect_acc.errVector_chꢉ
ꢈ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
Bit ꢁ: Flying cap error
Bit ꢂ: Reserved
Bit ꢉ: Over‑current protection
Accumulated channel ꢂ error vector. See
ꢈ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉxꢉꢂꢂD ꢉxꢉꢉ errVect_acc.errVector_chꢂ
description for errVect_acc.errVector_chꢉ
Accumulated error vector ꢉ.
Bit ꢆ: Low temperature warning
Bit ꢊ: IꢁS input error
Bit ꢀ: PLL not locked
Bit ꢈ: PVDD over‑voltage
ꢆ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉxꢉꢂꢂE
ꢉxꢉꢉ errVect_acc.errVector_all__ꢉ
Bit ꢄ: Reserved
Bit ꢁ: PVDD under‑voltage
Bit ꢂ: Over‑temperature error
Bit ꢉ: Over‑temperature warning
pa_hw
Address Reset Name/Function
Bits
Value
Description
Datasheet
page ꢄꢃ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
Unmute time delay from NMUTE=high to audio
playback.
ꢉxꢉꢂꢈꢁ
ꢉxꢉꢄ otp.unmute_cnt
ꢄ:ꢉ ꢉꢉꢉꢉꢉꢉꢂꢂ
ꢉꢉꢂꢂ: ꢄꢉꢉ ms
ꢂꢂꢉꢂ: ꢄꢉ ms (default)
Time/phase delay of PWM signal in ꢁꢁ.ꢀ degree
increments. Used with PWM sync to change
relative PWM phase of synchronized devices.
ꢉꢉꢉꢉꢉꢉꢉ: ꢉ deg
ꢉxꢉꢂꢀF
ꢉxꢉꢉ reg.pwm_phase
ꢊ:ꢉ ꢉꢉꢉꢉꢉꢉꢉꢉ
ꢉꢉꢉꢉꢉꢉꢂ: +ꢁꢁ.ꢀ deg
...
ꢉꢉꢉꢂꢂꢂꢂ: +ꢄꢄꢆ.ꢀ deg
ꢉꢉꢂꢉꢉꢉꢉ: +ꢄꢊꢉ deg (equivalent to ꢉ deg)
Datasheet
page ꢄꢇ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢄ Package Information
Dimensions are in millimeter unless otherwise specified.
Figure ꢀꢄ.ꢀ: QFN pad‑down ꢈꢉ‑pin MAꢁꢄꢉꢈPNS package dimensions. Leꢋ: Top view. Middle: Side view. Right: Bottom
view.
Figure ꢀꢄ.ꢁ: Package marking
Datasheet
page ꢈꢉ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
2.25
2.25
0.5
36×
0.25
40×
0.5
0.23
36×
40×
0.92
16×
0.56
8×
Pin1
4.7
1.68
8×
copper
solder mask
All dimensions are in units mm
stencil apertures
Figure ꢀꢄ.ꢂ: Recommended land pattern
Datasheet
page ꢈꢂ of ꢈꢁ
August, ꢁꢉꢁꢁ
MAꢁꢂꢅꢃPNS
MERUS™ Multilevel Switching Class‑D Audio Amplifier
ꢀꢇ Tape and Reel Information
Figure ꢀꢇ.ꢀ: Tape reel information
Pin1 marking
12
4
0.3
1.1
6.3
All dimensions are in units mm
The drawing is in compliance with ISO 128-30, Projection Method 1 [
]
Figure ꢀꢇ.ꢁ: Carrier tape information
Datasheet
page ꢈꢁ of ꢈꢁ
August, ꢁꢉꢁꢁ
MERUSªꢀMultilevelꢀSwitchingꢀClassꢀDꢀAudioꢀAmplifier
MA2304PNS
RevisionꢀHistory
MA2304PNS
Revision:ꢀ2022-08-23,ꢀRev.ꢀ2.2
Previous Revision
Revision Date
Subjects (major changes since last revision)
Release of final version
2.0
2.1
2.2
2022-07-06
2022-07-18
2022-08-23
Add filter condition on electrical characteristics
Add continuous output power data at 8 ohm load
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informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.
Information
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon
TechnologiesꢀOfficeꢀ(www.infineon.com).
Warnings
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
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Rev.ꢀ2.2,ꢀꢀ2022-08-23
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