MA5332MS [INFINEON]
MERUS™ 2 通道模拟输入 D 类音频放大器多芯片模块;
| 型号： | MA5332MS |
| 厂家： | 
Infineon |
| 描述： | MERUS™ 2 通道模拟输入 D 类音频放大器多芯片模块 放大器 音频放大器 |
| 文件： | 总60页 (文件大小：3254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MA5332MS
200W Stereo, Integrated Class D Amplifier
Features
2 channel analog input Class D audio amplifier in a small 7x7mm package
Very low RDS(ON) at 24.4 mΩ typical, enabling heatsink-less operation at 2x100W at 4Ω
95% efficiency Class D at 2x200W at 4Ω
PG- IQFN-42
Split or single power supply capable
Differential or single-ended input
Multiple configuration options: 2xSE, BTL, PSE (Parallel Single-Ended)
Over-current, over-temperature and under-voltage protections with self-reset feature
Start/stop click noise reduction
Clip and Fault reporting outputs
Applications
Multi-channel home theatre system
Studio monitor
Active speaker
Soundbar subwoofer
Marine amplifier
Aftermarket car audio system
General-purpose audio power amplifier
Total Harmonic Distortion
Product validation
Qualified for standard applications according to the
relevant tests of J-STD-020 and JESD22.
Product type
Package
7x7mm PG- IQFN-42
MA5332MS
Description
The MA5332MS offers the same or higher output power than monolithic alternatives without heatsink and 50%
less footprint. This MCM (multi-chip module) solution integrates 2 channel PWM controller, high voltage gate
driver, and 4 low RDS(ON) MOSFETs. Like its predecessor, IR43x2M, it includes standard Class D protection
features for reliable operation over various environmental conditions. As a powerful upgrade to IR43x2M and
other monolithic solutions, MA5332MS’ 7x7 mm PG- IQFN-42 package showcases the benefit of small footprint,
high power density, and heatsink-less operation.
Topology
Half-bridge / Full bridge
MA5332MS Output power(Half-
bridge,THD+N=10%, typical)
150 W in 2 Ω / 300 W in 4 Ω
200 W in 4 Ω / 400 W in 8 Ω
160 W in 6 Ω
*Residual noise (AES-17, IHF-A, typical)
250 μVrms
*THD+N (1kHz, 70W, 4 Ω, typical)
0.01 %
* In a typical application
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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MA5332MS
Table of contents
Table of contents
Features ........................................................................................................................................ 1
Applications................................................................................................................................... 1
Product validation.......................................................................................................................... 1
Description .................................................................................................................................... 1
Table of contents............................................................................................................................ 2
1
2
Qualification information........................................................................................................ 4
Device Comparison Table ........................................................................................................ 5
3
3.1
3.2
Pin Configuration................................................................................................................... 6
Lead assignments....................................................................................................................................6
Lead definitions.......................................................................................................................................7
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.9
Specifications ........................................................................................................................ 8
Absolute maximum ratings.....................................................................................................................8
Recommended operating conditions.....................................................................................................9
Electrical characteristics.......................................................................................................................10
Audio characteristics (SE) .....................................................................................................................13
Audio characteristics (BTL) ...................................................................................................................13
Audio characteristics (PSE) ...................................................................................................................14
Typical Audio characteristics (SE) ........................................................................................................15
Power vs. THD+N..............................................................................................................................15
Frequency vs. THD+N.......................................................................................................................16
Frequency response.........................................................................................................................16
Noise floor ........................................................................................................................................17
Efficiency ..........................................................................................................................................17
Typical Audio characteristics (BTL) ......................................................................................................18
Power vs. THD+N..............................................................................................................................18
Frequency vs. THD+N.......................................................................................................................19
Frequency response.........................................................................................................................19
Noise floor ........................................................................................................................................20
Typical Audio characteristics (PSE) ......................................................................................................21
Power vs. THD+N..............................................................................................................................21
Frequency vs. THD+N.......................................................................................................................22
Frequency response.........................................................................................................................22
Noise floor ........................................................................................................................................23
4.9.1
4.9.2
4.9.3
4.9.4
5
5.1
5.2
Thermal information .............................................................................................................24
Peak power duration thermal information ..........................................................................................24
Heatsink information ............................................................................................................................28
6
7
8
Functional block diagram.......................................................................................................29
Typical Implementation.........................................................................................................30
Input / Output pin equivalent circuit diagrams .........................................................................33
9
PWM Modulator Design ..........................................................................................................34
Input Section .........................................................................................................................................34
Control Loop Design..............................................................................................................................35
PWM Frequency.....................................................................................................................................35
Clock Synchronization ..........................................................................................................................36
Click Noise Elimination .........................................................................................................................37
9.1
9.2
9.3
9.4
9.5
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9.6
Differential Input ...................................................................................................................................38
10
Operational Mode..................................................................................................................39
10.1
Self-oscillation Start-up Condition.......................................................................................................39
11
Protections...........................................................................................................................40
Self-Reset Protection .......................................................................................................................41
Designing Ct......................................................................................................................................42
Shutdown Input ...............................................................................................................................42
Latched Protection...........................................................................................................................43
Interfacing with System Controller .................................................................................................43
Over Current Protection (OCP) .............................................................................................................44
Over Temperature Protection (OTP) ....................................................................................................45
Under Voltage Protection (UVP) ...........................................................................................................45
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.2
11.3
11.4
12
12.1
12.2
Status Output .......................................................................................................................46
Fault Output ..........................................................................................................................................46
CLIP Output ...........................................................................................................................................47
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.3
Power Supply Design.............................................................................................................48
Supplying VAA and VSS .........................................................................................................................48
Supplying VCC and VB...........................................................................................................................48
Choosing Bootstrap Capacitance....................................................................................................49
Choosing Bootstrap Diode...............................................................................................................49
Charging VBS Prior to Start................................................................................................................49
Power Supply Sequence .......................................................................................................................51
14
15
Package details.....................................................................................................................52
Board mounting, part marking, and ordering information .........................................................55
Revision history.............................................................................................................................60
Datasheet
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1
Qualification information
Qualification Level (1)
Standard (2)
Qualified for standard applications according to the relevant tests
of J-STD-020 and JESD22
Moisture Sensitivity Level (MSL) (3)
MSL3
(per IPC/JEDEC J-STD-020)
Class C2a
(per JEDEC standard JS-002)
ESD
Charge Device
Model
Human Body
Model
Class 1B
(per JEDEC standard JS-001)
Class I, Level A
(per JESD78)
Yes
IC Latch-Up Test
RoHS Compliant
Note:
1. Qualification standards can be found at Infineon’s web site http://www.infineon.com/
2. Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
3. Higher MSL ratings may be available for the specific package types listed here. Please contact your International
Rectifier sales representative for further information.
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2
Device Comparison Table
Table 1
Device Name
MA5332MS
IR4302M
IR4322M
IR4312M
IR4301M
IR4321M
IR4311M
Description
200W (4 Ω)*2 channel integrated analog input Class D audio Amplifier
130W (4 Ω)*2 channel integrated analog input Class D audio Amplifier
100W (2 Ω)*2 channel integrated analog input Class D audio Amplifier
35W (4 Ω)*2 channel integrated analog input Class D audio Amplifier
160W (4 Ω) single-channel integrated analog input Class D audio Amplifier
135W (2 Ω) single-channel integrated analog input Class D audio Amplifier
35W (4 Ω) single-channel integrated analog input Class D audio Amplifier
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3
Pin Configuration
3.1
Lead assignments
Figure 1
Lead assignments
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3.2
Lead definitions
Description
Pin # Symbol
1
2
3
4
5
CLIP
Clipping detection output, open drain, referenced to GND
CH2 PWM comparator input
COMP2
IN-2
CH2 Analog inverting input
IN+2
GND
CH2 Analog non-inverting input
GND for internal shunt zener diodes to VAA and VSS, a reference to FAULT and CLIP
outputs.
6
VSS
Floating input negative supply
7
VAA
Floating input positive supply
8
IN+1
IN-1
COMP1
CSD
FAULT
VCC
COM
CSH1
VB1
CH1 Analog non-inverting input
9
CH1 Analog inverting input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CH1 PWM comparator input
Shutdown timing capacitor / shutdown input
Fault reporting output, open drain, referenced to GND
Low side supply
Low side supply return, internally connected to pin 27
CH1 High side over current sensing input, referenced to VS1
CH1 High side floating supply
VS1
CH1 PWM output, internally connected to pin 19
CH1 Positive power supply
VP1
VS1
CH1 PWM output
VN1
VN2
VS2
CH1 Negative power supply, connect to COM externally
CH2 Negative power supply, connect to COM externally
CH2 PWM output, internally connected to pin 24
CH2 Positive power supply
VP2
VS2
CH2 PWM output
VB2
CH2 High side floating supply
CSH2
COM
NC
CH2 High side over current sensing input, referenced to VS2
Low side supply return, internally connected to pin 14
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4
Specifications
4.1
Absolute maximum ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM=VN1=VN2; all currents are defined positive into
any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still
air conditions.
Symbol Definition
Min
-
Max
100
Units
VPn
VBn
VSn
VCSHn
VCC
VAA
VSS
Positive power supply rail voltage, n=1-2
High side floating supply voltage
High side floating supply voltage(2), n=1-2
CSH pin input voltage, n=1-2
Low side supply voltage(2)
Floating input positive supply voltage(2)
Floating input negative supply voltage(2)
-0.3
115
VBn -15
VSn -0.3
-0.3
VBn +0.3
VBn +0.3
15
-0.3
110
-1
GND +0.3
(See ISSZ)
VSS -0.3
VIN+n
IINn
Floating input supply ground voltage , n=1-2
Input current between IN- and IN+ pins(1), n=1-2
CSD pin input voltage
VAA +0.3
±3
-
mA
V
VCSD
VCOMPn
VCLIP
ICLIP
VSS -0.3
VAA +0.3
VAA +0.3
VAA +0.3
5
COMP pin input voltage, n=1-2
VSS -0.3
CLIP pin input voltage
GND -0.3
CLIP pin sinking current
-
mA
V
VFAULT
IFAULT
IAAZ
FAULT pin input voltage
GND -0.3
VAA +0.3
5
FAULT pin sinking current
-
-
-
-
-
-
-
Floating input supply zener clamp current(2)
Floating input negative supply zener clamp current(2)
Low side supply zener clamp current(2)
Floating supply zener clamp current(2), n=1-2
20
ISSZ
20
mA
ICCZ
20
IBSZn
20
dVSn/dt Allowable Vs voltage slew rate, n=1-2
50
V/ns
Allowable Vss voltage slew rate(3)
dVSS/dt
50
V/ms
Id@ 25ºC
Continuous output current, from VPn to VSn, VSn to VNn,
VCC=10V, VBn-VSn=10V
-
-
-
16
10
64
Id@ 100ºC Continuous output current, from VPn to VSn, VSn to VNn,
VCC=10V, VBn-VSn=10V
A
IDM
Pulsed output current, from VPn to VSn, VSn to VNn, VCC=10V,
VBn-VSn=10V(5)
Power dissipation(4)@ TC = 25C
Thermal resistance, junction to case(4)
Control IC junction temperature
FET junction temperature
W
Pd
-
-
-
-
25
C/W
RthJC
TJIC
5
150
150
C
TJFET
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TS
TL
Storage Temperature
-55
-
150
300
Lead temperature (Soldering, 10 seconds)
Note:
1. IN- and IN+ contain clamping diodes between the two pins.
2. VAA -VSS, Vcc-COM and VBn-VSn contain internal shunt zener diodes. Note that the voltage ratings of these can be limited by
the clamping current.
3. For the rising and falling edges of step signal of 10V. Vss=15V to 100V.
4. Per MOSFET.
5. Repetitive rating, pulse width limited by maximum junction temperature.
4.2
Recommended operating conditions
For proper operation, the device should be used within the recommended conditions below. The Vss and Vsn
offset ratings are tested with supplies biased at COM=VN1=VN2, VAA-VSS=9.6V, VCC=12V and VBn-VSn=12V. All
voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead.
Symbol
Definition
Min
Max
Units
Positive power supply voltage, n=1-2, without
heatsink
MA5332MS
MA5332MS
-
60
VPn
Positive power supply voltage, n=1-2, with
heatsink
-
80
VBn
VSn
High side floating supply absolute voltage, n=1-2
High side floating supply offset voltage, n=1-2
VSn +10
VSn +14
100
V
(6)
MA5332MS
MA5332MS
Floating input positive supply voltage(7)
VAA
VSS
VSS +9.0
0
VSS + 9.8
100
Floating input negative supply voltage(7)
Floating input supply zener clamp current(7)
IAAZ
ISSZ
VCC
1
1
10
15
15
15
mA
Floating input negative supply zener clamp current(7)
Low side fixed supply voltage
VIC
IN- and IN+ pins common mode input voltage
Inverting input voltage, n=1-2
CSD pin input voltage
VSS + 2
VIN+ -0.5
VSS
VAA - 2
VIN+ +0.5
VAA
V
VIN-n
VCSD
VCOMPn
COMP pin input voltage, n=1-2
VSS
VAA
CCOMPn
COMP pin phase compensation capacitor to GND , n=1-2
1
-
nF
VCSHn
fSW
TJ_IC
CSH pin input voltage, n=1-2
Switching frequency
Juction temperature of controller IC
VSn
-
-40
VBn
500
100
V
kHz
C
Note:
6. Logic operational for Vs equal to –5V to +100V. Logic state held for Vs equal to –5V to –VBS.
7. GND input voltage is limited by IAAZ and ISSZ
.
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4.3
Electrical characteristics
Unless otherwise specified, the following apply:
VCC,VBS= 12 V
VSS=VS1=VS2=VN1=VN2=COM=0V
VAA=9.6V
TA=25C
Table 2
Symbol
Electrical characteristics
Definition
Min
Typ
Max
Units
Test conditions
Low-side supply
Vcc supply UVLO positive
threshold
UVCC+
UVCC-
8.4
8.2
8.9
8.7
9.4
9.2
V
V
Vcc supply UVLO negative
threshold
UVCCHYS
IQCC
UVCC hysteresis
-
-
-
0.2
-
-
V
Low side quiescent current
Low side supply current
3
-
mA
mA
ICC
10
f=400kHz
ICC=5mA
Low side zener diode clamp
voltage, n=1-2
VCLAMPL
n
14.7
15.3
8.5
16.2
V
High-side floating supply
High side well UVLO positive
threshold, n=1-2
UVBS+n
8.0
9.0
V
High side well UVLO negative
threshold, n=1-2
UVBS-n
UVBSHYSn
IQBSn
7.8
8.3
0.2
-
8.8
-
V
UVBS hysteresis, n=1-2
-
-
V
High side quiescent current,
n=1-2
2.4
mA
High side quiescent current,
with CSH pin open n=1-2
IQBSn_OFF-CSH
VCLAMPHn
350
500
650
uA
V
High side zener diode clamp
voltage, n=1-2
14.7
15.3
16.2
IBS=5mA
Floating input supply
VA+, VA- floating supply UVLO
positive threshold from VSS
VSS =0V, GND pin
floating
UVAA+
UVAA-
UVAAHYS
IQAA0
8.2
7.7
-
8.7
8.2
0.5
1.5
9.2
8.7
-
V
VA+, VA- floating supply UVLO
negative threshold from VSS
VSS =0V, GND pin
floating
V
VSS =0V, GND pin
floating
UVAA hysteresis
V
VAA=9.6V, VSS =0V,
VCSD =VSS
Floating Input positive quiescent
supply current
-
3
mA
VAA=9.6V, VSS =0V,
VCSD =VAA
Floating Input positive quiescent
supply current
IQAA1
-
4
6
mA
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VAA=9.6V, VSS =0V,
VCSD =GND
Floating Input positive quiescent
supply current
IQAA2
ILKM
-
-
5
-
7.5
50
mA
µA
VAA=VSS=VGND
100V
=
Floating input side to Low side
leakage current
IAA=5mA,
ISS=5mA,
VGND=0V,
VAA floating supply zener diode
clamp voltage, positive, with
respect to GND
VCLAMPM+
4.9
5.1
5.4
V
V
VCSD =VSS
IAA=5mA,
ISS=5mA,
VGND=0V,
VSS floating supply zener diode
clamp voltage, negative, with
respect to GND
VCLAMPM-
-5.4
-5.1
-4.9
VCSD =VSS
Audio input (VGND=0, VAA=4.8V, VSS=-4.8V)
VOSn
IBINn
Input offset voltage, n=1-2
Input bias current, n=1-2
-18
-
0
-
18
40
mV
nA
Small signal bandwidth in OTA, n=1-
2
GBWn
-
9
-
MHz
CCOMP=1nF, Rf=0
VIN+=0V, VIN-
=10mV
gmn
GVn
OTA transconductance, n=1-2
-
10
-
-
-
mS
dB
OTA gain, n=1-2
50
CHn OTA input noise voltage,
n=1-2
VNrmsn
-
200
330
mVrms
PWM
PWM comparator threshold in
COMP
(VAA -
VSS)/2
VthPWM
-
-
V
COMP pin star-up local oscillation
frequency, n=1-2
fOTAn
0.7
1.0
1.5
MHz
VCSD =GND
COMP to VS rising edge propagation
delay, n=1-2
Ton_n
-
-
370
-
-
ns
ns
COMP to VS trailing edge
propagation delay, n=1-2
Toff_n
DTn
320
50
Deadtime: Low-side turn-off to
High-side turn-on (DTLO-HO) & High-
side turn-off to Low-side turn-on
(DTHO-LO) , n=1-2
VP=30V,
VN=-30V,
-
-
ns
Power MOSFET (FET1, FET2, FET3, FET4)
At Tj=25°C, unless otherwise specified
VGS=0V,
ID=250uA
(8)
Drain-to-Source breakdown voltage
100
-
-
V
V(BR)DSS
ID=3.3A, VGS=10V
RDS(ON)
Qg
FET on resistance
Total gate charge
-
-
24.4
12.7
30.5
19
mΩ
nC
VGS=10V
VP=100V(8)
VCSD =VSS
,
ILK0
VP leakage current, VS=VN
-
-
20
µA
Protection
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Over current detection Positive
IOCPn
-
40
-
A
A
V
threshold, n=1-2(8)
Over current detection Negative
IOCNn
-
-40
-
threshold, n=1-2(9)
CSD pin shutdown release
threshold
Vth1
0.62xVAA
0.70xVAA
0.78xVAA
Vth2
ICSD+
ICSD-
CSD pin self-reset threshold
CSD pin discharge current
CSD pin charge current
0.26xVAA
70
0.30xVAA
100
0.34xVAA
130
V
VCSD = VSS +4.8V
VCSD = VSS +4.8V
µA
µA
70
100
130
Shutdown propagation delay from
VS < Vth1 to Shutdown, n=1-2
COMP = VSS
COMP = VSS
COMP = VSS
tSDn
-
-
250
ns
ns
ns
V
CHn propagation delay time from
IOn > IOCPn to Shutdown, n=1-2
tOCPn
-
-
500
CHn propagation delay time from
IOn < IOCNn to Shutdown, n=1-2
tOCNn
-
-
500
Clip detection positive threshold in
COMP
Vth+CLIP
Vth-CLIP
tCLIP
0.85xVAA
0.90xVAA
0.95xVAA
Clip detection negative threshold in
COMP
0.05xVAA
0.10xVAA
0.15xVAA
V
Clipping detection propagation
delay
-
40
3
-
-
-
-
ns
us
ºC
ºC
Clipping detection minimum output
duration
tCLIPmin
TSD
-
Over-temperature shutdown
threshold in controller IC
100
-
-
Over-temperature shutdown
threshold hysteresis
TSDHYS
7
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4.4
Audio characteristics (SE)
Table 3
Parameter
Po Power output per channel(10)
Test conditions
Typ
160
200
190
150
120
150
140
110
250
Unit
RL= 6Ω, 10%THD+N, Vbus = ± 40 V
RL= 4Ω, 10%THD+N, Vbus = ± 36.5 V
RL= 3Ω, 10%THD+N, Vbus = ± 31.5 V
RL= 2Ω, 10%THD+N, Vbus = ± 23 V
RL= 6Ω, 1%THD+N, Vbus = ± 40 V
RL= 4Ω, 1%THD+N, Vbus = ± 36.5 V
RL= 3Ω, 1%THD+N, Vbus = ± 31.5 V
RL= 2Ω, 1%THD+N, Vbus = ± 23V
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω
W
Residual noise(AES-17, IHF-A,
typical)
uV
Idling supply current
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω
+55
-80
95
mA
Efficiency(11)
EVAL_AUDAMP25, Vbus = ± 36.5 V,
Pout=200W, RL= 4Ω
%
Note:
8. Vp changes over temperature at a rate of 50mV/K compared to Tj=25°C.
9. Over-current protection threshold measured under Tj=25°C condition.
10. Tested with heatsink (digikey part number: V8818V)
11. Class D stage only
4.5
Audio characteristics (BTL)
Table 4
Parameter
Po Power output per channel(9)
Test conditions
Typ
400
380
300
300
280
220
350
Unit
RL= 8Ω, 10%THD+N, Vbus = ± 36.5 V
RL= 6Ω, 10%THD+N, Vbus = ± 31.5 V
RL= 4Ω, 10%THD+N, Vbus = ± 23 V
RL= 8Ω, 1%THD+N, Vbus = ± 36.5 V
RL= 6Ω, 1%THD+N, Vbus = ± 31.5 V
RL= 4Ω, 1%THD+N, Vbus = ± 23V
W
Residual noise(AES-17, IHF-A,
typical)
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω
uV
Idling supply current
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 8Ω
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 8Ω
+55
-80
95
mA
Efficiency(10)
%
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4.6
Audio characteristics (PSE)
Table 5
Parameter
Po Power output per channel(9)
Test conditions
Typ
400
300
250
Unit
RL= 2Ω, 10%THD+N, Vbus = ± 36.5 V
RL= 2Ω, 1%THD+N, Vbus = ± 36.5V
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω
W
Residual noise(AES-17, IHF-A,
typical)
uV
Idling supply current
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω
EVAL_AUDAMP25 , Vbus = ± 36.5 V ,RL= 4Ω
+55
-80
95
mA
Efficiency(10)
%
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4.7
Typical Audio characteristics (SE)
Test conditions:
All Measurements taken at Sine wave frequency= 1 kHz, AES17+ AUX-0025 measurement filters.
Vbus = ± 40 V, Load impedance = 6 Ω, FPWM = 400 kHz
Vbus = ± 36.5 V, Load impedance = 4 Ω, FPWM = 400 kHz
Vbus = ± 31.5 V, Load impedance = 3 Ω, FPWM = 400 kHz
Vbus = ± 23 V, Load impedance = 2 Ω, FPWM = 400 kHz
4.7.1
Power vs. THD+N
Figure 2
Power vs. THD+N
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4.7.2
Frequency vs. THD+N
Figure 3
Frequency vs. THD+N @1W
4.7.3
Frequency response
Test conditions:
Output power = 1 W, LPF = 22uH+0.47uF
Figure 4
Frequency response
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4.7.4
Noise floor
Figure 5
Noise floor
4.7.5
Efficiency
Figure 6
Efficiency 4 Ω load
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4.8
Typical Audio characteristics (BTL)
Test conditions:
All Measurements taken at Sine wave frequency= 1 kHz, AES17+ AUX-0025 measurement filters.
Vbus = ± 40 V, Load impedance = 8 Ω, FPWM = 400 kHz
Vbus = ± 31.5 V, Load impedance = 6 Ω, FPWM = 400 kHz
Vbus = ± 23 V, Load impedance = 4 Ω, FPWM = 400 kHz
4.8.1
Power vs. THD+N
Figure 7
Power vs. THD+N
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4.8.2
Frequency vs. THD+N
Figure 8
Frequency vs. THD+N @1W
4.8.3
Frequency response
Test conditions:
Output power = 1 W, fixed LPF 22uH+0.47uF
Figure 9
Frequency response
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4.8.4
Noise floor
Test conditions:
No input signal
Figure 10
Noise floor
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4.9
Typical Audio characteristics (PSE)
Test conditions:
All Measurements taken at Sine wave frequency= 1 kHz, AES17+ AUX-0025 measurement filters.
Vbus = ± 36.5 V, Load impedance = 2 Ω, FPWM = 400 kHz
4.9.1
Power vs. THD+N
Figure 11
Power vs. THD+N
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4.9.2
Frequency vs. THD+N
Figure 12
Frequency vs. THD+N @1W
4.9.3
Frequency response
Test conditions:
Output power = 1 W, fixed LPF 22uH+0.47uF
Figure 13
Frequency response
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4.9.4
Noise floor
Test conditions:
No input signal
Figure 14
Noise floor
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5
Thermal information
Benefits from unique co-packaging technique and superior MOSFET technology, MA5332MS has the
best-in-class thermal performance, Peak power duration. It can deliver 100W*2/4Ω even without a heatsink.
5.1
Peak power duration thermal information
Test conditions:
All Measurements are taken at sinewave frequency= 1 kHz, AES17+ AUX-0025 measurement filters. Input signal
= 1 kHz, FPWM = 400 kHz.
Tests are based on Eval_AUDAMP25 board when both channels are driven.
Table 6
Peak power with heatsink
10 percent THD+N power (W) Duration
Load (Ω) ±Vbus (V)
6
4
3
2
40
160
200
190
150
More than 1 minute without thermal shutdown
36.5
31.5
23
Figure 15
Peak power Pout = 164 W with 6 Ω load ±40 V
Note:
Maximum temperature 68.9°C at 1 minute.
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Figure 16
Peak power Pout = 200 W with 4 Ω load ±36.5 V
Note:
Maximum temperature 105°C at 1 minute.
Figure 17
Peak power Pout = 194 W with 3 Ω load ±31.5 V
Note:
Maximum temperature 130°C at 1 minute.
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Figure 18
Peak power Pout = 150 W with 2 Ω load ±23 V
Note:
Maximum temperature 154°C at 1 minute.
Table 7
Peak power without heatsink
Load (Ω) ±Vbus (V)
10 percent THD+N power
(W)
Duration
4
2
26.5
13.7
100
50
More than 1 minute without thermal shutdown
Figure 19
Peak power Pout = 102 W with 4 Ω load ±26.5 V
Note:
Maximum temperature 146.7°C at 1 minute.
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Figure 20
Peak power Pout = 55 W with 2 Ω load ±13.7 V
Note:
Maximum temperature 142.8°C at 1 minute.
Table 8
1/8 power test with heatsink
Load (Ω)
±Vbus (V)
40
Max. T-case (°C)
1/8 power (W)
Duration (minutes)
6
4
3
2
71.6
85.6
87.2
84.8
16.5
19.8
19.7
15
30
30
30
30
36.5
31.5
23
Table 9
1/8 power test without heatsink
Load (Ω)
±Vbus (V)
22.7
Max. T-case (°C)
1/8 power (W)
7.12
Duration (minutes)
4
2
84.6
76.1
30
30
13.7
4.88
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5.2
Heatsink information
Heatsink: V8818V
Thermal pad: BER161-ND
Figure 21
Heatsink installation
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6
Functional block diagram
Figure 22 Block diagram
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7
Typical Implementation
The MA5332MS can be designed as single-ended, BTL or parallel single ended (PSE) output configuration, using
a single or split power supply. Here are examples of typical configurations.
A configuration for single-ended input with split power supply sets the base example. The front end section
refers to GND which is common to speaker output GND.
+B
EXT CLK
(OPTIONAL)
CLIP
COMP2
CH2 INPUT
IN-2
VS2
VN2
CH2 OUTPUT
Speaker
IN+2
GND
VSS
VAA
IN+1
VN1
VS1
Speaker
CH1 INPUT
IN-1
COMP1
CSD
CH1 OUTPUT
FAULT
VCC
-B
Figure 23 Inverting amplifier with Split Power Supply
+B
EXT CLK
(OPTIONAL)
CLIP
COMP2
CH2 IN+
CH2 IN-
IN-2
IN+2
VS2
CH2 OUTPUT
Speaker
VN2
GND
VSS
VAA
VN1
VS1
CH1 IN-
CH1 IN+
IN+1
Speaker
IN-1
COMP1
CSD
CH1 OUTPUT
FAULT
VCC
-B
Figure 24 Differential amplifier with Split Power Supply
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The single-supply configuration uses a virtual GND which sits in the middle of the power supply rail. The front-
end section of the amplifier refers to the virtual GND as a reference. This method uses differential input to
receive an input signal from a different voltage potential. It is recommended to allow input capacitors to fully
settle to steady-state values before releasing the CSD pin to start PWM oscillation. The load current and
inductor ripple current flow through the bus splitting capacitor.
+B
EXT CLK
(OPTIONAL)
CLIP
COMP2
CH2 IN+
IN-2
VS2
VN2
CH2 OUTPUT
Speaker
CH2 IN-
IN+2
GND
VSS
VAA
IN+1
VN1
VS1
CH1 IN-
CH1 IN+
Speaker
IN-1
COMP1
CSD
CH1 OUTPUT
FAULT
VCC
Figure 25 Typical Application Circuit with Single Power Supply
Balanced Tied Load (BTL) output takes two output legs for speaker output. It doubles output power with
double load impedance. Any load current does not flow through supply dividing capacitor; therefore BTL
configuration is free from GND fluctuations. Also, the bus splitting capacitor can be much smaller. Higher
output power and absence of GND fluctuation make BTL suitable for subwoofer applications.
+B
EXT CLK
(OPTIONAL)
CLIP
COMP2
INPUT-
VS2
VN2
IN-2
IN+2
GND
VSS
VAA
IN+1
Speaker
VN1
VS1
INPUT+
IN-1
COMP1
CSD
FAULT
VCC
-B
Figure 26 Typical Bridged Tied Load (BTL) Output Application with Split Power Supply
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+B
EXT CLK
(OPTIONAL)
CLIP
COMP2
IN-2
INPUT-
VS2
VN2
IN+2
GND
VSS
VAA
IN+1
Speaker
VN1
VS1
10V
INPUT+
IN-1
COMP1
CSD
FAULT
10V
Figure 27 Typical Bridged Tied Load (BTL) Output Application with Single Power Supply
Parallel Single Ended (PSE) output parallels two channels’ output legs for one speaker output. It doubles
output current and makes it easier to drive a low impedance load. Higher output current with lower bus voltage
makes PSE suitable for subwoofer applications.
+B
CLIP
COMP2
INPUT
VS2
VN2
IN-2
IN+2
GND
VSS
VAA
IN+1
Speaker
VN1
VS1
IN-1
COMP1
CSD
FAULT
VCC
-B
Figure 28 PSE amplifier with Split Power Supply
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8
Input / Output pin equivalent circuit diagrams
,
Figure 29 Input/output pin equivalent circuit diagrams
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9
PWM Modulator Design
The open-access front-end configuration of MA5332MS enables many ways to implement a PWM modulator.
This section explains how PWM modulation works based on an example of a self-oscillating PWM modulator in
a typical application.
Figure 30 MA5332MS Typical Control Loop Design
9.1
Input Section
The audio input stage of MA5332MS forms an inverting error amplifier. The voltage gain of the amplifier, GV, is
determined by the ratio between input resistor RIN and feedback resistor RFB.
RFB
G
V
R
IN
Since the feedback resistor RFB is part of an integrator time constant, which determines switching frequency,
changing the overall voltage gain by RIN is simpler and therefore recommended. Note that the input impedance
of the amplifier is equal to the input resistor RIN.
A DC blocking capacitor C3 should be connected in series with RIN to minimize the DC offset voltage on the output.
Due to potential distortion, a ceramic capacitor is not recommended. Minimizing the DC offset is essential to
minimize the audible noise during power-ON and -OFF.
The connection of the non-inverting input IN+ is a reference for the error amplifier, and thus is crucial for audio
performance. Connect IN+ to the signal reference ground in the system, which has the same potential as the
negative terminal of the speaker output.
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9.2
Control Loop Design
The MA5332MS allows the user to choose from numerous methods of PWM modulator implementations. In this
section, all the explanations are based on a typical application circuit of a self-oscillating
9.3
PWM Frequency
Choosing the switching frequency entails making a trade-off between many aspects. At lower switching
frequency, conduction losses in the MOSFET stage increases due to higher inductor ripple current. The output
carrier leakage in the speaker output increases. At higher switching frequency, the efficiency degrades due to
higher switching losses. Higher switching frequency supports wider audio bandwidth. The inductor ripple
decreases yet core loss might increase. For these reasons, 400kHz is chosen for a typical design example.
Self-oscillating frequency has little influence from the bus voltage and input resistance RIN. Note that the
nature of a self-oscillating PWM is for the switching frequency to decrease as PWM modulation deviates from
idling.
Table 10 summarizes suggested values of components for a given target self-oscillating frequency. The front-
end operational transconductance amplifier (OTA) output has limited voltage and current compliances. This
set of component values ensures that OTA operates within its linear region for optimal THD+N performance. In
case the target frequency is somewhere in between the frequencies listed in Table 10, simply adjust the
frequency by tweaking R1.
Table 10
External Component Values vs. Self-Oscillation Frequency
Target Self-Oscillation
Frequency (kHz)
C1=C2 (nF)
R1 (ohms)
200
500
450
400
350
300
250
200
150
100
70
2.2
2.2
2.2
2.2
2.2
2.2
4.7
10
165
141
124
115
102
41.2
20.0
14.0
4.42
10
22
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9.4
Clock Synchronization
In the PWM control loop design example, the self-oscillating frequency can be set and synchronized to an external
clock. Through a set of resistors and a capacitor, the external clock injects periodic pulsating charges into the
integrator, forcing oscillation to lock up to the external clock frequency. A typical setup with 5 Vp-p 50% duty
clock signal uses RCK=22 kΩ and CCK=100 pF in Figure 31. To maximize audio performance, the self-running
frequency without clock injection should be 20 to 30% higher than the external clock frequency.
Figure 31 External Clock Synchronization
Figure 32 shows how a self-oscillating frequency locks up to an external clock frequency. A design of a 400 kHz
self-oscillating frequency synchronizes to an external clock whose frequency is within the red border lines.
600
500
400
300
200
100
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
Duty Cycle
Figure 32 Typical Lock Range to External Clock (RCK=22 kΩ and CCK=100 pF)
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9.5
Click Noise Elimination
The MA5332MS has a unique feature that minimizes power-ON and -OFF audible click noise. When CSD is in
between Vth1 and Vth2 during start-up, an internal closed loop around the OTA enables an oscillation that
generates voltages at COMP and IN-, bringing them to steady-state values. It runs at around 1 MHz, independent
from the switching oscillation.
Figure 33 Audible Click Noise Elimination
As a result, all capacitive components connected to COMP and IN- pins, such as C1, C2, C3 and Cc in Figure 33,
are pre-charged to their steady-state values during the start-up sequence. This allows instant settling of closed-
loop PWM operation.
To utilize the click noise reduction function, the following conditions must be met.
1. CSD pin has slow enough ramp up from Vth1 to Vth2 such that the voltages in the capacitors can settle
to their target values.
2. High-side bootstrap power supply needs to be charged up prior to starting oscillation.
3. Audio input has to be zero.
4. For internal local loop to override external feedback during the startup period, DC offset at speaker
output prior to shutdown release has to satisfy the following condition.
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9.6
Differential Input
Figure 34 shows an example of a differential input configuration. This design is useful in a single supply
configuration. Use RIN1=RIN2, RFB1=RFB2, C3=C4.
Voltage gain is given by a ratio between RIN and RFB.
RFB
G
V
R
IN
Figure 34 Differential Input
Although component values in the feedback network are balanced between inverting and non-inverting inputs,
the integration capacitor path in the non-inverting input creates unbalance at high frequencies, causing slightly
higher distortion compared to an unbalanced input configuration. To improve the THD degradations, place
optional RC network R2=R1 and C5=C1.
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10
Operational Mode
The CSD pin determines the operational mode of the MA5332MS as shown in Figure 35. The OTA has three
operational modes: shutdown, pop-less startup and normal operation; while the gate driver section has two
modes: shutdown and normal operation.
When VCSD < Vth2, the IC is in shutdown mode and the input OTA is cut off. When Vth2< VCSD < Vth1, the output
MOSFETs are still in shutdown mode. The OTA is activated and starts local oscillation for pop-less start-up which
pre-biases all the capacitive components in the error amplifier. When VCSD>Vth1, the MA5332MS enters normal
operation mode and PWM operation starts.
Figure 35 VCSD and Operational Mode
10.1
Self-oscillation Start-up Condition
The MA5332MS requires the following conditions in order for pop-less startup to work properly.
-
All the control power supplies, VAA, VSS, VCC and VBS are above the under-voltage lockout
thresholds.
CSD pin voltage is over Vth1 threshold.
iIN iFB
-
-
VIN
RIN
VB
RFB
i
i
FB
Where
,
.
IN
-
The duration CSD voltage transitioning from Vth2 to Vth1 is long enough to pre-charge input and
integration capacitors around OTA section.
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11
Protections
Figure 36 Protection Functional Block Diagram
The internal protection control block dictates the operational modes, normal or shutdown, using the input of the
CSD pin. In shutdown mode, the controller IC turns off internal power MOSFETs.
The CSD pin provides five functions.
1. Power up delay timer
2. Self-reset timer
3. Shutdown input
4. Latched protection configuration
5. Shutdown status output (host I/F)
The CSD pin cannot be paralleled with another MA5332MS directly.
The operating statuses of the protection features are shown in Table 11.
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Table 11
Events and Actions of CSD and FAULT
Event
CSD
Recycle
n/a
n/a
n/a
n/a
FAULT
L until CSD>Vth1
n/a
L at VAA<UVAA
L at VAA<UVAA
n/a
UVCC, rising edge
UVCC, falling edge
UVAA, rising edge
UVAA, falling edge
UVBS, rising edge
UVBS, falling edge
n/a
Keep recycling until OCP
is reset
n/a
Over Current Protection
Clip Detection
Held L until OCP is reset
n/a
n/a
Over Temperature
Protection
Keep recycling until OTP
is reset
*CSD recycle: CSD pin voltage
discharges down to Vth2 and charges
back to VAA, if CSD pin is configured
as self reset protection.
Held L until OTP is reset
11.1.1
Self-Reset Protection
Attaching a capacitor between CSD and VSS configures the MA5332MS self-reset protection mode.
Upon an OCP event, the CSD pin discharges the external capacitor voltage VCSD down to the lower threshold Vth2
to reset the internal shutdown latch. Then, the CSD pin begins to charge the external capacitor, Ct, in an attempt
to resume operation. Once the voltage of the CSD pin rises above the upper threshold, Vth1, the IC resumes normal
operation.
Figure 37 Self-Reset Protection Configuration
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11.1.2
Designing Ct
The external timing capacitor, Ct, programs self-reset timings: tRESET and tSU.
tRESET is the time that elapses from when the IC enters the shutdown mode to the time when the IC
resumes operation. tRESET should be long enough to avoid over heating the MOSFETs from the repetitive
sequence of shutting down and resuming operation during over-current conditions. In most
applications, the minimum recommended time for tRESET is 0.1 seconds.
tSU is the time between powering up the IC in shutdown mode to the moment the IC releases shutdown
to begin normal operation.
The Ct determines tRESET and tSU as following equations:
CtVAA
tRESET
[s]
[s]
1.1ICSD
Ct VAA
tSU
0.7 ICSD
where ICSD: the charge/discharge current at the CSD pin
VAA: the floating input supply voltage with respect to VSS.
11.1.3
Shutdown Input
During normal operation, pulling the CSD pin below the upper threshold Vth1 forces the IC into shutdown mode.
Figure 38 shows how to add an external discharging path to shutdown the PWM.
Figure 38 Shutdown Input
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11.1.4
Latched Protection
Connecting CSD to VAA through a 10 kΩ or less resistor configures latched protection mode. The internal
shutdown latch stays in shutdown mode after the overcurrent is detected. An external reset switch brings CSD
below the lower threshold Vth2 for a minimum of 200 ns and resets the latch. At first power-up, a reset signal to
the CSD pin is required to release the IC from shutdown mode.
Figure 39 Latched Protection with Reset Input
11.1.5
Interfacing with System Controller
The MA5332MS can communicate with an external system controller through a simple interfacing circuit shown
in Figure 40. A generic PNP transistor, U1, detects the sink current at the CSD pin during protection event and
outputs a shutdown flag signal to an external system controller. Another generic NPN transistor, U2, can then
reset the internal protection logic by pulling the CSD voltage below the lower threshold Vth2. After the first
power-up sequence, a reset signal to the CSD pin is required to release the IC from shutdown mode.
Figure 40 Interfacing CSD with System Controller
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Protections
11.2
Over Current Protection (OCP)
The MA5332MS features over current protection to protect the internal power MOSFETs during abnormal load
conditions. The control logic diagrams are in Figure 41. As soon as either the high-side or low-side current sensing
block detects over current, the following sequence will occur.
1. The shutdown latch flips its logic states from normal operational mode to shutdown mode.
2. Low-side and high-side MOSFETs go into an off state condition.
3. The CSD pin starts discharging the external capacitor Ct.
4. When voltage across Ct falls below the lower threshold Vth2, COMP2 resets the shutdown latch to normal
mode.
5. The CSD pin starts charging the external capacitor Ct.
6. When VCSD goes above the upper threshold Vth1, the logic on COMP1 toggles and the IC resumes
operation.
Figure 41 summarizes the above. As long as the over current condition exists, the IC will repeat the over current
protection sequence at a repetitive rate set by the CSD capacitor.
Figure 41 Overcurrent Protection Timing Chart
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Protections
11.3
Over Temperature Protection (OTP)
If the junction temperature TJ of the controller IC exceeds the on-chip thermal shutdown threshold, TSD, the on-
chip over temperature protection shuts down the PWM.
11.4
Under Voltage Protection (UVP)
In order to prevent a partial on-state of the internal MOSFET, under-voltage protection monitors the low side and
high side gate bias supplies, VCC and VB. When VCC is below UVLO, both high and low side MOSFETs are turned
off. When the high side supply VBS is below the UVLO threshold, the high side output is disabled, while the low
side works normally.
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Status Output
12
Status Output
12.1
Fault Output
FAULT output is an open drain output referenced to GND to report whether the MA5332MS is in shutdown mode
or in normal operating mode. If the FAULT pin is open, the MA5332MS is in normal operation mode, i.e. the
output MOSFETs are active. The following conditions trigger shutdown internally and pulls the FAULT pin down
to GND.
Over Current Protection
Over Temperature Protection
Shutdown mode from CSD pin voltage
Figure 42 Fault Output
Datasheet
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Integrated Class D Amplifier
MA5332MS
Status Output
12.2
CLIP Output
When the output of the amplifier loses track of an expected target value, the amplifier enters into clipping
condition.
The CLIP detection block monitors the COMP pin voltage with a window comparator. The CLIP pin is pulled to
GND when a clipping condition is detected. The detection thresholds in the COMP pin are at 10% and 90% of
VAA-VSS. The CLIP outputs are disabled in shutdown mode.
VAA
IN-
OTA
PWM
IN+
COMP
VSS
VAA
R
CLIP1
PGEN
R
R
GND
SD
VSS
Figure 43 CLIP Detection
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Integrated Class D Amplifier
MA5332MS
Power Supply Design
13
Power Supply Design
13.1
Supplying VAA and VSS
VAA and VSS are supply voltages to the front-end of the analog section, hence are noise sensitive. For best
audio performance, use regulated power supplies for VAA and VSS.
10
VAA
7805
2.2µF
GND
2.2µF
10
VSS
7905
MA53xx
Figure 44 Supplying VAA and VSS with External Voltage Regulators
When switched-mode regulators are used as supply voltages for VAA and VSS, place a two-stage R-C noise filter
in the supply lines as shown in Figure 45.
10
10
VAA
+5V
10µF
2.2µF
GND
VSS
10µF
10
2.2µF
10
-5V
MA53xx
Figure 45 Supplying VAA and VSS from Switched Mode Power Supply
13.2
Supplying VCC and VB
Figure 46 shows the recommended power supply configuration for gate driver power supplies. The gate driver
stage has three power supply inputs:
1. VCC-COM: low side gate drive supply
2. VB1-VS1: CH1 high side gate drive supply
3. VB2-VS2: CH2 high side gate drive supply
The low-side power supply, VCC, feeds the internal gate drive logic and low side gate driver. In order to protect
VCC from switching noise generated by the VS node, it is recommended to insert a few ohms of RVBS in the
bootstrap charging path.
The high-side driver requires a floating supply VBn referenced to the respective switching node VSn where the
source of the output MOSFET is connected. A charge pump method (floating bootstrap power supply)
eliminates the need for a floating power supply and thus is used in the typical application circuit. The floating
bootstrap power supply charges the bootstrap capacitor CBS from the low-side power supply VCC during the
low-side MOSFET ON period. When the high-side MOSFET is ON, the diode cuts off and floats the VBS supply. CBS
retains its VB supply voltage for the rest of the high-side ON duration.
Datasheet
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Integrated Class D Amplifier
MA5332MS
Power Supply Design
IVCC IQCC IQBS 2
QG fPWM
/per channel
Recommend to have minimum 20% design margin for Ivcc.
RVPN2
4.7
CVBS2
10uF
CLIP
COMP2
IN-2
VS2
VN2
IN+2
GND
VSS
VAA
IN+1
CBP
100nF
VN1
VS1
Vbus
IN-1
COMP1
CSD
FAULT
CVCC
1uF
CVB S1
10uF
VCC
RVPN1
4.7
Figure 46 Recommended Power Supply Configurations for Output Stage
13.2.1
Choosing Bootstrap Capacitance
Often MA5332MS uses hard clipping condition. The continuous high-side ON duration could continue as long as
half of the lowest audio frequency, tens of milliseconds. A typical application uses a 22 uF CBS to support low
audio frequency clipping. A ceramic capacitor (X7R, X5R or X5S type) or aluminum electrolytic capacitor with 25
V or higher voltage rating is recommended.
13.2.2
Choosing Bootstrap Diode
Use a bootstrap charging diode with voltage rating of 1.5 x the maximum bus voltage. In order to charge the
bootstrap capacitor in a very short low-side ON period with a high PWM modulation ratio, a fast recovery diode
type (trr<50ns) is recommended.
13.2.3
Charging VBS Prior to Start
For proper start-up, pre-charging the bootstrap supply VBS prior to PWM start-up is necessary for self-oscillating
PWM modulator topologies. A charging resistor, RCHARGE, inserted between the positive supply bus and VB,
charges CBS prior to switching start as shown in Figure 47. The minimum resistance of RCHARGE is limited by the
maximum PWM modulation index of the system. When the high-side MOSFET is on, RCHARGE drains the bootstrap
power supply together with the quiescent current, IQBS, so it reduces the holding time, resulting in maximum
continuous high-side on time.
The maximum resistance of RCHARGE is limited by the current charge capability of the resistor during startup.
Datasheet
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MA5332MS
Power Supply Design
Pre-charging current flows into the speaker load. In order to startup without the load connected, a dummy load
Rdummy in parallel with the speaker output provides a pre-charging current path.
Figure 47 Bootstrap Supply Pre-Charging
Datasheet
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MA5332MS
Power Supply Design
13.3
Power Supply Sequence
The protection control block in the MA5332MS monitors the status of VAA and VCC to ensure that both voltage
supplies are above their respective UVLO (under voltage lockout) thresholds before starting normal operation. If
either VAA or VCC is below the under voltage threshold, the output MOSFETs are disabled in shutdown mode until
both VAA and VCC rise above their voltage thresholds. As soon as VAA or VCC falls below its UVLO threshold, protection
logic in the MA5332MS turns off high-side and low-side.
Figure 48 MA5332MS UVLO Timing Chart
Datasheet
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Integrated Class D Amplifier
MA5332MS
Package details
14
Package details
Figure 49 Package details
Datasheet
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Integrated Class D Amplifier
MA5332MS
Package details
Figure 50 Package details; Bottom metallization detail view
Datasheet
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Integrated Class D Amplifier
MA5332MS
Package details
Figure 51 Dimension table
Datasheet
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Integrated Class D Amplifier
MA5332MS
Board mounting, part marking, and ordering information
15
Board mounting, part marking, and ordering information
Reliability of products in the PQFN package is subject to the board mounting process. The Soldering
process is critical. Refer to Application Note AN-1170 Audio IC Board Mounting Application Note for
specific footprint design and soldering methods.
Device outline
Figure 52 shows the outline for these devices. The relative pad positions are controlled to an accuracy of
±0.050mm. For full dimensions and tolerances of each device, and to find out its size and outline, refer to the
relevant product data sheet and package outline drawing.
Figure 52 42-lead 7x7 device outline
Datasheet
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MA5332MS
Board mounting, part marking, and ordering information
Substrate/PCB layout
Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout shown in
Figure 53 and Figure 54
Figure 53 42-lead 7x7 substrate /PCB layout_1
Figure 54 42-lead 7x7 substrate /PCB layout_2
Datasheet
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Integrated Class D Amplifier
MA5332MS
Board mounting, part marking, and ordering information
Stencil Design
Evaluations have shown that the best overall performance is achieved using the stencil design shown in
Figure 55-58.
Figure 55 42-lead 7x7 stencil design_1
Datasheet
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Integrated Class D Amplifier
MA5332MS
Board mounting, part marking, and ordering information
Figure 56 42-lead 7x7 stencil design_2
Figure 57 42-lead 7x7 stencil design_3
Note:
This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for
stencils of other thicknesses. All soldering conditions are necessary to ensure reliability. More
details please refer to Application Note AN-1170 Audio Power Quad Flat No-Lead (PQFN) Board
Mounting Application
Part marking
Figure 58 Part marking
Datasheet
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MA5332MS
Board mounting, part marking, and ordering information
Ordering information
Standard pack
Base part number Package type
Form
Complete part number
Quantity
MA5332MS
7x7mm PG- IQFN-42
Tape and Reel
3000
MA5332MS
Datasheet
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100VꢀIntegratedꢀClassꢀDꢀAmplifier
MA5332MS
RevisionꢀHistory
MA5332MS
Revision:ꢀ2021-09-25,ꢀRev.ꢀ2.0
Previous Revision
Revision Date
Subjects (major changes since last revision)
Release of final version
2.0
2021-09-25
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60
Rev.ꢀ2.0,ꢀꢀ2021-09-25
相关型号：
MA53R-100MHZ
CMOS/TTL Output Clock Oscillator, 100MHz Nom, HERMETIC SEALED, METAL, WELDED PACKAGE-8/4
CONNOR-WINFIE
MA53R-FREQ
CMOS/TTL Output Clock Oscillator, 13MHz Min, 100MHz Max, HERMETIC SEALED, METAL, WELDED PACKAGE-8/4
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