PC100-323-620 [INFINEON]
3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module; 3.3V 2M ×64 /72- 1位BANK SDRAM模块3.3V 4M ×64 /72- 2位BANK SDRAM模块
| 型号： | PC100-323-620 |
| 厂家： | 
Infineon |
| 描述： | 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module |
| 文件： | 总17页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 2M x 64/72-Bit 1 BANK SDRAM Module
3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
HYS64/72V2200GU-8/-10
HYS64/72V4220GU-8/-10
168 pin unbuffered DIMM Modules
• 168 Pin PC100 and PC66 compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules
for PC main memory applications
• 1 bank 2M x 64, 2M x 72 and 2 bank 4M x 64, 4M x 72 organisation
• Optimized for byte-write non-parity or ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTELs’ Rev. 1.0 module specification
• SDRAM Performance:
-8
-8-3
100
-10
66
Units
MHz
fCK
tAC
Clock frequency (max.)
Clock access time
100
6
6
8
ns
• Programmed Latencies :
Product Speed
CL
2
tRCD
tRP
-8
PC100
PC100
PC66
2
2
2
2
3
2
-8-3
-10
3
2
• Single +3.3V(± 0.3V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
2
• Serial Presence Detect with E PROM
• Utilizes 2M x 8 SDRAMs in TSOPII-44 packages
• 4096 refresh cycles every 64 ms
• 133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads
Semiconductor Group
1
6.98
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
The HYS64(72)2200 and HYS64(72)4220 are industry standard 168-pin 8-byte Dual in-line Memory Modules
(DIMMs) which are organised as 2M x 64, 2M x 72 in 1 bank and 4M x 64 and 4M x 72 in two banks high speed
memory arrays designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs
use -8 speed sort 2M x 8 SDRAM devices in TSOP44 packages to meet the PC100 requirement. Modules which
use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The
PC board design is according to INTELs’ PC SDRAM Rev.1.0 module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The
first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint,
with 1,25“( 31,75 mm) height
Ordering Information
Type
Ordering Code
Package
Descriptions
Module
Height
100 Mhz 2M x 64 1 bank SDRAM module
100 MHz 2M x 72 1 bank SDRAM module
100 Mhz 4M x 64 2 bank SDRAM module
100 Mhz 4M x 72 2 bank SDRAM module
100 Mhz 2M x 64 1 bank SDRAM module
100 MHz 2M x 72 1 bank SDRAM module
100 Mhz 4M x 64 2 bank SDRAM module
100 Mhz 4M x 72 2 bank SDRAM module
66 Mhz 2M x 64 1 bank SDRAM module
66 MHz 2M x 72 1 bank SDRAM module
66 Mhz 4M x 64 2 bank SDRAM module
66 Mhz 4M x 72 2 bank SDRAM module
HYS 64V2200GU-8
HYS 72V2200GU-8
HYS 64V4220GU-8
HYS 72V4220GU-8
HYS 64V2200GU-8-3
HYS 72V2200GU-8-3
HYS 64V4220GU-8-3
HYS 72V4220GU-8-3
HYS 64V2200GU-10
HYS 72V2200GU-10
HYS 64V4220GU-10
HYS 72V4220GU-10
PC100-222-620
PC100-222-620
PC100-222-620
PC100-222-620
PC100-323-620
PC100-323-620
PC100-323-620
PC100-323-620
PC66-222-920
PC66-222-920
PC66-222-920
PC66-222-920
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
L-DIM-168-29
1,25“
1,25“
1,25“
1,25“
1,25“
1,25“
1,25“
1,25“
1,25“
1,25“
1,25“
1,25“
Pin Names
A0-A10
BA
Address Inputs
Bank Address
CLK0 - CLK3
Clock Input
DQMB0 - DQMB7 Data Mask
DQ0 - DQ63 Data Input/Output
CS0 - CS3
Vcc
Chip Select
CB0-CB7
Check Bits (x72
Power (+3.3 Volt)
organisation only)
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Read / Write Input
Vss
SCL
SDA
N.C.
Ground
Clock for Presence Detect
Serial Data Out for Presence Detect
No Connection
CKE0, CKE1 Clock Enable
Address Format:
Part Number
Rows
11
Columns
Banks
Refresh
4k
Period
64 ms
64 ms
64 ms
64 ms
Interval
15,6 µs
15,6 µs
15,6 µs
15,6 µs
2M x 64
2M x 72
4M x 64
4M x 72
HYS 64V2200GU
HYS 72V2200GU
HYS 64V4220GU
HYS 72V4220GU
9
9
9
9
1
1
1
1
11
4k
11
4k
11
4k
Semiconductor Group
2
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Pin Configuration
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
1
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
NC (CB0)
NC (CB1)
VSS
NC
43
VSS
85
VSS
127
VSS
2
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DU
86
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CKE0
CS3
3
CS2
87
4
DQMB2
DQMB3
DU
88
DQMB6
DQMB7
NC
5
89
6
90
7
VCC
91
VCC
NC
8
NC
92
9
NC
93
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC (CB2)
NC (CB3)
VSS
94
CB6
95
CB7
96
VSS
DQ16
DQ17
DQ18
DQ19
VCC
97
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
NC (CB4)
NC (CB5)
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
NC
DU
DU
CKE1
VSS
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ53
DQ54
DQ55
VSS
NC
NC
NC
VCC
WE
VCC
CAS
DQ24
DQ25
DQ26
DQ27
VCC
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
DQMB0
DQMB1
CS0
DQMB4
DQMB5
CS1
DU
RAS
VSS
A0
DQ28
DQ29
DQ30
DQ31
VSS
VSS
A1
A2
A3
A4
A5
A6
A7
A8
CLK2
NC
A9
CLK3
NC
A10
BA
NC
WP
NC
SA0
VCC
VCC
CLK0
SDA
VCC
CLK1
NC
SA1
SCL
SA2
VCC
VCC
Note : Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
3
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
WE
CS0
CS WE
CS WE
DQMB0
DQ(7:0)
DQMB4
DQM
DQM
DQ(39:32)
DQ0-DQ7
DQ0-DQ7
D4
D0
CS WE
CS WE
DQM
DQ0-DQ7
DQM
DQMB1
DQMB5
DQ0-DQ7
DQ(15:8)
DQ(47:40)
D5
D1
CS WE
DQM
CB(7:0)
DQ0-DQ7
D8
CS2
CS WE
CS WE
DQMB2
DQM
DQM
DQMB6
DQ0-DQ7
DQ0-DQ7
DQ(55:48)
DQ(23:16)
D6
CS WE
D2
CS WE
DQMB7
DQM
DQM
DQMB3
DQ(63:56)
DQ0-DQ7
DQ0-DQ7
DQ(31:24)
D3
D0 - D7,(D8)
D0 - D7,(D8)
D0 - D7,(D8)
D7
E2PROM (256wordx8bit)
A0-A10,BA
VCC
VSS
SA0
SA1
SA2
SCL
SA0
SA1
SA2
SCL
SDA
WP
C0-C7,(C8)
47k
RAS
CAS
CKE0
D0 - D7,(D8)
D0 - D7,(D8)
Clock Wiring
2M x 64
CLK0 4 SDRAM+3.3pF 5 SDRAM
CLK1 Termination Termination
CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF
CLK3 Termination Termination
2M x 72
D0 - D7,(D8)
Note: D8 is only used in the x72 ECC version
Block Diagram for 2M x 64/72 SDRAM DIMM modules (HYS64/72V2200GU)
Semiconductor Group
4
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
CS1
CS0
CS
CS
CS
CS
DQM
DQM
DQMB0
DQ(7:0)
DQM
DQM
DQMB4
DQ0-DQ7
D0
DQ0-DQ7
D8
DQ0-DQ7
D4
DQ0-DQ7
D12
DQ(39:32)
CS
CS
CS
CS
DQM
DQM
DQM
DQM
DQMB1
DQMB5
DQ(15:8)
DQ(47:40)
DQ0-DQ7
D1
DQ0-DQ7
D9
DQ0-DQ7
D5
DQ0-DQ7
D13
CS
CS
DQM
DQM
DQ0-DQ7
D16
DQ0-DQ7
D17
CB(7:0)
CS3
CS2
CS
CS
CS
CS
DQM
DQM
DQMB2
DQM
DQM
DQMB6
DQ(23:16)
DQ(55:48)
DQ0-DQ7
D2
DQ0-DQ7
D10
DQ0-DQ7
D6
DQ0-DQ7
D14
CS
CS
CS
CS
DQMB3
DQM
DQM
DQMB7
DQM
DQM
DQ(31:24)
DQ(63:56)
DQ0-DQ7
D3
DQ0-DQ7
D11
DQ0-DQ7
D7
DQ0-DQ7
D15
E2PROM (256wordx8bit)
D0 - D15,(D16,D17)
D0 - D15,(D16,D17)
A0-A10,BA
VDD
SA0
SA1
SA2
SCL
SA0
SDA
WP
SA1
SA2
SCL
C0-C31,(C32..C35)
VSS
D0 - D7,(D8)
47k
RAS, CAS, WE
CKE0
D0 - D15,(D16,D17)
Clock Wiring
4M x 64
D0 - D7,(D16)
4M x 72
VDD
10k
CLK0 4 SDRAM+3.3pF 5 SDRAM
CLK1 4 SDRAM+3.3pF 5 SDRAM
CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF
CLK3 4 SDRAM+3.3pF 4 SDRAM+3.3pF
CKE1
D9 - D15,(D17)
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted.
Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4220GU)
Semiconductor Group
5
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit
min.
max.
Vcc+0.3
0.8
Input high voltage
VIH
VIL
2.0
– 0.5
2.4
V
Input low voltage
V
Output high voltage (IOUT = – 2.0 mA)
Output low voltage (IOUT = 2.0 mA)
VOH
VOL
II(L)
–
V
–
0.4
V
Input leakage current, any input
– 40
40
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current
IO(L)
– 40
40
µA
(DQ is disabled, 0 V < VOUT < VCC)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
max.
max.
max.
max.
2Mx64 2Mx72 4Mx64 4Mx72
Input capacitance
CI1
45
55
80
90
pF
(A0 to A10, BA, RAS, CAS, WE)
Input capacitance (CS0 -CS3 )
Input capacitance (CLK0 - CLK3)
Input capacitance (CKE0, CKE1)
Input capacitance (DQMB0 - DQMB7)
CI2
CICL
CI3
CI4
CIO
20
22
22
13
13
25
38
38
13
12
30
22
50
20
20
35
38
55
20
20
pF
pF
pF
pF
pF
Input / Output capacitance
(DQ0-DQ63,CB0-CB7)
Input Capacitance (SCL,SA0-2)
Input/Output Capacitance
C
C
8
8
8
8
pF
pF
sc
10
10
10
10
sd
Semiconductor Group
6
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
o
1)
Standby and Refresh Currents (T = 0 to 70 C, VCC = 3.3V ± 0.3V)
a
Note
Parameter
Symbol
Test Condition
X64 X72
max.
Burst length = 4, CL=3
trc>=trc(min.),
Operating Current
Icc1
800 900 mA 1,2
tck>=tck(min.), Io=0 mA
2 bank interleave operation
CKE<=VIL(max), tck>=tck(min.)
CKE<=VIL(max), tck=infinite
Precharged Standby
Current in Power
Down Mode
Icc2P
24
16
27 mA
18 mA
Icc2PS
CKE>=VIH(min), tck>=tck (min.),
input changed once in 3 cycles
Precharged Standby
Current in Non-
power
Icc2N
160 180 mA CS=
High
CKE>=VIH(min), tck=infinite,
no input change
Icc2NS
80
90 mA
Down Mode
CKE<=VIL(max), tck>=tck(min.)
CKE<=VIL(max), tck=infinite
Active Standby
Current in Power
Down Mode
Icc3P
24
16
27 mA
18 mA
Icc3PS
CKE>=VIH(min), tck>=tck (min.)
input changed one time
Active Standby
Current in Non-
power Down Mode
Icc3N
Icc3NS
Icc4
200 225 mA CS=
High
CKE=>VIH(min),tck=infinite,
no input change
120 135 mA
Burst Operating
Current
Burst length = full page,
trc = infinite, CL = 3,
tck>=tck (min.), Io = 0 mA
2 banks activated
760 855 mA 1,2
1,2
Auto (CBR) Refresh
Current
Icc5
Icc6
trc>=trc(min)
720 810 mA
Self Refresh Current
CKE=<0,2V
16 18 mA 1,2
Semiconductor Group
7
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
AC Characteristics 3)4)
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Symbol
Note
Parameter
Limit Values
Unit
-8
PC100
2-2-2
-8-3
PC100
3-2-3
-10
PC66
2-2-2
min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
tCK
fCK
tAC
CAS Latency = 3
CAS Latency = 2
10
10
10
10
10
15
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
–
–
100
100
–
–
100
100
–
–
100 MHz
66 MHz
Clock Access Time
4,5)
CAS Latency = 3
CAS Latency = 2
–
–
6
6
–
–
6
7
–
–
8
9
ns
ns
6)
6)
7)
7)
8)
Clock High Pulse Width
tCH
3
3
–
–
–
–
–
3
3
–
–
–
–
–
3.5
3.5
3
–
–
–
–
–
ns
ns
ns
ns
ns
Clock Low Pulse Width
Input Setup time
tCL
tCS
2
2
Input Hold Time
tCH
1
1
1
CKE Setup Time
tCKSP
2.5
2.5
3
(Power down mode)
9)
CKE Setup Time
(Self Refresh Exit)
tCKSR
tT
8
1
–
–
8
1
–
–
8
1
–
–
ns
ns
Transition time (rise and fall)
Common Parameters
RAS to CAS delay
Cycle Time
tRCD
tRC
tRAS
tRP
tRRD
tCCD
20
–
20
–
30
–
ns
120k
70 120k 70 120k 75
ns
Active Command Period
Precharge Time
45
20
16
1
–
–
–
–
45
30
20
1
–
–
–
–
45
30
20
1
–
–
–
–
ns
ns
Bank to Bank Delay Time
ns
CAS to CAS delay time
(same bank)
CLK
Semiconductor Group
8
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Symbol
Note
Parameter
Limit Values
Unit
-8
PC100
2-2-2
-8-3
PC100
3-2-3
-10
PC66
2-2-2
min. max. min. max. min. max.
Refresh Cycle
9)
8)
Self Refresh Exit Time
tSREX
10
64
–
–
10
64
–
–
10
64
–
–
ns
Refresh Period (4096 cycles) tREF
ms
Read Cycle
4)
Data Out Hold Time
tOH
tLZ
3
0
–
–
3
0
–
–
3
0
–
–
ns
ns
Data Out to Low Impedance
Time
10)
Data Out to High Impedance tHZ
Time
3
2
9
–
3
2
9
–
3
2
9
–
ns
DQM Data Out Disable
Latency
tDQZ
CLK
Write Cycle
–
Data input to Precharge (write tDPL
2
–
2
–
2
CLK
recovery)
–
–
11)
Data In to Active/refresh
DQM Write Mask Latency
tDAL
5
0
–
–
5
0
–
–
5
0
CLK
CLK
tDQW
Semiconductor Group
9
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
Notes:
1. The specified values are valid when addresses are changed no more than once during tck(min.)
and when No Operation commands are registered on every rising clock edge during tRC(min).
Values are shown per module bank.
2. The specified values are valid when data inputs (DQs’) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have V = 0.4 V and V = 2.4 V with the timing referenced to the 1.4 V crossover
il
ih
point. The transition time is measured between V and V . All AC measurements assume t =1ns
ih
il
T
with the AC output load circuit show. Specified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V.
tCH
+ 1.4 V
2.4 V
CLOCK
50 Ohm
0.4 V
tCL
t
T
Z=50 Ohm
tSETUP tHOLD
I/O
50 pF
1.4V
INPUT
tAC
tAC
I/O
tLZ
tOH
50 pF
Measurement conditions for
tac and toh
1.4V
OUTPUT
tHZ
fig.1
5. If clock rising time is longer than 1ns, a time (t /2 -0.5) ns has to be added to this parameter.
T
6. Rated at 1.5 V
7. If t is longen than 1 ns, a time (t -1) ns has to be added to this parameter.
T
T
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
11.t
is equivalent to t
+ t
.
DAL
DPL
RP
Semiconductor Group
10
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence
detect protocol ( I2C synchronous 2-wire bus)
SPD-Table:
Byte#
Description
SPD Entry Value
Hex
2Mx64 2Mx72 4Mx64 4Mx72
-8
80
08
04
0B
09
-8
80
08
04
0B
09
-8
80
08
04
0B
09
-8
80
08
04
0B
09
0
1
2
3
4
Number of SPD bytes
128
256
Total bytes in Serial PD
Memory Type
SDRAM
11
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x8 SDRAM)
9
5
6
7
8
9
Number of DIMM Banks
Module Data Width
1 / 2
64 / 72
0
01
40
00
01
A0
60
00
80
01
48
00
01
A0
60
02
80
02
40
00
01
A0
60
00
80
02
48
00
01
A0
60
02
80
Module Data Width (contd’ )
Module Interface Levels
SDRAM Cycle Time at CL=3
LVTTL
10.0 ns
6.0 ns
10 SDRAM Access time from Clock at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
none / ECC
Self-Refresh,
15.6µs
13 SDRAM width, Primary
x8
08
00
01
08
08
01
08
00
01
08
08
01
14 Error Checking SDRAM data width
n/a / x8
15 Minimum clock delay for back-to-back ran-
dom column address
tccd = 1 CLK
16 Burst Length supported
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
1, 2, 4, 8 & full page
2
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
CAS lat. = 2 & 3
CS latency = 0
Write latency = 0
20 WE Latencies
21 SDRAM DIMM module attributes
non buffered/non
reg.
22 SDRAM Device Attributes :General
Vcc tol +/- 10%
10.0 ns
06
A0
60
FF
FF
06
A0
60
FF
FF
06
A0
60
FF
FF
06
A0
60
FF
FF
23 Min. Clock Cycle Time at CAS Latency = 2
24 Max. data access time from Clock for CL=2
25 Minimum Clock Cycle Time at CL = 1
6.0 ns
not supported
not supported
26 Maximum Data Access Time from Clock at
CL=1
27 Minimum Row Precharge Time
20 ns
14
10
14
10
14
10
14
10
28 Minimum Row Active to Row Active delay
tRRD
16 ns
Semiconductor Group
11
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
SPD-Table (contd’ ):
Byte#
Description
SPD Entry Value
Hex
2Mx64 2Mx72 4Mx64 4Mx72
-8
14
2D
04
20
10
20
10
FF
-8
14
2D
04
20
10
20
10
FF
-8
14
2D
04
20
10
20
10
FF
-8
14
2D
04
20
10
20
10
FF
29 Minimum RAS to CAS delay tRCD
30 Minimum RAS pulse width tRAS
31 Module Bank Density (per bank)
32 SDRAM input setup time
20 ns
45 ns
16 MByte
2 ns
33 SDRAM input hold time
1 ns
34 SDRAM data input setup time
35 SDRAM data input hold time
2 ns
1 ns
36-61 Superset information (may be used in
future)
62 SPD Revision
Revision 1.2
100 MHz
12
C9
XX
12
DB
XX
12
CA
XX
12
DC
XX
63 Checksum for bytes 0 - 62
64- Manufacturers information (optional)
125 (FFh if not used)
126 Frequency Specification
127 Details of 100 MHz Support
128+ Unused storage locations
64
AF
FF
64
AF
FF
64
FF
FF
64
FF
FF
Semiconductor Group
12
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
SPD-Table:
Byte#
Description
SPD Entry Value
Hex
2Mx64 2Mx72 4Mx64 4Mx72
-8-3
-8-3
-8-3
-8-3
0
1
2
3
4
Number of SPD bytes
Total bytes in Serial PD
128
256
80
80
80
80
08
08
08
08
Memory Type
SDRAM
11
04
04
04
04
Number of Row Addresses (without BS bits)
0B
09
0B
09
0B
09
0B
09
Number of Column Addresses
(for x8 SDRAM)
9
5
6
7
8
9
Number of DIMM Banks
Module Data Width
1 / 2
64 / 72
0
01
40
00
01
A0
60
00
80
01
48
00
01
A0
60
02
80
02
40
00
01
A0
60
00
80
02
48
00
01
A0
60
02
80
Module Data Width (contd’ )
Module Interface Levels
SDRAM Cycle Time at CL=3
LVTTL
10.0 ns
6.0 ns
10 SDRAM Access time from Clock at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
none / ECC
Self-Refresh,
15.6µs
13 SDRAM width, Primary
x8
08
00
01
08
08
01
08
00
01
08
08
01
14 Error Checking SDRAM data width
n/a / x8
15 Minimum clock delay for back-to-back ran-
dom column address
tccd = 1 CLK
16 Burst Length supported
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
1, 2, 4, 8 & full page
2
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
CAS lat. = 2 & 3
CS latency = 0
Write latency = 0
20 WE Latencies
21 SDRAM DIMM module attributes
non buffered/non
reg.
22 SDRAM Device Attributes :General
Vcc tol +/- 10%
10.0 ns
06
A0
70
FF
FF
06
A0
70
FF
FF
06
A0
70
FF
FF
06
A0
70
FF
FF
23 Min. Clock Cycle Time at CAS Latency = 2
24 Max. data access time from Clock for CL=2
25 Minimum Clock Cycle Time at CL = 1
7.0 ns
not supported
not supported
26 Maximum Data Access Time from Clock at
CL=1
27 Minimum Row Precharge Time
30 ns
1E
14
1E
14
1E
14
1E
14
28 Minimum Row Active to Row Active delay
tRRD
20 ns
Semiconductor Group
13
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
SPD-Table (contd’ ):
Byte#
Description
SPD Entry Value
Hex
2Mx64 2Mx72 4Mx64 4Mx72
-8-3
14
2D
04
20
10
20
10
FF
-8-3
14
2D
04
20
10
20
10
FF
-8-3
14
2D
04
20
10
20
10
FF
-8-3
14
2D
04
20
10
20
10
FF
29 Minimum RAS to CAS delay tRCD
30 Minimum RAS pulse width tRAS
31 Module Bank Density (per bank)
32 SDRAM input setup time
20 ns
45 ns
16 MByte
2 ns
33 SDRAM input hold time
1 ns
34 SDRAM data input setup time
35 SDRAM data input hold time
2 ns
1 ns
36-61 Superset information (may be used in
future)
62 SPD Revision
Revision 1.2
100 MHz
12
E7
XX
12
F9
XX
12
E8
XX
12
FA
XX
63 Checksum for bytes 0 - 62
64- Manufacturers information (optional)
125 (FFh if not used)
126 Frequency Specification
127 Details of 100 MHz Support
128+ Unused storage locations
64
AD
FF
64
AD
FF
64
FD
FF
64
FD
FF
Semiconductor Group
14
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
SPD-Table:
Byte#
Description
SPD Entry Value
Hex
2Mx64 2Mx72 4Mx64 4Mx72
-10
80
08
04
0B
09
-10
80
08
04
0B
09
-10
80
08
04
0B
09
-10
80
08
04
0B
09
0
1
2
3
4
Number of SPD bytes
Total bytes in Serial PD
128
256
Memory Type
SDRAM
11
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x8 SDRAM)
9
5
6
7
8
9
Number of DIMM Banks
Module Data Width
1 / 2
64 / 72
0
01
40
00
01
A0
80
00
80
01
48
00
01
A0
80
02
80
02
40
00
01
A0
80
00
80
02
48
00
01
A0
80
02
80
Module Data Width (contd’ )
Module Interface Levels
SDRAM Cycle Time at CL=3
LVTTL
10.0 ns
8.0 ns
10 SDRAM Access time from Clock at CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
none / ECC
Self-Refresh,
15.6µs
13 SDRAM width, Primary
x8
08
00
01
08
08
01
08
00
01
08
08
01
14 Error Checking SDRAM data width
n/a / x8
15 Minimum clock delay for back-to-back ran-
dom column address
tccd = 1 CLK
16 Burst Length supported
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
1, 2, 4, 8 & full page
2
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
8F
02
06
01
01
00
CAS lat. = 2 & 3
CS latency = 0
Write latency = 0
20 WE Latencies
21 SDRAM DIMM module attributes
non buffered/non
reg.
22 SDRAM Device Attributes :General
Vcc tol +/- 10%
15.0 ns
06
F0
90
FF
FF
06
F0
90
FF
FF
06
F0
90
FF
FF
06
F0
90
FF
FF
23 Min. Clock Cycle Time at CAS Latency = 2
24 Max. data access time from Clock for CL=2
25 Minimum Clock Cycle Time at CL = 1
9.0 ns
not supported
not supported
26 Maximum Data Access Time from Clock at
CL=1
27 Minimum Row Precharge Time
30 ns
1E
14
1E
14
1E
14
1E
14
28 Minimum Row Active to Row Active delay
tRRD
20 ns
Semiconductor Group
15
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
SPD-Table (contd’ ):
Byte#
Description
SPD Entry Value
Hex
2Mx64 2Mx72 4Mx64 4Mx72
-10
1E
2D
04
30
10
30
10
FF
-10
1E
2D
04
30
10
30
10
FF
-10
1E
2D
04
30
10
30
10
FF
-10
1E
2D
04
30
10
30
10
FF
29 Minimum RAS to CAS delay tRCD
30 Minimum RAS pulse width tRAS
31 Module Bank Density (per bank)
32 SDRAM input setup time
30 ns
45 ns
16 MByte
3 ns
33 SDRAM input hold time
1 ns
34 SDRAM data input setup time
35 SDRAM data input hold time
3 ns
1 ns
36-61 Superset information (may be used in
future)
62 SPD Revision
Revision 1.2
66 MHz
12
A1
XX
12
B3
XX
12
A2
XX
12
B4
XX
63 Checksum for bytes 0 - 62
64- Manufacturers information (optional)
125 (FFh if not used)
126 Frequency Specification
127 Details
66
AF
FF
66
AF
FF
66
FF
FF
66
FF
FF
128+ Unused storage locations
Semiconductor Group
16
HYS64(72)V2200/4220GU-8/-10
SDRAM-Modules
L-DIM-168-29
SDRAM DIMM Module package
133,35
127,35
4,0
x)
84
1
10 11
40 41
42,18
66,68
A
C
B
85
94 95
124 125
168
x)
D
6,35
6,35
1,27
1,0 + 0.5
-
+
0,2 0,15
-
2,0
2,0
Detail C
Detail A
2.26
Detail B
DM168-29.WMF
RADIUS
1.27 + 0.10
x) on ECC modules only
Detail D
Semiconductor Group
17
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