PEF22504E [INFINEON]
Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications;
| 型号： | PEF22504E |
| 厂家： | 
Infineon |
| 描述： | Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications |
| 文件： | 总255页 (文件大小：7193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.3, Jan. 2006
QuadLIUTM
Quad E1/T1/J1 Line Interface Component for
Long- and Short-Haul Applications
PEF 22504 E, PEF 22504 HT, Version 2.1
Communications
Edition 2006-01-25
Published by Infineon Technologies AG,
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
QuadLIUTM
PEF 22504
PEF 22504 E, Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications
Revision History: 2006-01-25, Rev. 1.3
Previous Version: Preliminary Data Sheet 2005-11-07
Chapter, Table Subjects (major changes since last revision)
Chapter 2.3,
The QuadLIUTM is now available in PG-TQFP-144-17 package also
Chapter 5
Trademarks
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®,
INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®,
QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™,
VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft
Corporation, Linux® of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
Data Sheet
3
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1
1.2
1.3
2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ball Diagram P/PG-LBGA-160-1 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ball Diagram P/PG-LBGA-160-1 (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Diagram P-TQFP-144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1
2.2
2.3
2.4
2.5
3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.1.1
3.5.2
3.5.2.1
3.5.2.2
3.5.3
3.5.4
3.5.5
3.5.5.1
3.6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Asynchronous Micro Controller Interface (Intel or Motorola mode) . . . . . . . . . . . . . . . . . . . . . . . . . 67
Mixed Byte/Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Serial Micro Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Master Clocking Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
PLL (Reset and Configuring) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Line Coding and Framer Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Bipolar Violation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Receive Line Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Receive Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
“Generic” Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Receive Line Monitoring Mode (RLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Monitoring Application using RLM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Redundancy Application using RLM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
General Redundancy Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Loss-of-Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Receive Equalization Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Receive Line Attenuation Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Receive Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Receive Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Receive Jitter Attenuation Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Output Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Dual Receive Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Additional Receiver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Error Monitoring and Alarm Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Automatic Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
One-Second Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.6.1
3.7
3.7.1
3.7.2
3.7.3
3.7.3.1
3.7.3.2
3.7.3.3
3.7.3.4
3.7.3.5
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.7.8.1
3.7.8.2
3.7.8.3
3.7.8.4
3.7.9
3.8
3.8.1
3.8.2
3.8.3
3.8.4
Data Sheet
4
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Table of Contents
3.9
Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Transmit Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Transmit Clock TCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Automatic Transmit Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Transmit Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Dual Transmit Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Programmable Pulse Shaper and Line Build-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
QuadFALCTM V2.1 Compatible Programming with XPM(2:0) Registers . . . . . . . . . . . . . . . . . . 106
Programming with TXP(16:1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Transmit Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Framer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Pseudo-Random Binary Sequence Generation and Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
In-Band Loop Generation, Detection and Loop Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Remote Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Payload Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Alarm Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Multi Function Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.6.1
3.9.6.2
3.9.7
3.10
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.11.6
3.12
4
4.1
4.1.1
4.2
4.2.1
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Detailed Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Detailed Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6
6.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Master Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Asynchronous Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Intel Bus Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Motorola Bus Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Digital Interface (Framer Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Pulse Template E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Pulse Template T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Power Supply Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
6.1.1
6.1.2
6.1.3
6.1.4
6.1.4.1
6.1.4.2
6.1.4.3
6.1.4.4
6.1.5
6.1.6
6.1.6.1
6.1.6.2
6.2
6.3
6.4
6.4.1
6.4.2
7
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Device Configuration in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Device Configuration in T1/J1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Device Configuration for Digital Clock Interface Mode (DCIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
7.1
7.2
7.3
7.4
7.5
7.6
Data Sheet
5
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Table of Contents
8
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
8.1
8.2
8.3
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Data Sheet
6
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical Multiple Link Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical Multiple Repeater Application between line #1 and Line #2. . . . . . . . . . . . . . . . . . . . . . . . 16
Top View of the Pin Configuration (Ball Layout) P/PG-LBGA-160-1 . . . . . . . . . . . . . . . . . . . . . . . 17
Bottom View of the Pin Configuration (Ball Layout) P/PG-LBGA-160-1. . . . . . . . . . . . . . . . . . . . . 18
Pin Configuration P-TQFP-144-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Single Voltage Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Dual Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 10 SCI Interface Application with Point To Point Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 11 SCI Interface Application with Multipoint To Multipoint Connection . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 12 SCI Message Structure of QuadLIUTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 13 Frame Structure of QuadLIUTM SCI Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 14 Principle of Building Addresses and RSTA bytes in the SCI ACK Message of the QuadLIUTM . . . 72
Figure 15 Read Status Byte (RSTA) byte of the SCI Acknowledge (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 16 SPI Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 17 SPI Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 18 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 19 Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 20 Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 21 Behaviour of Bipolar Violation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 22 Receive System of one Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 23 Recovered and Receive Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 24 General Receiver Configuration with Integrated Resistor and Analog Switches for Receive
Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 25 Principle of Receive Line Monitoring RLM (shown for one line) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 26 Monitoring Application using RLM (shown for one line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 27 Redundancy Application using RLM (shown for one line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 28 General Redundancy Application (shown for one line). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 29 Principle of Configuring the DCO-R and DCO-X Corner Frequencies . . . . . . . . . . . . . . . . . . . . . . 94
Figure 30 Jitter Attenuation Performance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 31 Jitter Attenuation Performance (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 32 Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 33 Jitter Tolerance (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34 Output Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 35 The Receive Elastic Buffer as Circularly Organized Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 36 Transmit System of one Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 37 Transmit Line Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 38 Clocking and Data in Remote Loop Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 39 Measurement Configuration for E1 Transmit Pulse Template . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 40 Measurement Configuration for T1/J1 Transmit Pulse Template . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 41 Transmit Line Monitor Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 42 Framer Interface (shown for one channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 43 Remote Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 44 Local Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 45 Payload Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 46 P/PG-LBGA-160-1 (Plastic Green Low Profile Ball Grid Array Package). . . . . . . . . . . . . . . . . . . 220
Figure 47 PG-TQFP-144-17 (Plastic Thin Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 48 MCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 49 JTAG Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 50 Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Figure 51 Intel Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 52 Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Data Sheet
7
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
List of Figures
Figure 53 Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 54 Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 55 Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 56 Motorola Write Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 57 SCI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 58 SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 59 FCLKX Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 60 FCLKR Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 61 SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 62 FSC Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 63 E1 Pulse Shape at Transmitter Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 64 T1 Pulse Shape at the Cross Connect Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 65 Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 66 Input/Output Waveforms for AC Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 67 Device Configuration for Power Supply Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 68 Protection Circuitry Examples (shown for one channel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 69 Screen Shot of the “Master Clock Frequency Calculator” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 70 Screen Shot of the “External Line Frontend Calculator”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Data Sheet
8
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
I/O Signals for P/PG-LBGA-160-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
I/O Signals for P-TQFP-144-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Overview about the Pin Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Data Bus Access (16-Bit Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Data Bus Access (16-Bit Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Selectable asynchronous Bus and Microprocessor Interface Configuration . . . . . . . . . . . . . . . . 68
Read Status Byte (RSTA) Byte of the SCI Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . 73
Definition of Control Bits in Commands (CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SCI Configuration Register Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupt Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TAP Controller Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Conditions for a PLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Line Coding and Framer Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Controlling of the Receive Interface Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Generic Receiver Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
External Component Recommendations for Monitoring Applications using RLM . . . . . . . . . . . . . 87
Tristate Configurations for the RDO, RSIG, SCLKR and RFM Pins . . . . . . . . . . . . . . . . . . . . . . . 88
Configuration for Redundancy Application using RLM, switching with only one board signal . . . 89
General (proposed) Configuration for Redundancy Applications, Switching with only one Board
Signal
90
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Configuration for “non-generic” Redundancy Applications, Switching with only one Board Signal 91
Configuration for “generic” Redundancy Applications, Switching with only one Board Signal . . . 91
Switching in “Generic” Redundancy Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Overview DCO-R (DCO-X) Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Clocking Modes of DCO-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Receive (Transmit) Elastic Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Summary of Alarm Detection and Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Recommended Transmitter Configuration Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Recommended Pulse Shaper Programming for T1/J1 with Registers XPM(2:0) (Compatible to
QuadFALC V2.1 )
106
Table 30
Recommended Pulse Shaper Programming for E1 with Registers XPM(2:0) (Compatible to
QuadFALC V2.1)
107
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Recommended Pulse Shaper Programming for T1 with Registers TXP(16:1) . . . . . . . . . . . . . . 107
Recommended Pulse Shaper Programming for E1 with registers TXP(16:1) . . . . . . . . . . . . . . 108
Supported PRBS Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Multi Function Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
IMRn Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Interrupt Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
CCBn Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Clear Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
FLLB Constant Values (Case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
FLLB Constant Values (Case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
LLBP Constant Values (Case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
LLBP Constant Values (Case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
RPC1 Constant Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
XPC1 Constant Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
PCn Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Clock Mode Register Settings for E1 or T1/J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
TXP Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Data Sheet
9
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
List of Tables
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Alarm Simulation States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MCLK Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
JTAG Boundary Scan Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Reset Timing Parameter Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Intel Bus Interface Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Motorola Bus Interface Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SCI Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
SPI Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
FCLKX Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
FCLKR Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
SYNC Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
FSC Timing Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
T1 Pulse Template at Cross Connect Point (T1.102 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Package Characteristic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Power Supply Test Conditions E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Power Supply Test Conditions T1/J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Initial Values after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Configuration Parameters (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Line Interface Configuration (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Configuration Parameters (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Line Interface Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Device Configuration for DCIM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Data Sheet
10
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Preface
The QuadLIUTM is four channel E1/T1/J1 Line interface Component, it is designed to fulfill all required interfacing
between four analog E1/T1/J1 lines and four digital framers.
The digital functions as well as the analog characteristics can be configured either via a flexible microprocessor
interface, SPI interface or via a SCI interface.
Organization of this Document
This Data Sheet is organized as follows:
•
•
•
•
Chapter 1, “Introduction”: Gives a general description of the product and its family, lists the key features, and
presents some typical applications.
Chapter 2, “Pin Descriptions”: Lists pin locations with associated signals, categorizes signals according to
function, and describe signals.
Chapter 3, “Functional Description”: Describes the functional blocks and principle operation modes, organized
into separate sections for E1 and T1/J1 operation
Chapter 4, “Registers”: Gives a detailed description of all implemented registers and how to use them in
different applications/configurations.
•
•
•
Chapter 5, “Package Outlines”: Shows the mechanical characteristics of the device packages.
Chapter 6, “Electrical Characteristics”: Specifies maximum ratings, DC and AC characteristics.
Chapter 7, “Operational Description”: Shows the operation modes and how they are to be initialized
(separately for E1 and T1/J1).
•
Chapter 8, “Appendix”: Gives an example for over voltage protection and information about application notes
and tool support.
Related Documentation
This document refers to the following international standards (in alphabetical/numerical order):
ANSI/EIA-656
ANSI T1.102
ANSI T1.231
ANSI T1.403
AT&T PUB 43802
AT&T PUB 54016
AT&T PUB 62411
ESD Ass. Standard EOS/ESD-5.1-1993
ETSI ETS 300 011
ETSI ETS 300 233
ETSI TBR12
ITU-T G.703
ITU-T G.736
ITU-T G.737
ITU-T G.738
ITU-T G.739
ITU.T G.733
ITU-T G.775
ITU-T G.823
ITU-T G.824
ITU-T I.431
JT-G703
ETSI TBR13
JT-G704
FCC Part68
JT-G706
H.100
JT-G33
H-MVIP
JT-I431
IEEE 1149.1
MIL-Std. 883D
UL 1459
TR-TSY-000009
TR-TSY-000253
TR-TSY-000499
Data Sheet
11
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Introduction
1
Introduction
The QuadLIUTM is the latest addition to Infineon’s family of sophisticated E1/T1/J1 Line interface Components.
This monolithic four channel device is designed to fulfill all required interfacing between four analog E1/T1/J1 lines
and four digital framer interfaces for world market telecommunication systems.
The device is supplied in P/PG-LBGA-160-1 package (P/PG-LBGA-160-1 is RoHS compliant) and in a PG-TQFP-
144-17 package, and is designed to minimize the number of external components required, so reducing system
costs and board space.
Due to its multitude of implemented functions, it fits to a wide range of networking applications and fulfills the
according international standards.
Crystal-less jitter attenuation with only one master clock source reduces the amount of required external
components.
Equipped with a flexible microprocessor interface, a SCI and a SPI interface, it connects to various control
processor environment. A standard boundary scan interface is provided to support board level testing. LBGA
device packaging, minimum number of external components and low power consumption lead to reduced overall
system costs.
The QuadLIUTM is not hardware and software compatibel to older versions!
Other members of the FALC® family are the OctalLIUTM supporting eight line interface components on a single
chip, the OctalFALCTM and the QuadFALC® E1/T1/J1 Framer And Line interface Components for long-haul and
short-haul applications, supporting 8 or 4 channels on a single chip respectively.
Data Sheet
12
Rev. 1.3, 2006-01-25
Quad E1/T1/J1 Line Interface Component for Long-
and Short-Haul Applications
QuadLIUTM
PEF 22504 E
Version 2.1
1.1
Features
Line Interface
•
•
High-density, generic interface for all E1/T1/J1 applications
Four Analog receive and transmit circuits for long-haul and short-haul
applications
•
•
•
•
E1 or T1/J1 mode selectable
Data and clock recovery using an integrated digital phase-locked loop
Clock generator for jitter-free transmit clocks per channel
Jitter specifications of ITU-T I.431, G.703, G.736 (E1), G.823 (E1) and
AT&T TR62411 (T1/J1) and PUB 62411 are met
Maximum line attenuation up to -43 dB at 1024 kHz (E1) and up to -
36 dB at 772 kHz (T1/J1)
Flexible programmable transmit pulse shapes for E1 and T1/J1 pulse
masks
Programmable line build-out for CSU signals according to ANSI T1.
403 and FCC68: 0 dB, -7.5 dB, -15 dB, -22.5 dB (T1/J1)
Programmable low transmitter output impedances for high transmit
return loss and generic E1/T1/J1 applications
P/PG-LBGA-160-1
•
•
•
•
•
•
•
•
•
Tristate function of the analog transmit line outputs
Transmit line monitor protecting the device from damage
Flexible tristate functions of the digital receive outputs
Receive line monitor mode
P-TQFP-144-6, -8, -14
Integrated switchtable 300 Ω receive resistors for generic E1/T1/J1
applications to meet termination resistance 75/120 Ω for E1, 100 Ω for T1 and 110 Ω for J1
Integrated multi purpose analog switch at line receive interface to support generic redundancy applications
(only supported in P/PG-LBGA-160-1 package)
•
•
•
•
•
•
•
•
•
Crystal-less wander and jitter attenuation/compensation according to TR 62411, ETS-TBR 12/13, PUB 62411
Common master clock reference for E1 and T1/J1 with any frequency within 1.02 and 20 MHz
Power-down function
Support of automatic protection switching
Dual-rail or single-rail digital inputs and outputs
Unipolar CMI for interfacing fiber-optical transmission routes
Selectable line codes (E1: HDB3, AMI/T1: B8ZS, AMI with ZCS)
Loss-of-signal indication with programmable thresholds according to ITU-T G.775, ETS300233 (E1) and ANSI
T1.403 (T1/J1)
•
•
Optional data stream muting upon LOS detection
Programmable receive slicer threshold
Type
Package
PEF 22504 HT
PEF 22504 E
PG-TQFP-144-17
P/PG-LBGA-160-1
Data Sheet
13
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Introduction
•
Local loop, digital loop and remote loop for diagnostic purposes. Automatic remote loop switching is possible
with In-Band and Out-Band loop codes
•
•
•
•
•
•
Low power device, two power supply voltages 1.8 V and 3.3 V or a single supply of 3.3 V
Alarm and performance monitoring per second 16-bit counter for code violations, PRBS bit errors
Insertion and extraction of alarm indication signals (AIS)
Single-bit defect insertion
Flexible clock frequency for receiver and transmitter
Dual elastic stores for both, receive and transmit route clock wander and jitter compensation; controlled slip
capability and slip indication
•
•
•
•
Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass
Programmable In-band loop code detection and generation (TR62411)
Local loop back, payload loop back land remote loop back capabilities (TR54016)
Flexible pseudo-random binary sequence generator and monitor
Microprocessor Interfaces
•
•
•
•
•
Asynchronous 8/16-bit microprocessor bus interface (Intel or Motorola type selectable)
SPI bus interface
SCI bus interface
All registers directly accessible
Multiplexed and non-multiplexed address bus operations on asynchronous 8/16-bit microprocessor bus
interface
•
•
•
Hard/software reset options
Extended interrupt capabilities
One-second timer (internal or external timing reference)
General
•
•
•
•
•
Boundary scan standard IEEE 1149.1
PG-TQFP-144-17P-BGA-160-1 package
Temperature range from -40 to +85 °C
1.8 V and 3.3 V power supply or single 3.3 V power supply
Typical power consumption 140 mW per channel
Applications
•
•
•
•
•
•
•
•
Wireless base stations
E1/T1/J1 ATM gateways, multiplexer
E1/T1/J1 Channel & Data Service Units (CSU, DSU)
E1/T1/J1 Internet access equipment
LAN/WAN router
ISDN PRI, PABX
Digital Access Crossconnect Systems (DACS)
SONET/SDH add/drop multiplexer
Data Sheet
14
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Introduction
1.2
Logic Symbol
RLAS2(4:1)
RL1(4:1)
RL2(4:1)
Receive
Line
Interface
RDO(4:1)
RPA(4:1)
RPB(4:1)
Receive
Digital
Interface
RPC(4:1)
RPD(4:1)
FCLKR(4:1)
QuadLIU V2.1
PEF 22504 E
TDI
Boundary
Scan
Interface
TMS
TCK
TRS
TDO
P/PG-BGA-160-1
PEF 22504 HT
PG-TQFP-144-17
XDI(4:1)
XPA(4:1)
Transmit
Digital
Interface
XPB(4:1)
XPC(4:1)
XPD(4:1)
FCLKX(4:1)
Transmit
Line
XL1(4:1)
XL2(4:1)
Interface
(SCI- or
SPI-Bus)
Microprocessor Interface
Mode
QLIU_Logic_symbol
Figure 1
Logic Symbol
Data Sheet
15
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Introduction
1.3
Typical Applications
Figure 2 shows a multiple link application, Figure 3 a repeater application using the QuadLIUTM
.
.
4 x E1/T1/J1
Receive&
Transmit
System
Highway
QuadLIU
Framer ASIC
.
.
PEB 22504
Microprocessor
QLI U_F0195
Figure 2
Typical Multiple Link Application
RL1.1
RDO1
FCLKR1
RL2.1
XL1.1
RDON1
XDI1
Bidirectional
Line #1
FCLKX1
XL2.1
RL1.2
XDIN1
RDO2
1/2
QuadLIU
FCLKR2
RL2.2
XL1.2
RDON2
XDI2
Bidirectional
Line #2
FCLKX2
XDIN2
XL2.2
QLI U_F0069
Figure 3
Typical Multiple Repeater Application between line #1 and Line #2
Data Sheet
16
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
2
Pin Descriptions
In this chapter the function and placement of all pins are described.
2.1
Ball Diagram P/PG-LBGA-160-1 (top view)
Figure 4 shows the ball layout of the QuadLIUTM in a P/PG-LBGA-160-1 package.
1
2
3
4
5
6
7
8
9
10 11 12 13 14
XL1_2 XL2_2 VDDR VSSR RL1_2 RL2_2 RL2_1 RL1_1 VSSR VDDR XL2_1 XL1_1
A
B
C
D
E
F
VSSX
VSSX
VSSX XDI1 MCLK XPC2 TRS XPD2 VDD XPA1 VDDP XPB1 D15 VSSX
FCLKX
(RLAS22)
(RLAS21)
VDDX VDDX
TCK VSSP VDDP XPA2 XPB2 XPC1 VDDC TDO
D14 VDDX VDDX
1
RPC1 RPA1 RPB1 RPD1 TMS VSEL RCLK2 VSS XPD1 RCLK1 TDI
FCLKR
D12
D13
D11
D10
D6
RDO1
VDD
VDD
RPA2
RPD2
VSS
VDD VDD
1
FCLKR
2
RDO2 VSS
RPC2 RPB2
D9
D7
D8
READY
/DTACK
FCLKX
2
VSS
VSS
VSS
VSS
D5
D4
D0
D3
D1
G
H
J
(VDD)
READY_
FCLKX
XDI3
3
XDI2 RPA3
D2 EN
(VSS)
FCLKR
BHE/
BLE
WR/
RW
RPB3 RPD3 RPC3
CS
A8
A3
A1
A0
RD/DS
A7
3
IM1
RDO3
VDD RDO4
A9
A5
IM
A6
A2
(VSS)
K
L
FCLKR
4
SEC/
FSC
RPB4 RPA4 DBW RCLK3 XPA3 XPD3 XPB4 ALE
A4
FCLKX
VDDX VDDX RPC4
VSSX
INT
RES
VDD VDD XPD4 VDDC
VDDX VDDX
4
M
N
P
VSSX
VSSX
VSSX RPD4 XDI4 XPC3 SYNC XPB3 XPA4 RCLK4 VSS XPC4
(RLAS23)
(RLAS24)
XL1_3 XL2_3 VDDR VSSR RL1_3 RL2_3 RL2_4 RL1_4 VSSR VDDR XL2_4 XL1_4
QLI U_F0213_2
Figure 4
Top View of the Pin Configuration (Ball Layout) P/PG-LBGA-160-1
2.2
Ball Diagram P/PG-LBGA-160-1 (bottom view)
Figure 4 shows the ball layout of the QuadLIUTM in a P/PG-LBGA-160-1 package.
Data Sheet
17
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
14 13 12 11 10
9
8
7
6
5
4
3
2
1
XL1_1 XL2_1 VDDR VSSR RL1_1 RL2_1 RL2_2 RL1_2 VSSR VDDR XL2_2 XL1_2
A
VSSX
VSSX
VSSX D15 XPB1 VDDP XPA1 VDD XPD2 TRS XPC2 MCLK XDI1 VSSX
FCLKX
B (RLAS21)
(RLAS22)
VDDX VDDX D14
TDO VDDC XPC1 XPB2 XPA2 VDDP VSSP TCK
VDDX VDDX
C
1
D11
D13
D12
TDI RCLK1 XPD1 VSS RCLK2 VSEL TMS RPD1 RPB1 RPA1 RPC1
FCLKR
D
D10
VDD VDD
VSS
VDD
VDD
RDO1
E
1
FCLKR
2
D6
D8
D7
D9
RPA2
RPD2
VSS RDO2
RPB2 RPC2
F
READY/
FCLKX
2
D3
D4 DTACK D5
(VDD)
VSS
VSS
VSS
VSS
G
READY_
FCLKX
XDI3
3
D1
D0
EN
D2
RPA3 XDI2
FCLKR
H
(VSS)
WR/
RW
BHE/
BLE
RD/DS
CS
A8
RPC3 RPD3 RPB3
J
3
IM1
A7
A6
A2
A9
A5
IM
RDO4 VDD
RDO3
K
(VSS)
SEC/
FSC
FCLKR
4
A4
A3
A1
ALE XPB4 XPD3 XPA3 RCLK3 DBW RPA4 RPB4
FCLKX
L
VDDX VDDX
VSSX
VDDC XPD4 VDD VDD
RES
INT
RPC4 VDDX VDDX
M
4
VSSX
VSSX A0
XPC4 VSS RCLK4 XPA4 XPB3 SYNC XPC3 XDI4 RPD4 VSSX
N (RLAS24)
(RLAS23)
XL1_4 XL2_4 VDDR VSSR RL1_4 RL2_4 RL2_3 RL1_3 VSSR VDDR XL2_3 XL1_3
P
QLIU_F0213_3
Figure 5
Bottom View of the Pin Configuration (Ball Layout) P/PG-LBGA-160-1
Data Sheet
18
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
2.3
Pin Diagram P-TQFP-144
Figure 6 shows the pin diagram of the QuadLIUTM
.
108
109
104
100
96
92
88
84
80
76
73
72
XL1_1/XDOP1/XOID1
VDDX
XL1_4/XDOP4/XOID4
VDDX
XL2_1/XDON1/XFM1
XL2_4/XDON4/XFM4
TDI
112
116
120
124
128
132
136
140
SEC/FSC
TDO
68
64
60
56
52
48
44
IM
VDDR
VDDR
RL1_1/RDIP1/ROID1
RL2_1/RDIN1/RCLKI1
VSSR
RL1_4/RDIP4/ROID4
RL2_4/RDIN4/RCLKI4
VSSR
VDDC
VDDC
RCLK1
ALE
XPA1
RCLK4
XPB1
XPC1
XPD1
VDDP
XPD4
XPC4
XPB4
XPA4
VSS
VSS
XPA2
VDD
XPB2
XPC2
XPD2
RCLK2
XPD3
XPC3
XPB3
XPA3
TRS
SCLKX4
VDDP
XDI4
MCLK
SYNC
VSEL
RCLK3
VSSP
VSSR
RES
VSSR
RL2_2/RDIN2/RCLKI2
RL2_3/RDIN3/RCLKI3
RL1_2/RDIP2/ROID2
RL1_3/RDIP3/ROID3
VDDR
TCK
VDDR
INT
TMS
40
37
DBW
XL2_2/XDON2/XFM2
XL2_3/XDON3/XFM3
VDDX
VDDX
XL1_2/XDOP2/XOID2
144
1
XL1_3/XDOP3/XOID3
4
8
12
16
20
24
28
32
36
QLIU_F214
Figure 6
Pin Configuration P-TQFP-144-8
Data Sheet
19
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
2.4
Pin Definitions and Functions
The following table describes all pins and their functions:
Table 1
Pin No.
I/O Signals for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
Operation Mode Selection and Device Initialization
M5
RES
I
PU
Hardware Reset
Active low
K2
IM1
IM0
I
I
PD
PU
Interface Mode Selection
´00B´: Asynchronous Intel Bus Mode.
´01B´: Asynchronous Motorola Bus Mode
´10B´: SPI Bus Slave Mode.
M11
´11B´: SCI Bus Slave Mode
Asynchronous and Serial Micro Controller Interfaces
K11
K12
K14
K13
L11
A9
A8
A7
A6
A5
A5
I
I
I
I
I
I
PU
PU
PU
PU
PU
PU
Address Bus Line 9 (MSB)
Address Bus Line 8
Address Bus Line 7
Address Bus Line 6
Address Bus Line 5
SCI source address bit 5 (MSB)
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
L14
L12
L13
M12
N12
B12
A4
A4
I
I
PU
PU
Address Bus Line 4
SCI source address bit 4
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
A3
A3
I
I
PU
PU
Address Bus Line 3
SCI source address bit 3
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
A2
A2
I
I
PU
PU
Address Bus Line 2
SCI source address bit 2
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
A1
A1
I
I
PU
PU
Address Bus Line 1
SCI source address bit 1
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
A0
A0
I
I
PU
PU
Address Bus Line 0
SCI source address bit 0 (LSB)
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
D15
IO
I
PU
PU
Data Bus Line 15
PLL10
PLL programming bit 10
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
Data Sheet
20
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
C12
D13
D12
D14
E14
F11
F13
F12
F14
G11
D14
IO
I
PU
PU
Data Bus Line 14
PLL9
PLL programming bit 9
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D13
IO
I
PU
PU
Data Bus Line 13
PLL8
PLL programming bit 8
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D12
IO
I
PU
PU
Data Bus Line 12
PLL7
PLL programming bit 7
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D11
IO
I
PU
PU
Data Bus Line 11
PLL6
PLL programming bit 6
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D10
IO
I
PU
PU
Data Bus Line 10
PLL5
PLL programming bit 5
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D9
IO
I
PU
PU
Data Bus Line 9
PLL4
PLL programming bit 4
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D8
IO
I
PU
PU
Data Bus Line 8
PLL3
PLL programming bit 3
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D7
IO
I
PU
PU
Data Bus Line 7
PLL2
PLL programming bit 2
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D6
IO
I
PU
PU
Data Bus Line 6
PLL1
PLL programming bit 1
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
D5
IO
I
PU
PU
Data Bus Line 5
PLL0
PLL programming bit 0
Only used if SCI or SPI interface mode is selected by
IM(1:0) = ´1Xb´.
G13
G14
D4
D3
IO
IO
PU
PU
Data Bus Line 4
Data Bus Line 3
Data Sheet
21
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
H11
H14
H13
L9
D2
IO
I
PU
–
Data Bus Line 2
SCI Bus Clock
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
SCI_CLK
SCLK
I
–
SPI Bus Clock
Only used if SPI interface mode is selected by IM(1:0) =
´10b´.
D1
IO
I
PU
PU
Data Bus Line 1
SCI_RXD
SCI Bus Serial Data In
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
SDI
I
PU
PU
SPI Serial Data In
Only used if SPI interface mode is selected by IM(1:0) =
´10b´.
D0
IO
I
Data Bus Line 0
SCI_TXD
PP or oD SCI Bus Serial Data Out
Only used if SCI interface mode is selected by IM(1:0) =
´11b´.
SDO
ALE
I
I
PU
PU
SPI Bus Serial Data Out
Only used if SPI interface mode is selected by IM(1:0) =
´10b´.
Address Latch Enable
A high on this line indicates an address on an external
multiplexed address/data bus. The address information
provided on lines A(10:0) is internally latched with the
falling edge of ALE. This function allows the QuadLIUTM
to be connected to a multiplexed address/data bus
without the need for external latches. In this case, pins
A(7:0) must be connected to the data bus pins
externally. In case of demultiplexed mode this pin can
be connected directly to VDD or can be left open.
J14
RD
DS
I
I
PU
PU
Read Enable
Intel bus mode.
This signal indicates a read operation. When the
QuadLIUTM is selected via CS, the RD signal enables
the bus drivers to output data from an internal register
addressed by A(10:0) to the Data Bus.
Data Strobe
Motorola bus mode.
This pin serves as input to control read/write operations.
Data Sheet
22
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
J13
WR
I
PU
Write Enable
Intel bus mode.
This signal indicates a write operation. When CS is
active the QuadLIUTM loads an internal register with
data provided on the data bus.
RW
I
I
PU
PU
Read/Write Select
Motorola bus mode.
This signal distinguishes between read and write
operation.
L4
DBW
Data Bus Width select
Bus interface mode
A low signal on this input selects the 8-bit bus interface
mode. A high signal on this input selects the 16-bit bus
interface mode. In this case word transfer to/from the
internal registers is enabled. Byte transfers are
implemented by using A0 and BHE/BLE.
J11
BHE
BLE
I
I
PU
PU
Bus High Enable
Intel bus mode.
If 16-bit bus interface mode is enabled, this signal
indicates a data transfer on the upper byte of the data
bus D(15:8). In 8-bit bus interface mode this signal has
no function and should be tied to VDD or left open.
Bus Low Enable
Motorola bus mode.
If 16-bit bus interface mode is enabled, this signal
indicates a data transfer on the lower byte of the data
bus D(7:0). In 8-bit bus interface mode this signal has
no function and should be tied to VDD or left open.
J12
M4
CS
I
PU
–
Chip Select
Low active chip select.
INT
O
Interrupt Request
Interrupt request.
INT serves as general interrupt request for all interrupt
sources. These interrupt sources can be masked via
registers IMR(7:0). Interrupt status is reported via
registers GIS (Global Interrupt Status) and ISR(7:0).
Output characteristics (push-pull active low/high, open
drain) are determined by programming register IPC.
Data Sheet
23
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
G12
READY
O
O
I
oD
(PU)
Data Ready
oD output only if activated by READY_EN = 1B and if
Intel bus mode is selected. If not activated (READY_EN
= 0B) the pull-up resistor is active.
Asynchronous handshake signal to indicate successful
read or write cycle.
DTACK
oD
(PU)
Data Acknowledge
oD output only if activated by READY_EN = 1B and if
motorola bus mode is selected. If not activated
(READY_EN = 0B) the pull-up resistor is active.
Asynchronous handshake signal to indicate successful
read or write cycle.
H12
READY_EN
PD
Ready Enable
Activates the oD functionality of READY/ DTACK.
0B: READY/ DTACK is not activated (only pull-up
resistor is active). Pin READY/ DTACK can be
connected to VDD.
1B: READY/ DTACK is an active oD output
Separate Analog Switches (only supported in BGA package)
B14
RLAS21
RLAS22
RLAS23
RLAS24
IO
(analog)
–
–
–
–
Analog Switch Connector port 1
Can be connected to VSSX if analog switch is not used
(HW compatibel to QuadFALC® v2.1)
B1
IO
(analog)
Analog Switch Connector port 2
Can be connected to VSSX if analog switch is not used
(HW compatibel to QuadFALC® v2.1)
N1
IO
(analog)
Analog Switch Connector port 3
Can be connected to VSSX if analog switch is not used
(HW compatibel to QuadFALC® v2.1)
N14
IO
Analog Switch Connector port 4
(analog)
Can be connected to VSSX if analog switch is not used
(HW compatibel to QuadFALC® v2.1)
Line Interface Receiver
A9
RL1.1
I (analog) –
Line Receiver input 1, port 1
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
ROID1
I
–
Receive Optical Interface Data, port 1
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). If CMI coding is
selected (MR0.RC(1:0) = ´01b´ and LIM0.DRS = ´1´), an
internal DPLL recovers clock an data; no clock signal on
RCLKI2 is required.
A8
RL2.1
I (analog) –
Line Receiver input 2, port 1
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
Data Sheet
24
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
A6
RL1.2
I (analog) –
Line Receiver input 1, port 1
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
ROID2
I
–
Receive Optical Interface Data, port 2
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). If CMI coding is
selected (MR0.RC(1:0) = ´01b´ and LIM0.DRS = ´1´), an
internal DPLL recovers clock an data; no clock signal on
RCLKI2 is required.
A7
P6
RL2.2
RL1.3
ROID3
I (analog) –
I (analog) –
Line Receiver input 2, port 2
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
Line Receiver input 1, port 3
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
I
–
Receive Optical Interface Data, port 3
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). If CMI coding is
selected (MR0.RC(1:0) = ´01b´ and LIM0.DRS = ´1´), an
internal DPLL recovers clock an data; no clock signal on
RCLKI2 is required.
P7
P9
RL2.3
RL1.4
ROID4
I (analog) –
I (analog) –
Line Receiver input 2, port 3
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
Line Receiver input 1, port 4
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
I
–
Receive Optical Interface Data, port 4
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). If CMI coding is
selected (MR0.RC(1:0) = ´01b´ and LIM0.DRS = ´1´), an
internal DPLL recovers clock an data; no clock signal on
RCLKI2 is required.
P8
RL2.4
I (analog) –
Line Receiver input 2, port 4
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
Data Sheet
25
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
Line Interface Transmitter
A13
XL1.1
O
–
–
Transmit Line 1, port 1
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
XOID1
O
Transmit Optical Interface Data, port 1
Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK2 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
A12
A2
XL2.1
XL1.2
XOID2
O
–
–
–
Transmit Line 2, port 1
(analog)
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
O
Transmit Line 1, port 2
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
O
Transmit Optical Interface Data, port 2
Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK2 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
A3
XL2.2
O
–
Transmit Line 2, port 2
(analog)
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Data Sheet
26
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
P2
XL1.3
O
–
Transmit Line 1, port 3
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
XOID3
O
–
Transmit Optical Interface Data, port 3
Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK3 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
P3
XL2.3
XL1.4
XOID4
O
–
–
–
Transmit Line 2, port 3
(analog)
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
P13
O
Transmit Line 1, port 4
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
O
Transmit Optical Interface Data, port 4
Data in CMI code is shifted out with 50% or 100% duty
cycle on both transitions of XCLK4 according to the CMI
coding. Output polarity is selected by bit LIM0.XDOS
(after reset: data is sent active high). The single-rail
mode is selected if LIM1.DRS is set and MR0.XC1 is
cleared. After reset this pin is in high-impedance state
until register LIM1.DRS is set and XPM2.XLT is cleared.
P12
XL2.4
MCLK
O
–
–
Transmit Line 2, port 4
(analog)
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit MR0.XC1 is set and
XPM2.XLT is cleared.
Clock Signals
B4
I
Master Clock
A reference clock of better than ±32 ppm accuracy in
the range of 1.02 to 20 MHz must be provided on this
pin. The QuadLIUTM internally derives all necessary
clocks from this master
(see registers GCM(6:1)).
Data Sheet
27
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
N6
SYNC
I
PU
Clock Synchronization of DCO-R
If a clock is detected on pin SYNC the
DCO-R circuitry of the QuadLIUTM synchronizes to this
1.544/2.048 MHz clock (see LIM0.MAS, CMR1.DCS
and CMR2.DCF). Additionally, in master mode the
QuadLIUTM is able to synchronize to an 8 kHz reference
clock (IPC.SSYF = ´1´). If not connected, an internal
pull-up transistor ensures high input level.
L10
FSC
O
O
–
–
8 kHz Frame Synchronization
The optionally synchronization pulse is active high or
low for one 2.048/1.544 MHz cycle (pulse width =
488 ns for E1and 648 ns or T1/J1).
D10, D7, L5, N9 RCLK(1:4)
Receive Clock Out, ports 1 to 4
After reset this ports are configured to be internally
pulled up weakly. Setting of register bit PC5.CRPR will
switch this ports to be active outputs.
Digital (Framer) Interface Receive
E1
RDO1
O
–
Receive Data Out, port 1
Received data at RL1, RL2 is sent to RDOP, RDON.
Clocking of data is done with the rising or falling edge of
RCLK.
E2
F1
F3
K1
J4
FCLKR1
RDO2
I/O
O
PU
–
Framer Data Clock Receive, port 1
Input if PC5.CSRP = ´0´, output if PC5.CSRP = ´1´.
Receive Data Out, port 2
See description of RDOP1.
FCLKR2
RDO3
I/O
O
PU
–
Framer Data Clock Receive, port 2
See description of FCLKR1.
Receive Data Out, port 3
See description of RDOP1.
FCLKR3
RDO4
I/O
O
PU
–
Framer Data Clock Receive, port 3
See description of FCLKR1.
K4
L1
Receive Data Out, port 4
See description of RDOP1.
FCLKR4
I/O
PU
Framer Data Clock Receive, port 4
See description of FCLKR1.
Digital (Framer) Interface Transmit
B3
XDI1
I
–
Transmit Data In, port 1
NRZ transmit data received from the framer. Latching of
data is done with rising or falling transitions of FCLKX1
according to bit DIC3.RESX.
C3
H3
FCLKX1
XDI2
I/O
I
–
–
Framer Data Clock Transmit, port 1
Transmit Data In, port 2
See description of XDI1.
G3
H1
FCLKX2
XDI3
I/O
I
–
–
Framer Data Clock Transmit, port 2
See description of FCLKX1.
Transmit Data In, port 3
See description of XDI1.
Data Sheet
28
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
H2
N4
M6
FCLKX3
XDI4
I/O
–
–
–
Framer Data Clock Transmit, port 3
See description of FCLKX1.
I
Transmit Data In, port 4
See description of XDI1.
FCLKX4
I/O
Framer Data Clock Transmit, port 4
See description of FCLKX1.
Multi Function Pins
D2
D3
D1
D4
RPA1
I/O
PU/–
Receive Multifunction Pins A to D, port 1
Depending on programming of bits PC(1:4).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
RPB1
RPC1
RPD1
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions are described below.
D2
D3
D1
D4
D2
D3
D1
D4
D2
D3
D1
D4
D2
D3
D1
D4
D2
D3
D1
D4
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
I
PU
PU
–
Receive Line Termination (RLT), port 1
PC(1:4).RPC(3:0) = ´1000b´.
These input function controls together with LIM0.RTRS
the analog switch of the receive line interface: A logical
equivalence is build out of LIM0.RTRS and RLT.
I
General Purpose Input (GPI), port 1
PC(1:4).RPC(3:0) = ´1001b.
The pin is set to input. The state of this input is reflected
in the register bits MFPI.RPA, MFPI.RPB or MFPI.RPC
respectively.
O
O
O
General Purpose Output High (GPOH), port 1
PC(1:4).RPC(3:0) = ´1010b´.
The pin level is set fix to high level.
–
General Purpose Output Low (GPOL), port 1
PC(1:4).RPC(3:0) = ´1011b´.
The pin level is set fix to low-level.
–
Loss of Signal Indication Output (LOS), port 1
PC(1:3).RPC(3:0) = ´1100b.
The output reflects the Loss of Signal status as readable
in LSR0.LOS.
Data Sheet
29
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
D2
D3
D1
D4
RPA1
RPB1
RPC1
RPD1
O
–
Receive Data Output Negative (RDON), port 1
PC(1:4).RPC(3:0) = ´1110b´.
Receive data output negative for dual rail mode on
digital (framer) interface (LIM3.DRR = ´1´).
Bipolar violation output for single rail mode on digital
(framer) interface (LIM3.DRR = ´0´).
D2
D3
D1
D4
RPA1
RPB1
RPC1
RPD1
O
–
Receive Clock Output (RCLK), port 1
PC(1:4).RPC(3:0) = ´1111b´. Default setting after reset
Receive clock output RCLK. After reset RCLK is
configured to be internally pulled up weekly. By setting
of PC5.CRP RCLK is an active output.
RCLK source and frequency selection is made by
CMR1.RS(1:0) if COMP = ´1´ or by CMR4.RS(2:0) if
COMP = ´0´.
F4
RPA2
RPB2
RPC2
RPD2
I/O
PU/–
Receive Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
G2
G1
G4
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions as described for port 1.
H4
J1
J3
J2
RPA3
RPB3
RPC3
RPD3
I/O
PU/–
Receive Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions as described for port 1.
Data Sheet
30
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
L3
RPA4
RPB4
RPC4
RPD4
I/O
PU/–
Receive Multifunction Pins A to D, port 4
Depending on programming of bits PC(1:4).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
L2
M3
N3
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions as described for port 1.
B9
XPA1
XPB1
XPC1
XPD1
I/O
PU/–
Transmit Multifunction Pins A to D, port 1
Depending on programming of bits PC(1:4).XPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESX
latching/transmission of data is done with the rising or
falling edge of FCLKX. If not connected, an internal pull-
up transistor ensures a high input level.
B11
C9
D9
Each input function (TCLK, XDIN, XLT or XLT) may only
be selected once.
Selectable pin functions are described below.
B9
XPA1
XPB1
XPC1
XPD1
I
PU
Transmit Clock (TCLK), port 1
PC(1:4).XPC(3:0) = ´0011b´
B11
C9
D9
A 2.048/8.192 MHz (E1) or 1.544/6.176 MHz (T1/J1)
clock has to be sourced by the framer if the internally
generated transmit clock (generated by DCO-X) shall
not be used. Optionally this input is used as a
synchronization clock for the DCO-X circuitry with a
frequency of 2.048 (E1) or 1.544 MHz (T1/J1).
B9
XPA1
XPB1
XPC1
XPD1
O
I
–
Transmit Clock (XCLK), port 1
PC(1:4).XPC(3:0) = ´0111b´
Transmit line clock of 2.048 MHz (E1) or 1.544 MHz
(T1/J1) derived from FCLKX/R, RCLK or generated
internally by DCO circuitries.
B11
C9
D9
B9
XPA1
XPB1
XPC1
XPD1
PU
Transmit Line Tristate (XLT), port 1
PC(1:4).XPC(3:0) = ´1000b´
A high level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically
OR´d with register bit XPM2.XLT.
B11
C9
D9
Data Sheet
31
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
B9
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
I
PU
General Purpose Input (GPI), port 1
PC(1:4).XPC(3:0) = ´1001b.
The pin is set to input. The state of this input is reflected
in the register bits MFPI.XPA, MFPI.XPB or MFPI.XPC
respectively.
B11
C9
D9
B9
O
O
I
–
General Purpose Output High (GPOH), port 1
PC(1:4).XPC(3:0) = ´1010b´.
The pin level is set fix to high level.
B11
C9
D9
B9
–
General Purpose Output Low (GPOL), port 1
PC(1:4).XPC(3:0) = ´1011b´.
The pin level is set fix to high level.
B11
C9
D9
B9
PU
Transmit Data Input Negative (XDIN), port 1
PC(1:2).XPC(3:0) = ´1101b.
Transmit data input negative for dual rail mode on
framer side (LIM3.DRX = ´1´). Depending on bit
DIC3.RESX latching of data is done with the rising or
falling edge of FCLKX.
B11
C9
D9
B9
XPA1
XPB1
XPC1
XPD1
I
PU
Transmit Line Tristate, low active, port 1
XLT : PC(1:4).XPC(3:0) = ´1110b´.
A low level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically
OR´d with register bit XPM2.XLT.
B11
C9
D9
C7
C8
XPA2,
XPB2
I/O
PU/–
Transmit Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).XPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESX
latching/transmission of data is done with the rising or
falling edge of FCLKX. If not connected, an internal pull-
up transistor ensures a high input level.
B5
B7
XPC2
XPD2
Each input function (TCLK, XDIN, XLT or XLT) may only
be selected once.
Selectable pin functions as described for port 1.
Data Sheet
32
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
L6
N7
XPA3
XPB3
I/O
PU/–
Transmit Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).XPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESX
latching/transmission of data is done with the rising or
falling edge of FCLKX. If not connected, an internal pull-
up transistor ensures a high input level.
N5
L7
XPC3
XPD3
Each input function (TCLK, XDIN, XLT or XLT) may only
be selected once.
Selectable pin functions as described for port 1.
N8
L8
XPA4
XPB4
I/O
PU/–
Transmit Multifunction Pins A to D, port 4
Depending on programming of bits PC(1:4).XPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIUTM. After
reset the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESX
latching/transmission of data is done with the rising or
falling edge of FCLKX. If not connected, an internal pull-
up transistor ensures a high input level.
N11
M9
XPC4
XPD4
Each input function (TCLK, XDIN, XLT or XLT) may only
be selected once.
Selectable pin functions as described for port 1.
Power Supply
A11
VDDR1
VDDR2
VDDR3
VDDR4
VDDX1
VDDX2
VDDX3
VDDX4
S
S
S
S
S
S
S
S
–
–
–
–
–
–
–
–
Positive Power Supply
For the analog receiver 1 (3.3 V)
A4
Positive Power Supply
For the analog receiver 2 (3.3 V)
P4
Positive Power Supply
For the analog receiver 3 (3.3 V)
P11
Positive Power Supply
For the analog receiver 4 (3.3 V)
C13, C14
C1, C2
M1, M2
M13, M14
Positive Power Supply
For the analog transmitter 1
Positive Power Supply
For the analog transmitter 2
Positive Power Supply
For the analog transmitter 3
Positive Power Supply
For the analog transmitter 4
Data Sheet
33
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
M10, C10
VDDC
S
–
Positive Power Supply
For the digital core (1.8 V).
These pins can either be positive power supply input or
output, dependent on VSEL:
VSEL connected to VSS : 1.8 V power supply inputs,
require decoupling.
VSEL connected to VDD: 1.8 V outputs for decoupling to
V
SS . These pins must not be used to supply external
devices.
B10
C6
VDDPLL
VDDP
S
S
–
–
Positive Power Supply
For the analog PLL
E3, E4
K3
Positive Power Supply
For the digital pads(3.3 V)
For correct operation, all VDDP pins have to be
connected to positive power supply.
M7, M8
E12, E13, B8
P5
VSS
S
–
Power Ground
Common for all sub circuits (0 V)
For correct operation, all VSS pins have to be connected
to ground.
P10
A10
A5
B2
N2
N13
B13
F2
N10
E11
D8
G7
G8
H7
H8
C5
B1, B14, N1, N14 VSS
S
–
–
Only for P/PG-LBGA-160-1 Package
Either usage as power ground or usage as connectors
RLAS2 of the analog switches
Power Supply Configuration
D6
VSEL
I + PU
Voltage Select
Enables the internal voltage regulator for 3.3 V only
operation mode if connected to VDD (recommended) or
left open.
Disables the internal voltage regulator for dual power
supply mode (1.8 V and 3.3 V) if connected to VSS.
Data Sheet
34
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 1
Pin No.
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
Pin Type Buffer
Type
Function
Boundary Scan/Joint Test Access Group (JTAG)
B6
TRS
I
PD
Test Reset
For Boundary Scan (active low). If not connected, an
internal pull-down transistor ensures low input level.
D11
TDI
PU
Test Data Input
For Boundary Scan.
If not connected an internal pull-up transistor ensures
high input level.
D5
TMS
TCK
TDO
Test Mode Select
For Boundary Scan.
If not connected an internal pull-up transistor ensures
high input level.
C4
Test Clock
For Boundary Scan.
If not connected an internal pull-up transistor ensures
high input level.
C11
O
–
Test Data Output
For Boundary Scan
Note:oD = open drain output PU = input or input/output comprising an internal pull-up device To override the
internal pull-up by an external pull-down, a resistor value of 22 kΩ is recommended. The pull-up devices are
activated during reset, this means their state is undefined until the reset signal has been applied. Unused
pins containing pull-ups can be left open.
Data Sheet
35
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8
Pin No. Name
Pin Type Buffer
Type
Function
Operation Mode Selection and Device Initialization
46
RES
I
PU
Hardware Reset
Active low.
29
68
IM1
IM
I
I
PD
PU
Interface Mode Selection
00B Asynchronous Intel Bus Mode
01B Asynchronous Motorola Bus Mode
10B SPI Bus Slave Mode
11B SCI Bus Slave Mode
Asynchronous and Serial Microcontroller Interfaces
83
82
81
80
79
A9
A8
A7
A6
A5
A5
I
I
I
I
I
I
PU
PU
PU
PU
PU
PU
Address Bus Line 9 (MSB)
Address Bus Line 8
Address Bus Line 7
Address Bus Line 6
Address Bus Line 5
SCI Source address bit 5 (MSB)
Only used if SCI interface mode is selected by IM(1:0) = 11B.
78
77
76
75
74
107
A4
A4
I
I
PU
PU
Address Bus Line 4
SCI Source Address bit 4
Only used if SCI interface mode is selected by IM(1:0) = 11B.
A3
A3
I
I
PU
PU
Address Bus Line 3
SCI Source Address bit 3
Only used if SCI interface mode is selected by IM(1:0) = 11B.
A2
A2
I
I
PU
PU
Address Bus Line 2
SCI Source Address bit 2
Only used if SCI interface mode is selected by IM(1:0) = 11B.
A1
A1
I
I
PU
PU
Address Bus Line 1
SCI Source Address bit 1
Only used if SCI interface mode is selected by IM(1:0) = 11B.
A0
A0
I
I
PU
PU
Address Bus Line 0
SCI Source Address Bit 0 (LSB)
Only used if SCI interface mode is selected by IM(1:0) = 11B.
D15
IO
I
PU
PU
Data Bus Line 15
PLL10
PLL Programming Bit 10
Only used if SCI or SPI interface mode is selected by IM(1:0)
= 1XB.
106
105
D14
IO
I
PU
PU
Data Bus Line 14
PLL9
PLL Programming Bit 9
Only used if SCI or SPI interface mode is selected by IM(1:0)
= 1XB.
D13
IO
I
PU
PU
Data Bus Line 13
PLL8
PLL programming bit 8
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
Data Sheet
36
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
104
103
100
99
D12
IO
I
PU
PU
Data Bus Line 12
PLL7
PLL programming bit 7
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
D11
IO
I
PU
PU
Data Bus Line 11
PLL6
PLL programming bit 6
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
D10
IO
I
PU
PU
Data Bus Line 10
PLL5
PLL programming bit 5
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
D9
IO
I
PU
PU
Data Bus Line 9
PLL4
PLL programming bit 4
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
98
D8
IO
I
PU
PU
Data Bus Line 8
PLL3
PLL programming bit 3
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
97
D7
IO
I
PU
PU
Data Bus Line 7
PLL2
PLL programming bit 2
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
96
D6
IO
I
PU
PU
Data Bus Line 6
PLL1
PLL programming bit 1
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
95
D5
IO
I
PU
PU
Data Bus Line 5
PLL0
PLL programming bit 0
Only used if SCI or SPI interface mode is selected by
IM(1:0) = 1XB.
94
93
90
D4
IO
IO
IO
I
PU
PU
PU
–
Data Bus Line 4
Data Bus Line 3
Data Bus Line 2
D3
D2
SCI_CLK
SCI Bus Clock
Only used if SCI interface mode is selected by IM(1:0) = 11B.
SCLK
I
–
SPI Bus Clock
Only used if SPI interface mode is selected by IM(1:0) = 10B.
89
D1
IO
I
PU
PU
Data Bus Line 1
SCI_RXD
SCI Bus Serial Data In
Only used if SCI interface mode is selected by IM(1:0) = 11B.
SDI
I
PU
SPI Serial Data In
Only used if SPI interface mode is selected by IM(1:0) = 10B.
Data Sheet
37
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
88
62
D0
IO
I
PU
Data Bus Line 0
SCI_TXD
PP or oD SCI Bus Serial Data Out
Only used if SCI interface mode is selected by IM(1:0) = 11B.
SDO
ALE
I
I
PU
PU
SPI Bus Serial Data Out
Only used if SPI interface mode is selected by IM(1:0) = 10B.
Address Latch Enable
A high on this line indicates an address on an external
multiplexed address/data bus. The address information
provided on A(9:0) is internally latched with the falling edge
of ALE. This function allows the QuadLIUTM to be connected
to a multiplexed address/data bus without the need for
external latches. In this case, pins A(7:0) must be connected
to the data bus pins externally. In case of demultiplexed
mode this pin can be connected directly to VDD or can be left
open.
85
RD
I
PU
Read Enable
Intel bus mode.
This signal indicates a read operation. When the QuadLIUTM
is selected via CS, the RD signal enables the bus drivers to
output data from an internal register addressed by A(10:0) to
the Data Bus.
DS
I
I
PU
PU
Data Strobe
Motorola bus mode.
This pin serves as input to control read/write operations.
84
WR
Write Enable
Intel bus mode.
This signal indicates a write operation. When CS is active the
QuadLIUTM loads an internal register with data provided on
the data bus.
RW
I
I
PU
PU
Read/Write Select
Motorola bus mode.
This signal distinguishes between read and write operation.
40
DBW
Data Bus Width select
Bus interface mode
A low signal on this input selects the 8-bit bus interface
mode. A high signal on this input selects the 16-bit bus
interface mode. In this case word transfer to/from the internal
registers is enabled. Byte transfers are implemented by using
A0 and BHE/BLE.
Data Sheet
38
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
87
BHE
BLE
I
PU
Bus High Enable
Intel bus mode.
If 16-bit bus interface mode is enabled, this signal indicates
a data transfer on the upper byte of the data bus D(15:8). In
8-bit bus interface mode this signal has no function and
should be tied to VDD or left open.
I
PU
Bus Low Enable
Motorola bus mode.
If 16-bit bus interface mode is enabled, this signal indicates
a data transfer on the lower byte of the data bus D(7:0). In 8-
bit bus interface mode this signal has no function and should
be tied to VDD or left open.
86
41
CS
I
PU
–
Chip Select
Low active chip select.
INT
O
Interrupt Request
INT serves as general interrupt request for all interrupt
sources. These interrupt sources can be masked via
registers IMR(7:0). Interrupt status is reported via registers
GIS (Global Interrupt Status) and ISR(7:0).
Output characteristics (push-pull active low/high, open drain)
are determined by programming register IPC.
91
READY
O
O
I
oD
(PU)
Data Ready
oD output only if activated by READY_EN = 1B and if Intel
bus mode is selected. If not activated (READY_EN = 0B) the
pull-up resistor is active.
Asynchronous handshake signal to indicate successful read
or write cycle.
DTACK
oD
(PU)
Data Acknowledge
oD output only if activated by READY_EN = 1B and if
motorola bus mode is selected. If not activated (READY_EN
= 0B) the pull-up resistor is active.
Asynchronous handshake signal to indicate successful read
or write cycle.
92
READY_EN
PD
Ready Enable
Activates the oD functionality of READY/ DTACK.
0B: READY/ DTACK is not activated (only pull-up resistor is
active). Pin READY/ DTACK can be connected to VDD.
1B: READY/ DTACK is an active oD output
Data Sheet
39
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
Line Interface Receiver
115
RL1.1
I (analog)
I
–
–
Line Receiver input 1, port 1
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIP1
Receive Data Input Positive, port 1
Digital input for received dual-rail PCM(+) route signal which
is latched with the internally recovered receive route clock.
An internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%. The dual-rail mode is selected if
LIM1.DRS and FMR0.RC1 are set. Input polarity is selected
by bit RC0.RDIS (after reset: active low), line coding is
selected by FMR0.RC(1:0).
ROID1
I
–
Receive Optical Interface Data, port 1
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). Latching of data is
done with the falling edge of RCLKI. Input polarity is selected
by bit RC0.RDIS. The single-rail mode is selected if
LIM1.DRS is set and FMR0.RC1 is cleared. If CMI coding is
selected (FMR0.RC(1:0) = 01B), an internal DPLL recovers
clock an data; no clock signal on RCLKI1 is required.
116
RL2.1
I (analog)
I
–
–
Line Receiver input 2, port 1
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIN1
Receive Data Input Negative, port 1
Input for received dual-rail PCM(-) route signal which is
latched with the internally recovered receive route clock. An
internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%.
The dual-rail mode is selected if LIM1.DRS and FMR0.RC1
are set. Input polarity is selected by bit RC0.RDIS
(after reset: active low), line coding is selected by
FMR0.RC(1:0).
RCLKI1
I
–
Receive Clock Input, port 1
Receive clock input for the optical interface if LIM1.DRS is
set and
FMR0.RC(1:0) = 00B.
Clock frequency: 2.048 MHz (E1) or 1.544 MHz (T1/J1).
RCLKI1 is ignored if CMI coding is selected.
Data Sheet
40
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
138
RL1.2
I (analog)
–
Line Receiver input 1, port 2
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIP2
I
–
Receive Data Input Positive, port 2
Digital input for received dual-rail PCM(+) route signal which
is latched with the internally recovered receive route clock.
An internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%. The dual-rail mode is selected if
LIM1.DRS and FMR0.RC1 are set. Input polarity is selected
by bit RC0.RDIS (after reset: active low), line coding is
selected by FMR0.RC(1:0).
ROID2
I
–
Receive Optical Interface Data, port 2
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). Latching of data is
done with the falling edge of RCLKI. Input polarity is selected
by bit RC0.RDIS. The single-rail mode is selected if
LIM1.DRS is set and FMR0.RC1 is cleared. If CMI coding is
selected (FMR0.RC(1:0) = 01B), an internal DPLL recovers
clock an data; no clock signal on RCLKI2 is required.
137
RL2.2
I (analog)
I
–
–
Line Receiver input 2, port 2
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIN2
Receive Data Input Negative, port 2
Input for received dual-rail PCM(-) route signal which is
latched with the internally recovered receive route clock. An
internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%.
The dual-rail mode is selected if LIM1.DRS and FMR0.RC1
are set. Input polarity is selected by bit RC0.RDIS
(after reset: active low), line coding is selected by
FMR0.RC(1:0).
RCLKI2
I
–
Receive Clock Input, port 2
Receive clock input for the optical interface if LIM1.DRS is
set and
FMR0.RC(1:0) = 00B.
Clock frequency: 2.048 MHz (E1) or 1.544 MHz (T1/J1).
RCLKI2 is ignored if CMI coding is selected.
Data Sheet
41
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
43
RL1.3
I (analog)
–
Line Receiver input 1, port 3
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIP3
I
–
Receive Data Input Positive, port 3
Digital input for received dual-rail PCM(+) route signal which
is latched with the internally recovered receive route clock.
An internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%. The dual-rail mode is selected if
LIM1.DRS and FMR0.RC1 are set. Input polarity is selected
by bit RC0.RDIS (after reset: active low), line coding is
selected by FMR0.RC(1:0).
ROID3
I
–
Receive Optical Interface Data, port 3
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). Latching of data is
done with the falling edge of RCLKI. Input polarity is selected
by bit RC0.RDIS. The single-rail mode is selected if
LIM1.DRS is set and FMR0.RC1 is cleared. If CMI coding is
selected (FMR0.RC(1:0) = 01B), an internal DPLL recovers
clock an data; no clock signal on RCLKI3 is required.
44
RL2.3
I (analog)
I
–
–
Line Receiver input 2, port 3
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIN3
Receive Data Input Negative, port 3
Input for received dual-rail PCM(-) route signal which is
latched with the internally recovered receive route clock. An
internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%.
The dual-rail mode is selected if LIM1.DRS and FMR0.RC1
are set. Input polarity is selected by bit RC0.RDIS
(after reset: active low), line coding is selected by
FMR0.RC(1:0).
RCLKI3
I
–
Receive Clock Input, port 3
Receive clock input for the optical interface if LIM1.DRS is
set and
FMR0.RC(1:0) = 00B.
Clock frequency: 2.048 MHz (E1) or 1.544 MHz (T1/J1).
RCLKI3 is ignored if CMI coding is selected.
Data Sheet
42
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
66
RL1.4
I (analog)
–
Line Receiver input 1, port 4
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIP4
I
–
Receive Data Input Positive, port 4
Digital input for received dual-rail PCM(+) route signal which
is latched with the internally recovered receive route clock.
An internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%. The dual-rail mode is selected if
LIM1.DRS and FMR0.RC1 are set. Input polarity is selected
by bit RC0.RDIS (after reset: active low), line coding is
selected by FMR0.RC(1:0).
ROID4
I
–
Receive Optical Interface Data, port 4
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). Latching of data is
done with the falling edge of RCLKI. Input polarity is selected
by bit RC0.RDIS. The single-rail mode is selected if
LIM1.DRS is set and FMR0.RC1 is cleared. If CMI coding is
selected (FMR0.RC(1:0) = 01B), an internal DPLL recovers
clock an data; no clock signal on RCLKI4 is required.
65
RL2.4
I (analog)
I
–
–
Line Receiver input 2, port 4
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
RDIN4
Receive Data Input Negative, port 4
Input for received dual-rail PCM(-) route signal which is
latched with the internally recovered receive route clock. An
internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%.
The dual-rail mode is selected if LIM1.DRS and FMR0.RC1
are set. Input polarity is selected by bit RC0.RDIS
(after reset: active low), line coding is selected by
FMR0.RC(1:0).
RCLKI4
I
–
Receive Clock Input, port 4
Receive clock input for the optical interface if LIM1.DRS is
set and
FMR0.RC(1:0) = 00B.
Clock frequency: 2.048 MHz (E1) or 1.544 MHz (T1/J1).
RCLKI4 is ignored if CMI coding is selected.
Data Sheet
43
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
109
XL1.1
O
–
Transmit Line 1, port 1
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDOP1
O
–
Transmit Data Output Positive, port 1
This digital output for transmitted dual-rail PCM(+) route
signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked with positive transitions of XCLK1 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low). The dual-rail mode is selected if LIM1.DRS
and FMR0.XC1 are set. After reset this pin is in high-
impedance state until register LIM1.DRS is set and
XPM2.XLT is cleared.
XOID1
O
–
Transmit Optical Interface Data, port 1
Unipolar data sent to a fiber-optical interface with 2048 kbit/s
(E1) or 1544 kbit/s (T1/J1) which is clocked on the positive
transitions of XCLK1. Clocking of data in NRZ code is done
with 100% duty cycle. Data in CMI code is shifted out with
50% or 100% duty cycle on both transitions of XCLK
according to the CMI coding. Output polarity is selected by bit
LIM0.XDOS (after reset: data is sent active high). The single-
rail mode is selected if LIM1.DRS is set and FMR0.XC1 is
cleared. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT is cleared.
Data Sheet
44
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
111
XL2.1
O (analog) –
Transmit Line 2, port 1
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDON1
O
–
Transmit Data Output Negative, port 1
This digital output for transmitted dual-rail
PCM(-) route signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked on positive transitions of XCLK1 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low).
The dual-rail mode is selected if LIM1.DRS and FMR0.XC1
are set. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT cleared.
XFM1
O
–
Transmit Frame Marker, port 1
This digital output marks the first bit of every frame
transmitted on port XDOP. This function is only available in
the optical interface mode (LIM1.DRS = 1B and FMR0.XC1 =
0B). Data is clocked on positive transitions of XCLK1. After
reset this pin is in high-impedance state until register
LIM1.DRS is set and XPM2.XLT cleared.
In remote loop configuration the XFM1 marker is not valid.
Data Sheet
45
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
144
XL1.2
O
–
Transmit Line 1, port 2
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDOP2
O
–
Transmit Data Output Positive, port 2
This digital output for transmitted dual-rail PCM(+) route
signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked with positive transitions of XCLK2 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low). The dual-rail mode is selected if LIM1.DRS
and FMR0.XC1 are set. After reset this pin is in high-
impedance state until register LIM1.DRS is set and
XPM2.XLT is cleared.
XOID2
O
–
Transmit Optical Interface Data, port 2
Unipolar data sent to a fiber-optical interface with 2048 kbit/s
(E1) or 1544 kbit/s (T1/J1) which is clocked on the positive
transitions of XCLK. Clocking of data in NRZ code is done
with 100% duty cycle. Data in CMI code is shifted out with
50% or 100% duty cycle on both transitions of XCLK2
according to the CMI coding. Output polarity is selected by bit
LIM0.XDOS (after reset: data is sent active high). The single-
rail mode is selected if LIM1.DRS is set and FMR0.XC1 is
cleared. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT is cleared.
Data Sheet
46
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
142
XL2.2
O (analog) –
Transmit Line 2, port 2
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDON2
O
–
Transmit Data Output Negative, port 2
This digital output for transmitted dual-rail
PCM(-) route signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked on positive transitions of XCLK2 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low).
The dual-rail mode is selected if LIM1.DRS and FMR0.XC1
are set. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT cleared.
XFM2
O
–
Transmit Frame Marker, port 2
This digital output marks the first bit of every frame
transmitted on port XDOP. This function is only available in
the optical interface mode (LIM1.DRS = 1B and FMR0.XC1 =
0B). Data is clocked on positive transitions of XCLK2. After
reset this pin is in high-impedance state until register
LIM1.DRS is set and XPM2.XLT cleared.
In remote loop configuration the XFM2 marker is not valid.
Data Sheet
47
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
37
XL1.3
O
–
Transmit Line 1, port 3
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDOP3
O
–
Transmit Data Output Positive, port 3
This digital output for transmitted dual-rail PCM(+) route
signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked with positive transitions of XCLK3 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low). The dual-rail mode is selected if LIM1.DRS
and FMR0.XC1 are set. After reset this pin is in high-
impedance state until register LIM1.DRS is set and
XPM2.XLT is cleared.
XOID3
O
–
Transmit Optical Interface Data, port 3
Unipolar data sent to a fiber-optical interface with 2048 kbit/s
(E1) or 1544 kbit/s (T1/J1) which is clocked on the positive
transitions of XCLK. Clocking of data in NRZ code is done
with 100% duty cycle. Data in CMI code is shifted out with
50% or 100% duty cycle on both transitions of XCLK3
according to the CMI coding. Output polarity is selected by bit
LIM0.XDOS (after reset: data is sent active high). The single-
rail mode is selected if LIM1.DRS is set and FMR0.XC1 is
cleared. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT is cleared.
Data Sheet
48
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
39
XL2.3
O (analog) –
Transmit Line 2, port 3
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDON3
O
–
Transmit Data Output Negative, port 3
This digital output for transmitted dual-rail
PCM(-) route signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked on positive transitions of XCLK3 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low).
The dual-rail mode is selected if LIM1.DRS and FMR0.XC1
are set. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT cleared.
XFM3
O
–
Transmit Frame Marker, port 3
This digital output marks the first bit of every frame
transmitted on port XDOP. This function is only available in
the optical interface mode (LIM1.DRS = 1 and FMR0.XC1 =
0B). Data is clocked on positive transitions of XCLK3. After
reset this pin is in high-impedance state until register
LIM1.DRS is set and XPM2.XLT cleared.
In remote loop configuration the XFM3 marker is not valid.
Data Sheet
49
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
72
XL1.4
O
–
Transmit Line 1, port 4
(analog)
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDOP4
O
–
Transmit Data Output Positive, port 4
This digital output for transmitted dual-rail PCM(+) route
signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked with positive transitions of XCLK4 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low). The dual-rail mode is selected if LIM1.DRS
and FMR0.XC1 are set. After reset this pin is in high-
impedance state until register LIM1.DRS is set and
XPM2.XLT is cleared.
XOID4
O
–
Transmit Optical Interface Data, port 4
Unipolar data sent to a fiber-optical interface with 2048 kbit/s
(E1) or 1544 kbit/s (T1/J1) which is clocked on the positive
transitions of XCLK. Clocking of data in NRZ code is done
with 100% duty cycle. Data in CMI code is shifted out with
50% or 100% duty cycle on both transitions of XCLK4
according to the CMI coding. Output polarity is selected by bit
LIM0.XDOS (after reset: data is sent active high). The single-
rail mode is selected if LIM1.DRS is set and FMR0.XC1 is
cleared. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT is cleared.
Data Sheet
50
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
70
XL2.4
O (analog) –
Transmit Line 2, port 4
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
XDON4
O
–
Transmit Data Output Negative, port 4
This digital output for transmitted dual-rail
PCM(-) route signals can provide
•
Half bauded signals with 50% duty cycle (LIM0.XFB = 0B)
or
•
Full bauded signals with 100% duty cycle (LIM0.XFB =
1B)
The data is clocked on positive transitions of XCLK4 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low).
The dual-rail mode is selected if LIM1.DRS and FMR0.XC1
are set. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT cleared.
XFM4
O
–
Transmit Frame Marker, port 4
This digital output marks the first bit of every frame
transmitted on port XDOP. This function is only available in
the optical interface mode (LIM1.DRS = 1B and FMR0.XC1 =
0B). Data is clocked on positive transitions of XCLK4. After
reset this pin is in high-impedance state until register
LIM1.DRS is set and XPM2.XLT cleared.
In remote loop configuration the XFM4 marker is not valid.
Clock Signals
133
MCLK
I
I
–
Master Clock
A reference clock of better than ±32 ppm accuracy in the
range of 1.02 to 20 MHz must be provided on this pin. The
QuadLIUTM internally derives all necessary clocks from this
master
(see registers GCM(8:1)).
48
SYNC
PU
Clock Synchronization of DCO-R
If a clock is detected on pin SYNC the
DCO-R circuitry of the OctalFALCTM synchronizes to this
1.544/2.048 MHz clock (see LIM0.MAS, CMR1.DCS and
CMR2.DCF). Additionally, in master mode the OctalFALCTM
is able to synchronize to an 8 kHz reference clock (IPC.SSYF
= 1B). If not connected, an internal pullup transistor ensures
high input level.
Data Sheet
51
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
69
SEC
I
PU
One-Second Timer Input
A pulse with logical high level for at least two 2.048 MHz
cycles triggers the internal one-second timer. After reset this
pin is configured to be an input. If not connected, an internal
pullup transistor ensures high input level (see register
GPC1).
SEC
FSC
O
O
–
–
One-Second Timer Output
Activated high every second for two 2.048 MHz clock cycles.
8 kHz Frame Synchronization
The optionally synchronization pulse is active high or low for
one 2.048/1.544 MHz cycle (pulse width = 488 ns for E1and
648 ns or T1/J1).
119,
130,
47,
RCLK(1:4)
O
O
–
–
Receive Clock Out, ports 1 to 4
After reset this ports are configured to be internally pulled up
weakly. Setting of register bit PC5.CRP will switch this ports
to be active outputs.
61
System Interface Receive
9
RDO1
Receive Data Out, port 1
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR1, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR1 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO1 is cleared (driven to low level, not tristate).
8
SCLKR1
I/O
PU
System Clock Receive, port 1
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR1 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
12
RDO2
O
–
Receive Data Out, port 2
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR2, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR2 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO2 is cleared (driven to low level, not tristate).
Data Sheet
52
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
13
27
26
30
SCLKR2
I/O
PU
System Clock Receive, port 2
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR2 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
RDO3
O
–
Receive Data Out, port 3
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR3, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR3 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO3 is cleared (driven to low level, not tristate).
SCLKR3
I/O
PU
System Clock Receive, port 3
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR3 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
RDO4
O
–
Receive Data Out, port 4
Received data that is sent to the system highway. Clocking
of data is done with the rising or falling edge (SIC3.RESR) of
SCLKR4, if the receive elastic store is bypassed. The delay
between the beginning of time slot 0 and the initial edge of
SCLKR4 (after SYPR goes active) is determined by the
values of registers RC1 and RC0.
If received data is shifted out with higher (more than
2.048/1.544 Mbit/s) data rates, the active channel phase is
defined by bits SIC2.SICS(2:0). During inactive channel
phases RDO4 is cleared (driven to low level, not tristate).
Data Sheet
53
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
31
SCLKR4
I/O
PU
System Clock Receive, port 4
Working clock for the receive system interface with a
frequency of 16.384/8.192/4.096/2.048 MHz in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode. If the receive elastic store is bypassed, the clock
supplied on this pin is ignored, because RCLK is used to
clock the receive system interface.
If SCLKR4 is configured to be an output, the internal working
clock of the receive system interface sourced by DCO-R or
RCLK is output.
System Interface Transmit
2
XDI1
I
–
Transmit Data In, port 1
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX1
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX1 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
3
SCLKX1
XDI2
I
I
PU
System Clock Transmit, port 1
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode.
18
–
Transmit Data In, port 2
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX2
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX2 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
19
SCLKX2
I
PU
System Clock Transmit, port 2
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode.
Data Sheet
54
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
20
XDI3
I
–
Transmit Data In, port 3
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX3
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX3 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
21
49
SCLKX3
XDI4
I
I
PU
System Clock Transmit, port 3
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode.
–
Transmit Data In, port 4
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX4
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX4 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
50
SCLKX4
I
PU
System Clock Transmit, port 4
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0B) or
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1B) in T1/J1
mode.
Multi Function Pins
4
5
6
7
RPA1
RPB1
RPC1
RPD1
I/O
PU/–
Receive Multifunction Pins A to D, port 1
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset these ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions are described below.
Data Sheet
55
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
4
5
6
7
RPA1
RPB1
RPC1
RPD1
I
PU
Synchronous Pulse Receive, port 1
SYPR, PC(1:4).RPC(3:0) = 0000B
Together with the values of registers RC(1:0) this signal
defines the beginning of time slot 0 on system highway port
RDO.
Only one multifunction port may be selected as SYPR input.
After reset, SYPR of port A is used, the other lines are
ignored.
In system interface multiplex mode, SYPR has to be provided
at port RPA1 for four or all four channels dependent if 4:1 or
8:1 multiplex mode is selected. SYPR defines the beginning
of the time slot 0 on port RDO/RSIG.
The pulse cycle is an integer multiple of 125 µs.
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
–
Receive Frame Marker (RFM), port 1
PC(1:4).RPC(3:0) = 0001B
CMR2.IRSP = 0B
The receive frame marker can be active high for a 2.048 MHz
(E1) or 1.544 MHz (T1/J1) period during any bit position of
the current frame. It is clocked off with the rising or falling
edge of SCLKR or RCLK, depending on SIC3.RESR. Offset
programming is done by using registers RC(1:0).
CMR2.IRSP = 1B
Frame synchronization pulse generated by the DCO-R
circuitry internally. This pulse is active low for a 2.048 MHz
(E1) or 1.544 MHz (T1/J1) period.
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
–
Receive Multiframe Begin (RMFB), port 1
PC(1:4).RPC(3:0) = 0010B
In E1 mode RMFB marks the beginning of every received
multiframe (RDO). Optionally the time slot 16 CAS
multiframe begin can be marked (SIC3.CASMF). Active high
for one 2.048 MHz period.
In T1/J1 mode the function depends on bit XC0.MFBS:
MFBS = 1B
RMFB marks the beginning of every received multiframe
(RDO).
MFBS = 0B
RMFB marks the beginning of every received superframe.
Additional pulses are provided every 12 frames when using
ESF/F24 or F72 format.
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
–
Receive Signaling Marker (RSIGM), port 1
PC(1:4).RPC(3:0) = 0011B
E1: Marks the time slots which are defined by register
RTR(4:1) of every received frame on port RDO.
T1/J1: Marks the time slots which are defined by register
RTR(4:1) of every received frame on port RDO, if CAS-BR is
not used.
When using the CAS-BR signaling scheme, the robbed bit of
each channel every sixth frames is marked, if CAS-BR is
enabled by XC0.BRM = 1B.
Data Sheet
56
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
–
Receive Signaling Data (RSIG), port 1
PC(1:4).RPC(3:0) = 0100B
The received CAS signaling data is sourced by this pin. Time
slots on RSIG correlate directly to the time slot assignment
on RDO.
In 4:1 system interface multiplex mode four received signaing
data streams are merged into a single data stream
respectively which is transmitted on RPB1 (bit- or byte-
interleaved).
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
–
Data Link Bit Receive (DLR), port 1
PC(1:4).RPC(3:0) = 0101B
E1: Marks the Sa(8:4)-bits within the data stream on RDO.
The Sa(8:4)-bit positions in time slot 0 of every frame not
containing the frame alignment signal are selected by
register XC0.
T1/J1: Marks the DL-bit position within the data stream on
RDO.
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
O
–
–
Freeze signaling (FREEZE), port 1
PC(1:4).RPC(3:0) = 0110B
The freeze signaling status is set active high by detecting a
loss of signal alarm, a loss of CAS frame alignment or a
receive slip (positive or negative). It will stay high for at least
one complete multiframe after the alarm disappears. Setting
SIC2.FFS enforces a high on pin FREEZE.
4
5
6
7
RPA1
RPB1
RPC1
RPD1
Frame Synchronous Pulse (RFSP) , port 1
RFSP, PC(1:4).RPC(3:0) = 0111B
Active low framing pulse derived from the received PCM
route signal (line side, RCLK). During loss of synchronization
(bit FRS0.LFA = 1B), this pulse is suppressed (not influenced
during alarm simulation).
Pulse frequency: 8 kHz
Pulse width: 488 ns (E1) or 648 ns (T1/J1).
4
5
6
7
4
5
6
7
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
I
PU
PU
–
Receive Line Termination (RLT), port 1
PC(1:4).RPC(3:0) = 1000B.
I
General Purpose Input (GPI), port 1
PC(1:4).RPC(3:0) = 1001B.
The pin is set to input. The state of this input is reflected in
the register bits MFPI.RPA, MFPI.RPB or MFPI.RPC
respectively.
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
General Purpose Output High (GPOH), port 1
PC(1:4).RPC(3:0) = 1010B.
The pin level is set fix to high level.
Data Sheet
57
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
4
5
6
7
4
5
6
7
4
5
6
7
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
O
O
I
–
General Purpose Output Low (GPOL), port 1
PC(1:4).RPC(3:0) = 1011B.
The pin level is set fix to low level.
–
Loss of Signal Indication Output (LOS), port 1
PC(1:4).RPC(3:0) = 1100B.
The output reflects the Loss of Signal status as readable in
FRS0.LOS.
PU
Receive TDM System Interface Tristate (RTDMT), port 1
PC(1:4).RPC(3:0) = 1101B.
Controlling of tristate mode for RDO, RSIG,SCLKR and
RFM. The RTDMT value is logically exored with the register
bit SIC3.RRTRI.
4
5
6
7
RPA1
RPB1
RPC1
RPD1
O
–
Receive Clock Output (RCLK), port 1
PC(1:4).RPC(3:0) = 1111B. Default setting after reset
Receive clock output RCLK. After reset RCLK is configured
to be internally pulled up weekly. By setting of PC5.CRP
RCLK is an active output.
RCLK source and frequency selection is made by
CMR1.RS(1:0) if GPC6.COMP_DIS = 0B or by
CMR4.RS(2:0) if GPC6.COMP_DIS = 1B.
14
15
16
17
RPA2
RPB2
RPC2
RPD2
I/O
PU/–
Receive Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset these ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
22
23
24
25
RPA3
RPB3
RPC3
RPD3
I/O
PU/–
Receive Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset these ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
Data Sheet
58
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
32
33
34
35
RPA4
RPB4
RPC4
RPD4
I/O
PU/–
Receive Multifunction Pins A to D, port 4
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset these ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
120
121
122
123
XPA1
XPB1
XPC1
XPD1
I/O
PU/–
Transmit Multifunction Pins A to D, port 1
Depending on programming of bits PC(1:4).XPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset the ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is done with the
rising or falling edge of SCLKX. If not connected, an internal
pullup transistor ensures a high input level.
Each input function (SYPX, XMFS, XSIG,TCLK, XLT or XLT)
may only be selected once. SYPX and XMFS must not be
used in parallel.
Selectable pin functions are described below.
120
121
122
123
XPA1
XPB1
XPC1
XPD1
I
I
PU
PU
Synchronous Pulse Transmit, port 1
SYPX, PC(1:4).XPC(3:0) = ´0000B´
Together with the values of registers XC(0:1) this signal
defines the beginning of time slot 0 at system highway port
XDI.
The pulse cycle is an integer multiple of 125 µs.
SYPX must not be used in parallel with XMFS.
120
121
122
123
XPA1
XPB1
XPC1
XPD1
Tran4mit Multiframe Synchronization (XMFS), port 1
PC(1:4).XPC(3:0) = 0001B
This port defines the frame and multiframe begin on the
transmit system interface ports XDI and XSIG.
Depending on PC5.CXMFS the signal on XMFS is active
high or low.
XMFS must not be used in parallel with SYPX.
Note:A new multiframe position has settled at least one
multiframe after pulse XMFS has been supplied.
120
121
122
123
XPA1
XPB1
XPC1
XPD1
I
PU
Transmit Signaling Data (XSIG), port 1
PC(1:4).XPC(3:0) = 0010B
Input for transmit signaling data received from the signaling
highway. Optionally, (SIC3.TTRF = 1), sampling of XSIG
data is controlled by the active high XSIGM marker. At higher
data rates sampling of data is defined by bits
SIC2.SICS(2:0).
Data Sheet
59
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
120
121
122
123
XPA1
XPB1
XPC1
XPD1
I
PU
Transmit Clock (TCLK) input, port 1
PC(1:4).XPC(3:0) = 0011B
A 2.048/8.192 MHz (E1) or 1.544/6.176 MHz (T1/J1) clock
has to be sourced by the system if the internally generated
transmit clock (generated by DCO-X) shall not be used.
Optionally this input is used as a synchronization clock for the
DCO-X circuitry with a frequency of 2.048 (E1) or 1.544 MHz
(T1/J1).
120
121
122
123
120
121
122
123
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
O
O
–
–
Transmit Multiframe Begin (XMFB), port 1
PC(1:4).XPC(3:0) = 0100B
XMFB marks the beginning of every transmitted multiframe
on XDI. The signal is active high for one 2.048 (E1) or
1.544 MHz (T1/J1) period.
Transmit Signaling Marker (XSIGM), port 1
PC(1:4).XPC(3:0) = 0101B
E1
Marks the transmit time slots on XDI of every frame which are
defined by register TTR(1:4).
T1/J1
Marks the transmit time slots on XDI of every frame which are
defined by register TTR(1:4) (if not CAS-BR is used).
When using the CAS-BR signaling scheme the robbed bit of
each channel in every sixth frame is marked.
120
121
122
123
XPA1
XPB1
XPC1
XPD1
O
–
Data Link Bit Transmit (DLX), port 1
PC(1:4).XPC(3:0) = 0110B
E1
Marks the Sa(8:4)-bits within the data stream on XDI. The
Sa(8:4)-bit positions in time slot 0 of every frame not
containing the frame alignment signal are selected by
register XC0.SA8E to XC0.SA4E.
T1/J1
This output provides a 4 kHz signal which marks the DL-bit
position within the data stream on XDI (in ESF mode only).
120
121
122
123
XPA1
XPB1
XPC1
XPD1
O
I
–
Tran4mit Clock (XCLK), port 1
PC(1:4).XPC(3:0) = 0111B
Transmit line clock of 2.048 MHz (E1) or 1.544 MHz (T1/J1)
derived from SCLKX/R, RCLK or generated internally by
DCO circuitries.
120
121
122
123
120
121
122
123
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
PU
PU
Transmit Line Tristate (XLT), port 1
PC(1:4).XPC(3:0) = 1000B
A high level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically ored
with register bit XPM2.XLT.
I
General Purpose Input (GPI), port 1
PC(1:4).XPC(3:0) = 1001B.
The pin is set to input. The state of this input is reflected in
the register bits MFPI.XPA, MFPI.XPB or MFPI.XPC
respectively.
Data Sheet
60
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
120
121
122
123
120
121
122
123
120
121
122
123
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
O
O
I
–
General Purpose Output High (GPOH), port 1
PC(1:4).XPC(3:0) = 1010B.
The pin level is set fix to high level.
–
General Purpose Output Low (GPOL), port 1
PC(1:4).XPC(3:0) = 1011B.
The pin level is set fix to high level.
PU
Transmit Line Tristate, low active, port 1
XLT : PC(1:2).XPC(3:0) = 1110B.
A low level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically ored
with register bit XPM2.XLT.
126,
127,
128,
129
XPA2
XPB2
XPC2
XPD2
I/O
PU/–
Transmit Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).XPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset the ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is done with the
rising or falling edge of SCLKX. If not connected, an internal
pullup transistor ensures a high input level.
Each input function (SYPX, XMFS, XSIG,TCLK, XLT or XLT)
may only be selected once. SYPX and XMFS must not be
used in parallel.
Selectable pin functions as described for port 1.
51,
52,
53,
54
XPA3
XPB3
XPC3
XPD3
I/O
PU/–
Transmit Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).XPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset the ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is done with the
rising or falling edge of SCLKX. If not connected, an internal
pullup transistor ensures a high input level.
Each input function (SYPX, XMFS, XSIG,TCLK, XLT or XLT)
may only be selected once. SYPX and XMFS must not be
used in parallel.
Selectable pin functions as described for port 1.
Data Sheet
61
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
57,
58,
59,
60
XPA4
XPB4
XPC4
XPD4
I/O
PU/–
Transmit Multifunction Pins A to D, port 4
Depending on programming of bits PC(1:4).XPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIUTM. After reset the ports
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is done with the
rising or falling edge of SCLKX. If not connected, an internal
pullup transistor ensures a high input level.
Each input function (SYPX, XMFS, XSIG,TCLK, XLT or XLT)
may only be selected once. SYPX and XMFS must not be
used in parallel.
Selectable pin functions as described for port 1.
Power Supply
114
139
42
VDDR1
S
S
S
S
S
S
S
S
S
–
–
–
–
–
–
–
–
–
Positive Power Supply
For the analog receiver 1 (3.3 V)
VDDR2
VDDR3
VDDR4
VDDX1
VDDX2
VDDX3
VDDX4
VDDC
Positive Power Supply
For the analog receiver 2 (3.3 V)
Positive Power Supply
For the analog receiver 3 (3.3 V)
67
Positive Power Supply
For the analog receiver 4 (3.3 V)
110
143
38
Positive Power Supply
For the analog transmitter 1 (3.3 V)
Positive Power Supply
For the analog transmitter 2(3.3 V)
Positive Power Supply
For the analog transmitter 3 (3.3 V)
71
Positive Power Supply
For the analog transmitter 4 (3.3 V)
63
Positive Power Supply
For the digital core (1.8 V).
These pins can either be positive power supply input or
output, dependent on VSEL:
118
VSEL connected to VSS : 1.8 V power supply inputs, require
decoupling.
VSEL connected to VDD: 1.8 V outputs for decoupling to VSS.
These pins must not be used to supply external devices.
124
132
10
V
S
S
–
–
Positive Power Supply
For the analog PLL (3.3 V)
VDDP
Positive Power Supply
For the digital pads (3.3 V)
For correct operation, all VDDP pins have to be connected to
positive power supply.
28
55
101
Data Sheet
62
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
Table 2
I/O Signals for P-TQFP-144-8 (cont’d)
Pin No. Name
Pin Type Buffer
Type
Function
45
VSS
S
–
Power Ground
Common for all sub circuits (0 V)
For correct operation, all VSS pins have to be connected to
ground.
64
117
136
1
36
73
108
11
56
102
125
135
Power Supply Configuration
134 VSEL I + PU
–
Voltage Select
Enables the internal voltage regulator for 3.3 V only operation
mode if connected to VDD (recommended) or left open.
Disables the internal voltage regulator for dual power supply
mode (1.8 V and 3.3 V) if connected to VSS.
Boundary Scan/Joint Test Access Group (JTAG)
131
TRS
I
PD
Test Reset
For Boundary Scan (active low). If not connected, an internal
pulldown transistor ensures low input level.
112
TDI
PU
Test Data Input
For Boundary Scan.
If not connected an internal pullup transistor ensures high
input level.
141
140
113
TMS
TCK
TDO
Test Mode Select
For Boundary Scan.
If not connected an internal pullup transistor ensures high
input level.
Test Clock
For Boundary Scan.
If not connected an internal pullup transistor ensures high
input level.
O
–
Test Data Output
For Boundary Scan
Data Sheet
63
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Pin Descriptions
2.5
Pin Strapping
Some pins are used for selection of functional modes of the QuadLIUTM
:
Table 3
PIN
Overview about the Pin Strapping
Pin Strapping is used
Always
Pin Strapping Function
IM(1:0)
A(5:0)
Defines the used micro controller interface
Only in SCI interface mode Defines the six LBSs of the SCI source address, see
Chapter 3.5.2.1
D(15:5)
Only in SCI or SPI
interface mode
Programs the parameters N and M of the PLL in the
master clocking unit instead of registers GCM5 and
GCM6, see Chapter 3.5.5:
- D(15:11) values programs PLL dividing factor M
- D(10:5) values programs PLL dividing factor N
Programming by pin strapping is equivalent to
programming by register bits GCM5.PLL_M(4:0) and
GCM6.PLL_N(5:0) which is used in asynchronous micro
controller modes.
Data Sheet
64
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
3
Functional Description
3.1
Hardware
The QuadLIUTM requires either two supply voltages, 1.8 V and 3.3 V, see Figure 8, or a single 3.3 V supply, with
the 1.8 V supply being generated internally by an on-chip regulator, see Figure 7. In order to minimize power
dissipation, it is recommended to operate the device using separate external 3.3 V and 1.8 V supplies. Please note
that the 1.8 V supply requires de-coupling whether generated on-chip or externally. Supply voltage selection is
done by the pin VSEL.
The pin IM1 is used to select the additional serial interfaces SPI and SCI bus, see also Chapter 2.5.
The pin READY_EN can be used to activate the output functionality of the additional pin READY/ DTACK. for the
asynchronous micro controller interface. Because the READY_EN pin is used for VSS in version 2.1, the pin
READY/ DTACK is not active (is in tri-state mode) if no change is made on the board. Therefore for the READY/
DTACK pin also no change must be made on the board. See also Chapter 3.5.1.
Some pins of the micro controller interface have different functions if the SPI or SCI bus is selected as interface
to the micro controller.
The pins RLAS2(1:4) of the additional separate analog switches at the receive line interfaces (supported only in
P/PG-LBGA-160-1 package) can be connected to VSSX if the analog switches are not used.
To accommodate the package several signals can be configured at the multifunction ports. Four multifunction
ports exist for the receive direction and four for the transmit direction for each of the four channels.
3.3 V
3.3 V
VDD
VDDX
VDDR
VDDP
VDDC
VDDC
VSEL
(can be left
open)
VDD , VDDP , VDDX , VDDR > VDDC
QuadLIU
VSS
must always be guaranteed,
also during power on and
power down sequences.
VSSP
VSSX
VSSR
QLIU_F0248
Figure 7
Single Voltage Supply
Data Sheet
65
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
1.8 V
3.3 V
VDD
VDDX
VDDR
VDDP
VDDC
VDDC
VSEL
VDD , VDDP , VDDX , VDDR > VDDC
QuadLIU
VSS
must always be guaranteed,
also during power on and
power down sequences.
VSSP
VSSX
VSSR
QLIU_F0249
Figure 8
Dual Voltage Supply
3.2
Software
The QuadLIUTM device contains analog and digital function blocks that are configured and controlled by an
external microprocessor or micro controller, using either the asynchronous interface, SPI bus or SCI bus.
The register address range is 10 bit wide.
3.3
Functional Overview
The main interfaces are
•
•
•
•
•
•
Receive and transmit line interface
Asynchronous Microprocessor interface with two modes: Intel or Motorola
SPI Bus interface
SCI Bus interface
Framer interface
Boundary scan interface
As well as several control lines for reset, mode and clocking purpose.
The main internal functional blocks are
•
•
•
•
•
•
•
•
•
•
Analog line receiver with equalizer network and clock/data recovery
Analog line driver with programmable pulse shaper and line build out
Master clock generation unit
Dual elastic buffers for receive and transmit direction, controlled by the appropriate jitter attenuators
Receive line decoding, alarm detection and PRBS monitoring
Transmit line encoding, alarm and PRBS generation
Receive jitter attenuator
Transmit jitter attenuator
Available test loops: Local loop, remote loop and payload loop
Boundary scan control
Data Sheet
66
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
3.4
Block Diagram
Figure 9 shows the block diagram of the QuadLIUTM
.
Receive
Jitter Attunator
MUX
FCLKR(1:4)
RDO(1:4)
RLAS2(1:4)
Analog Switch
Long+Short
Dual Receive
Elastic Buffer
Receive
RL1/ROID(1:4)
RL2(1:4)
RPA(1:4)
RPB(1:4)
RPC(1:4)
RPD(1:4)
Haul Receive
Line Decoder
PRBS Monitor
Framer
Line Interface
Clock &Data
Interface
IBL Monitor
Recovery
XDI(1:4)
XPA(1:4)
XPB(1:4)
XPC(1:4)
XPD(1:4)
Line Encoder
PRBS Gener.
IBL Generator
Transmit
Framer
Long+Short
Haul Transmit
Line Interface
Dual Transmit
Elastic Buffer
XL1/XOID(1:4)
XL2(1:4)
Interface
FCLKX(1:4)
Transmit
Jitter Attunator
MUX
TCLK
RCLK
Voltage
Regulator
Boundary Scan
JTAG
Asynchronous Micro
Controller Interface
Master Clocking
Unit
SCI Interface SPI Interface
CS
RD/DS ALE
RES
MCLK SYNC FSC
READY/TDACK
INT D(15:0)
READY_EN
IM(1:0) VSEL TDI,TMS,TCK,TRS,TDO
A(9:0)
WR/RW BHE/BLE DBW
QLIU_blockdiagram
Figure 9
Block Diagram
3.5
Functional Blocks
The four possible micro controller interface modes - two asynchronous modes (Intel, Motorola) and two serial
interface modes (SPI bus or SCI bus) - are selected by using the interface mode selection pins IM(1:0). This
selection is valid immediately after reset becomes inactive.
After changing of the interface mode by IM(1:0), a hardware reset must be applied.
3.5.1
Asynchronous Micro Controller Interface (Intel or Motorola mode)
The asychronous micro controller interface is selected if IM(1:0) is strapped to ´00B´ (Intel mode) or ´01B´
(Motorola mode).
An handshake signal (data acknowledge DTACK for Motorola- and READY for Intel-mode) is provided indicating
successful read or write cycle. By using DTACK or READY respectively no counter is necessary in the micro
controller to finish the access, see also timing diagrams Figure 51 ff.
If activated, READY/ DTACK is an open Drain (oD) output and will be only driven to low if CS is low. Therefore the
READY/ DTACK signals of two or more QuadLIUTM v3.1 can be connect together, using a common external pull-
up resistor (wired or).
The generation of READY /DTACK is asynchronous:
In Intel mode read access READY will be set to low by the QuadLIUTM after the data output is stable at the
QuadLIUTM. After the rising edge of RD (which is driven by the micro controller), READY is low for a “hold time”,
before it will be set to high by the QuadLIUTM
Data Sheet
.
67
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
In the Intel mode write access READY will be set to low by the QuadLIUTM after the falling edge of WR (which is
driven by the micro controller). After WR is high and data are written successfully into the registers of the
QuadLIUTM, READY will be set to high by the QuadLIUTM
.
The general timing diagrams are shown in Figure 51 to Figure 56.
The communication between the external micro controller and the QuadLIUTM is done using a set of directly
accessible registers. The interface can be configured as Intel or Motorola type with a selectable data bus width of
8 or 16 bits.
The external micro controller transfers data to and from the QuadLIUTM, sets the operating modes, controls
function sequences, and gets status information by writing or reading control and status registers. All accesses
can be done as byte or word accesses if enabled. If 16-bit bus width is selected, access to lower/upper part of the
data bus is determined by address line A0 and signal BHE / BLE as shown in Table 4 and Table 5.
Table 6 shows how the ALE (Address Latch Enable) line is used to control the bus structure and interface type.
The switching of ALE allows the QuadLIUTM to be directly connected to a multiplexed address/data bus.
3.5.1.1
Mixed Byte/Word Access
Reading from or writing to the internal registers can be done using a 8-bit (byte) or 16-bit (word) access depending
on the selected bus interface mode. Randomly mixed byte/word access is allowed without any restrictions.
Table 4
Data Bus Access (16-Bit Intel Mode)
BHE
A0
Register Access
QuadLIUTM Data Pins Used
0
0
1
1
0
1
0
1
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
D(15:0)
D(15:8)
D(7:0)
None
Table 5
Data Bus Access (16-Bit Motorola Mode)
BLE
A0
Register Access
QuadLIUTM Data Pins Used
0
0
1
1
0
1
0
1
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
D(15:0)
D(7:0)
D(15:8)
None
Table 6
ALE
Selectable asynchronous Bus and Microprocessor Interface Configuration
IM(1:0) Asynchronous Microprocessor Interface Mode Bus Structure
Constant
level
01
00
00
Motorola
Intel
De-multiplexed
De-multiplexed
Multiplexed
Switching
Intel
The assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends
on the selected asynchronous microprocessor interface mode:
Data Sheet
68
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Intel
(Address n + 1)
(Address n)
Motorola
(Address n)
(Address n + 1)
↑
↑
↓
↓
Data lines
D15
D8
D7
D0
n: even address
3.5.2
Serial Micro Controller Interfaces
Two serial interfaces are included to enable device programming and controlling:- Slave Serial Control Interface
(SCI) - Slave Serial Peripheral Interface (SPI)
By using the SCI Interface, the QuadLIUTM can be easily connected to Infineon interworking devices plus Infineon
SHDSL- and ADSL-PHYs so that implementation of different line transmission technologies on the same line card
easily is possible. The SCI interface is a three-wire bus and optionally replaces the parallel processor interface to
reduce wiring overhead on the PCB, especially if multiple devices are used on a single board. Data on the bus is
HDLC encapsulated and uses a message-based communication protocol.
If SCI interface with multipoint to multipoint configuration is used, address pins A(5:0) are used for SCI source
(slave) address pin strapping, see Table 3.
Note that after a reset writing into or reading from QuadLIUTM registers using the SCI- or SPI-Interface is not
possible until the PLL is locked: If the SCI-Interface is used no acknowledge message will be sent by the
QuadLIUTM. If the SPI-Interface is used pin SDO has high impedance (SDO is pulled up by external resistor). To
trace if the SPI interface is accessible, the micro controller should poll for example the register DSTR so long as
it read no longer the value ´FH ´.
3.5.2.1
SCI Interface
The Serial Control Interface (SCI) is selected if IM(1:0) is strapped to ´11H´.
The QuadLIUTM SCI interface is always a slave.
Figure 57 shows the timing diagram of the SCI interface, Table 62 gives the appropriate values of the timing
parameters.
Figure 10 shows a first application using the SCI interfaces of some QuadLIUTMs where point to point full duplex
connections are realized between every QuadLIUTM and the micro controller. Here the data out pins of the SCI
interfaces (SCI_TXD) of the QuadLIUTMs must be configured as push-pull (PP), see configuration register bit PP
in Table 9.
Figure 11 shows an application with Multipoint to multipoint connections between the QuadLIUTMs and the micro
controller (half duplex). Here the data out pin of the SCI interfaces (SCI_TXD) of all QuadLIUTMs must be
configured as an open Drain (oD), see configuration register bit PP in Table 9. The data out and data in pins
(SCI_RXD, SCI_TXD) of each QuadLIUTM are connected together to form a common data line. Together with a
common pull up resistor for the data line, all open Drain data out pins are building a wired And.
The Infineon proprietary Daisy-Chain approach is not supported
The group address of the SCI interface is ´00H´ after reset. Recommendation for configuring is ´C4H´ to be different
to the group addresses of all other Infineon devices.
In case of multipoint to multipoint applications the 6 MSBs of the SCI source address will be defined by
pinstrapping of the address pins A5 to A0. The two LSBs of the SCI source address are constant ´10B´, see
Table 9. The SCI source address can be overwritten by a write command into the SCI configuration register. For
applications with point to point connections for the SCI interface the source address is not valid.
Because 14 bits are used for the register addresses in the SCI interface macro the two MSBs of the 16 bit wide
register addresses are set fixed to zero.
Data Sheet
69
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Clk
TxData
RxData
PP
SCI_TXD
SCI_RXD
IM(1:0)
QuadLIU
Microprocessor
or
Interworking
Device
Clk
TxData
RxData
IM(1:0)
Clk
QuadLIU
QuadLIU
TxData
RxData
IM(1:0)
QLIU-Interfaces_2
Figure 10 SCI Interface Application with Point To Point Connections
Clk
oD
Data
SCI_TXD
SCI_RXD
A(5:0)
A(5:0)
IM(1:0)
QuadLIU
Micro-processor
or
Interworking
Device
Clk
Data
IM(1:0)
Data
IM(1:0)
QuadLIU
QuadLIU
Clk
A(5:0)
QLIU_SCI_halfduplex
Figure 11 SCI Interface Application with Multipoint To Multipoint Connection
The following configurations of the SCI interface of the QuadLIUTM can be set by the micro controller by a write
command into the SCI configuration register (control bits ´10B´, see Table 9, SCI register address is ´0000H´, see
Table 4 and Figure 13):
•
•
Half duplex/full duplex (reset value: Half duplex), bit DUP.
OpenDrain/push-pull (configuration of output pin to openDrain/push-pull is in general independent of the
duplex mode and must be set appropriately in application) (reset value: open Drain), bit PP.
CRC for transmit and receive on/off (reset value: off), bit CRC_EN.
Automatic acknowledgement of CMD messages on/off (reset value: off), bit ACK_EN.
Clock edge rising/falling (reset value: falling), bit CLK_POL.
•
•
•
•
Clock gating (reset value: off), bit CLK_GAT.
The following SCI configurations are fixed and cannot be set by the micro controller:
•
•
Interrupt feature is disabled, bit INT_EN = ´0´.
Arbitration always made with LAPD (only SCI applications like in Figure 10 and Figure 11 are possible), bit
ARB = ´0´.
The maximum possible SCI clock frequency is 6 MHz for point to point applications (full duplex) and about 2 MHz
for multipoint to multipoint applications, dependent on the electrical capacity of the bus lines of the PCB.
Figure 12 shows the message structure of the QuadLIUTM. The SCI interface uses HDLC frames for
communication. The HDLC flags mark beginning and end of all messages.
Data Sheet
70
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
HOST
QuadLIU
CMD
ACK
QLIU_SCI_message_structure
Figure 12 SCI Message Structure of QuadLIUTM
Every write into or read from a register of the QuadLIUTM is initiated by a command message CMD from the Host
(micro con roller) and is then confirmed by an acknowledge message ACK from the QuadLIUTM if in the SCI
configuration automatic acknowledgement is set (bit ACK_EN, see Table 9). Read commands are always
confirmed, independent on the bit ACK_EN.
The frame structure of this messages are shown in Figure 13.
In general the LSB of every byte is transmitted first and lower bytes are transmitted before higher bytes (regarding
the register address)
Source and destination addresses are 8 bits long. Only the first 6 bits are really used for addressing. The bit C/R
(Command/Response) distinguishes between a command and a response. The bit MS (Master/Slave) is ´0B´ for
all Slaves and ´1B´ for all masters, see Table 9 and Figure 13
The source address is defined by pinstrapping of A5 to A0 after reset, but other values can be configured by
programming of the SCI configuration register.
The payload of the write CMD includes two control bits (MSBs of the payload), which distinguish between the
different kind of commands, see Table 8, the 14 bit wide register address and the 8 bit wide data whereas the read
CMD payload includes only the control bits and the register address. Register addresses can be either QuadLIUTM
register addresses or SCI configuration register addresses. Because of the address space of the QuadLIUTM
really 10 LSBs of the 14 bit address are used in the QuadLIUTM. The 4 MSBs are ignored
,
The payload of the read ACK includes the content of the register (one byte) in addition to the payload of the write
ACK.
The Frame Check Sequence FCS has 16 bits and is build (or checked) over the address and payload according
to ISO 3309-1984.
The Read Status Byte RSTA of the acknowledge message shows the status of the received message and is built
by the SCI interface of the QuadLIUTM, see Figure 15 and Table 7.
The destination address in the ACK message is always the source address of the corresponding CMD (the
address of the micro controller), see Figure 14, because no CMD messages will be sent by the QuadLIUTM SCI
interface
Data Sheet
71
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
SCI HDLC Basic Frame Structure
Flag Address
Payload
FCS
Flag
Control
bits
Write CMD Frame Structure
Source
Destination
Address
14 bit Register
address
01111110
8 bit data
FCS
FCS
01111110
01111110
Address
00: write OctalFALC register
10: write SCI configuration
register
Read CMD Frame Structure
Source
Address
Destination
Address
14 bit Register
address
Read
Depth
01111110
01: read OctalFALC register
11: read SCI configuration
register
Write ACK Frame Structure
Source
Destination
Address
01111110
RSTA
RSTA
FCS
01111110
Address
Read ACK Frame Structure
Source
Address
Destination
Address
Register
Content
01111110
FCS
01111110
One Byte
t
6 bit
address
MS C/R
LSB
QLIU_SCI_frame_structure
Figure 13 Frame Structure of QuadLIUTM SCI Messages
Source
Address
Destination
Address
CMD
QuadLIU SCI Interface
Source address
RSTA register
Source
Address
Destination
Address
ACK
RSTA
QLIU_SCI_acknowledge
Figure 14 Principle of Building Addresses and RSTA bytes in the SCI ACK Message of the QuadLIUTM
Data Sheet
72
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
7 (MSB)
0 (LSB)
VFR RDO CRC RAB
SA1
SA0
C/R
TA
QLIU_SCI_RSTA
Figure 15 Read Status Byte (RSTA) byte of the SCI Acknowledge (ACK)
Table 7
Field
Read Status Byte (RSTA) Byte of the SCI Acknowledge (ACK)
Bit
Description
VFR
7
Valid Frame. Indicates whether a valid frame has received.
´0´: Received frame is invalid.
´1´: Received frame is valid.
RDO
CRC
6
5
Reserved
CRC compare check. Indicates whether a CRC check is failed or not.
´0´: CRC error check failed on the received frame.
´1´: Received frame is free of CRC errors.
RAB
4
Received message aborted. CMD message abortion is declared. The receive message
was aborted by the HOST. A sequence of 7 consecutive ´1´ was detected before closing
the flag. Note that ACK message and therefore RAB will not be send before destination
address was received.
´0´: Data reception is in progress.
´0´: Data reception has been aborted.
SA1
SA0
C/R
TA
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Table 8
Definition of Control Bits in Commands (CMD)
Command type
Control Bits
(MSB LSB)
01
00
10
11
Read QuadLIUTM registers
Write QuadLIUTM register1
Write SCI configuration register
Read SCI configuration register
Table 9
SCI Configuration Register Content
Address
Bit 7
Bit6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
´0000H´
´0001H´
´0002H´
PP
1
CLK_POL CLK_GAT ACK_EN
Destination Address
INT_EN
CRC_EN ARB
1 (=C/R)
1 (=C/R)
DUP
0 (=MS)
0 (=MS)
0
Group Address
3.5.2.2
SPI Interface
The Serial Peripheral Interface (SPI) is selected if IM(1:0) is strapped to ´10H´.
The SPI interface of the QuadLIUTM is always a slave.
Data Sheet
73
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Figure 16 and Figure 17 show the read and the write operation respectively. The start of a read or write operation
is marked by the falling edge of the chip select signal CS whereas the end of the operations is marked by the rising
edge of CS. Because of CS the SPI interface has no slave address.
The first bit of the serial data in (SDI) is ´1´ for a read operation and ´0´ for a write operation. The first four bits of
the 15 bit address are not valid for the QuadLIUTM
.
In read operation the QuadLIUTM delivers the 8 bit wide content of the addressed register at the serial data out
(SDO).
In general SPI data are driven with the negative edge of the serial clock (SCLK) and sampled with the positive
edge of SCLK. Figure 58 shows the timing of the SPI interface and Table 63 the appropriate timing parameter
values.
CS
SCLK
A9
10 bit address
A0
SDI
x
x
x
x
x
don´t care
8 bit data
D7
D0
high impedance
SDO
QLI U_SPI _read
Figure 16 SPI Read Operation
CS
SCLK
A9
10 bit address
A0 D7
8 bit data
D0
SDI
x
x
x
x x
high impedance
SDO
QLI U_SPI _writ e
Figure 17 SPI Write Operation
3.5.3
Interrupt Interface
Special events in the QuadLIUTM are indicated by means of an interrupt output INT, which requests the external
micro controller to read status information from the QuadLIUTM, or to transfer data from/to the QuadLIUTM. The
electrical characteristics (open drain or push-pull) is programmed defined by the register bits IPC.IC(1:0), see IPC.
The QuadLIUTM has a single interrupt output pin INT with programmable characteristics (open drain or push-pull,
defined by registers IPC) too.
Since only one INT request output is provided, the cause of an interrupt must be determined by the external micro
controller by reading the QuadLIUTM’s interrupt status registers (GIS, ISR(1:4), ISR6 and ISR7). The interrupt on
pin INT and the interrupt status bits are reset by reading the interrupt status registers. The interrupt status registers
ISR are of type “clear on read“ (“rsc”).
The structure of the interrupt status registers is shown in Figure 18.
Data Sheet
74
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
„Global“
Interrupt Status
Register GIS
(per channel)
VISPLL
IPC
Status Registers and Masking
(shown for one channel)
PLLLC
GIS2
1 to 4
PLLL
GIMR
SR1
ISR1
ISR1
PLL
IMR1
ISR2
R2
...
PLLLS not visible
IMR2
ISR2
SR3
Channel
...
ISR3
Interrupt Status
Register CIS ,
global
ISR3
SR4
IMR3
ISR4
...
IMR4
ISR4
...
ISR6
SR6
ISR6
SR7
ISR7
IMR6
...
ISR7
IMR7
VIS
INT
GCR
...
different Status bits
...
channel
GIS4
GIS3
GIS2
GIS1
channel
1to4
channel
QLIU_ISR_2
Figure 18 Interrupt Status Registers
Each interrupt indication bit of the registers ISR can be selectively masked by setting the corresponding bit in the
corresponding mask registers IMR. If the interrupt status bits are masked they neither generate an interrupt at INT
nor are they visible in ISR. All reserved bits in the mask registers IMR must not be written with the value ´0´.
GIS, the non-maskable “Global” Interrupt Status Register per channel, serves as pointer to pending interrupts
sourced by registers ISR(1:4), ISR6 and ISR7.
The non-maskable Channel Interrupt Status Register CIS serves as channel pointer to pending interrupts sourced
by registers GIS.
After the QuadLIUTM has requested an interrupt by activating its INT pin, the external micro controller should first
read the register CIS to identify the requesting interrupt source channel. Then it should read the Global Interrupt
Status register GIS to identify the requesting interrupt source register ISR of that channel.
After reading the assigned interrupt status registers ISR(1:4), ISR6 and ISR7, the pointer bit in register GIS is
cleared or updated if another interrupt requires service. After all bits ISR(7:0) of a register GIS are cleared, the
assigned bit in register CIS is cleared. After all bits in register CIS are cleared the INT pin will be deactivated.
If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes inactive.
Updating of interrupt status registers ISR(1:4), ISR6 and ISR7 and GIS is only prohibited during read access.
Data Sheet
75
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Masked Interrupts Visible in Status Registers
•
The “Global” Interrupt Status register (GIS) indicates those interrupt status registers with active interrupt
indications (bits GIS.ISR(7:0)).
•
An additional interrupt mode can be selected per port via bit GCR.VIS (GCR). In this mode, masked interrupt
status bits neither generate an interrupt on pin INT nor are they visible in GIS, but are displayed in the
corresponding interrupt status registers ISR(1:4), ISR6 and ISR7.
PLL Interrupt Status Register
•
•
The bit n (n = 1 to 4) of the register CIS pointers an interrupt on channel n.
The Global Interrupt Status register GIS2 indicates the lock status of the (global) PLL. Masking can be done
by the register GIMR.
•
An additional interrupt mode can be selected per port via bit IPC.VISPLL (IPC) where the masked interrupt
status bit GIS2.PLLLS does not generate an interrupt on pin INT, but is displayed in the corresponding
interrupt status register bit GIS2.PLLLC.
The additional interrupt mode is useful when some interrupt status bits are to be polled in the individual interrupt
status registers.
Table 10
Interrupt Modes
GCR.VIS; IPC.VISPLL
Appropriate Mask bit
Interrupt active
Visibility in ISR(1:4),
ISR(6:7) and GIS2
0
0
1
1
0
1
0
1
Yes
No
Yes
No
Yes
No
Yes
Yes
Note:
1. In the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not,
are reset when the interrupt status register is read. Thus, when polling of some interrupt status bits is desired,
care must be taken that unmasked interrupts are not lost in the process.
2. All unmasked interrupt statuses are treated as before.
Please note that whenever polling is used, all interrupt status registers concerned have to be polled individually
(no “hierarchical” polling possible), since GIS only contains information on actually generated, i.e. unmasked
interrupts.
3.5.4
Boundary Scan Interface
In the QuadLIUTM a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite
state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller
and boundary scan, meet the requirements given by the JTAG standard IEEE 1149.1-2001. Figure 19 gives an
overview, Figure 49 shows the timing diagram and Table 58 gives the appropriate values of the timing
parameters.
Data Sheet
76
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
TAP controller reset
TRS
TCK
TMS
TDI
clock
Clock
Generation
Reset
test
BD data in
control
1
2
TAP Controller
data in
enable
finite state machine
instruction register
test signal generator
control
bus
n
TDO
ID data out
data
out
BD data out
F0115
Figure 19 Block Diagram of Test Access Port and Boundary Scan
After switching on the device (power-on), a reset signal has to be applied to TRS, which forces the TAP controller
into test logic reset state.
The boundary length is t.b.d..
If no boundary scan operation is used, TRS, TMS, TCK and TDI do not need to be connected since pull-up or
pulldown transistors ensure default input levels in this case.
Test handling (boundary scan operation) is performed using the pins TCK (Test Clock), TMS (Test Mode Select),
TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, that means
TRS is connected to VDD or it remains unconnected due to its internal pull up. Test data at TDI is loaded with a
clock signal connected to TCK. "1" or "0" on TMS causes a transition from one controller state to another; constant
"1" on TMS leads to normal operation of the chip.
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out and enable) and
an I/O-pin (I/O) uses three cells (data in, data out and enable). Note that most functional output and input pins of
the QuadLIUTM are tested as I/O pins in boundary scan, hence using three cells.
The desired test mode is selected by serially loading a 8-bit instruction code into the instruction register through
TDI (LSB first), see Table 11. The test modes are:
EXTEST
Extest is used to examine the interconnection of the devices on the board. In this test mode at first all input pins
capture the current level on the corresponding external interconnection line, whereas all output pins are held at
constant values ("0" or "1"). Then the contents of the boundary scan is shifted to TDO. At the same time the next
scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan
contents and all input pins again capture the current external level afterwards, and so on.
SAMPLE
Is a test mode which provides a snapshot of pin levels during normal operation.
Data Sheet
77
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
IDCODE
A 32-bit identification register is serially read out on pin TDO. It contains the version number (4 bits), the device
code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to "1".
The ID code field is set to (MSB to LSB): t.b.d.
Version number (first 4 bits) = ´0001B´
Part Number (next 16 bits) = ´0000 0001 0000 0100B´
Manufacturer ID (next 11 bits) = 0000 1000 001B´
LSB fixed to ´1´.
BYPASS
A bit entering TDI is shifted to TDO after one TCK clock cycle.
An alphabetical overview of all TAP controller operation codes is given in Table 11.
Table 11
TAP Controller Instruction Codes
TAP Instruction
BYPASS
Instruction Code
11111111
EXTEST
00000000
IDCODE
00000100
SAMPLE
00000001
Reserved for device test
01010011
3.5.5
Master Clocking Unit
The QuadLIUTM provides a flexible clocking unit, which references to any clock in the range of 1.02 to 20 MHz
supplied on pin MCLK, see Figure 20.
The clocking unit has two different modes:
•
In the so called “flexible master clocking mode” (GCM2.VFREQ_EN = ´1´, GCM2) the clocking unit has to be
tuned to the selected reference frequency by setting the global clock mode registers GCM(8:1) accordingly,
see formulas in GCM6. All four ports can work in E1 or T1 mode individually. After reset the clocking unit is in
“flexible master clocking mode”.
•
In the so called “clocking fixed mode” (GCM2.VFREQ_EN = ´0´) the tuning of the clocking unit is done
internally so that no setting of the global clock mode registers GCM(8:1) is necessary. All four ports must work
together either in E1 or in T1 mode.
For the calculation for the appropriate register settings see GCM6. Calculation can be done easy by using the
flexible Master Clock Calculator which is part of the software support of the QuadLIUTM, see Chapter 8.3.
All required clocks for E1 or T1/J1 operation are generated by this circuit internally. The global setting depends
only on the selected master clock frequency and is the same for E1 and T1/J1 because both clock rates are
provided simultaneously.
To meet the E1 requirements the MCLK reference clock must have an accuracy of better than ± 32 ppm. The
synthesized clock can be controlled on pins RCLK and FCLKR.
Data Sheet
78
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
E1 Clocks
MCLK
T1 / J1
Clocks
Flexible Master Clock Unit
GCM1...GCM8
PLL
channel
1 to 4
D(15:5) IM(1:0)
QLIU__F0116
Figure 20 Flexible Master Clock Unit
3.5.5.1
PLL (Reset and Configuring)
If the (asynchronous) micro controller interface mode is selected by IM(1:0) the PLL must be configured
•
By programming of the registers GCM5 and GCM6 in “flexible master clocking mode”. Every change of the
contents of these registers - the divider factors N and M of the PLL - causes a reset of the PLL. Switching
between E1 and T1 modes in arbitrary channels causes a reset of the clock unit but not of the PLL itself.
Or by enabling of the ”fixed mode”: GCM2.VFREQ_EN = ´0´ (GCM2). Programming of registers GCM5 and
GCM6 is not necessary. Any programming of GCM5 and GCM6 does NOT cause a reset of the PLL. Switching
between E1 and T1 modes (for all channels) causes a reset of the clock unit but not of the PLL itself.
•
The SPI and SCI are synchronous interfaces and therefore need defined clocks immediately after reset, before
any configuration is done. So to enable access to serial interfaces, the clock MCLK must be active and must have
a defined frequency before reset becomes inactive. Dependent on the MCLK frequency the internal PLL must be
configured if the SCI- or SPI-Interface mode is selected by IM(1:0)
•
By strapping of the pins D(15:5) if “fixed mode” is not enabled (GCM2.VFREQ_EN = ´1´), see also Table 3.
Because “fixed mode” is not enabled after reset, pinstrapping at D(15:5) is always necessary! Every new value
at this pins causes a reset of the PLL. Configuring by the registers GCM5 and GCM6 is not taken into account
and causes not a reset of the PLL
•
Or by enabling of the ” fixed mode”.This is only allowed if the values of N and M defined by pinstrapping are
identical to that values which are internally used for the “fixed mode”. That avoids changing of N and M by
switching into the ”fixed mode” and therefore a new reset of the PLL. (A new reset of the PLL can cause a hang
up of the whole system!) In ”fixed mode” the values are: N = ´3310´, M = ´010´ so that the pinstrapping must be:
D(10:5) = ´HLLLLH´, D(15:11) = ´LLLLL´. In ”fixed mode” programming of registers GCM1 to GCM8 is no
longer necessary and values at the pins D(15:5) are no longer taken into account and causes NOT a reset of
the PLL. A switching between E1 and T1 modes causes a reset of the clock unit but not of the PLL itself.
The configuration of the PLL by pinstrapping (see Table 3) in case of serial interface modes is done in the same
way as by using the registers GCM5 and GCM6 if asynchronous micro controller interface mode (Intel or Motorola)
is selected. So calculation of the pinstrapping values can be done also by using the formulas in GCM6 or by using
the “flexible Master Clock Calculator” which is part of the software support of the QuadLIUTM, see Chapter 8.3. If
the serial interfaces are selected, pinstrapping of D(15:5) configure the PLL directly, so changes causes always a
reset of the PLL.
The conditions to trigger a reset of the central clock PLL are listed in Table 12. Every reset of the PLL causes a
reset of the clock system.
Data Sheet
79
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Table 12
Conditions for a PLL Reset
Reset Pin GCM2.VFREQ_EN Used controller
interface
A PLL reset is made if ...
Active
X (will be set to ´1´
by reset)
X
Always
Inactive
1
Asynchron
(Motorola or Intel)
If GCM5 or GCM6 are written and their values N or M
change
SPI or SCI
If pinstrapping values change
Never
0
Asynchron
(Motorola or Intel)
SPI or SCI
If pinstrapping values change
0 -> 1 or 1 -> 0
Asynchron
If actual values of N or M in GCM5 or GCM6 are
(Motorola or Intel)
different to internal settings of the “clocking fixed mode”
SPI or SCI
If pinstrap values are different to internal settings of the
“clocking fixed mode”; That is not allowed!
3.6
Line Coding and Framer Interface Modes
An overview of the coding at the line interface and the Modes at the framer interface is given in Table 13.
Table 13
Line Coding and Framer Interface Modes
Register Bits Signals at Pins
Line Code,
Framer IF
Mode
FMR0.RC, FMR0.XC, RDON (RPC)
LIM3.DRR LIM3.DRX
RDO
XDI
XDIN (XPB)
AMI, single rail 10
0
10
0
Pos and neg
AMI error
Neg
Pos, via
encoder
Neg, via
encoder
AMI, dual rail
10
1
10
1
Pos
Pos, encoder
bypass
Neg, encoder
bypass
HDB3/B8ZS,
single rail
11
0
11
0
Decoded data
Pos
Violation
Neg
Via encoder
(HDB3/B8ZS
coding)
HDB3/B8ZS,
dual rail
11
1
11
1
Via encoder
(HDB3/B8ZS
coding)
NRZ, single rail 00
0
00
0
Pos
´0´
NRZ, via
encoder
Frame marker
Frame marker
(CMI coding)
(CMI coding)
NRZ, dual rail
00
1
00
1
Pos
Neg
NRZ
CMI, single rail 01
0
01
0
Decoded data
Pos
Violation
Neg
Via encoder
Via encoder
CMI, dual rail
01
1
01
1
Data Sheet
80
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Table 13
Line Coding and Framer Interface Modes (cont’d)
Register Bits Signals at Pins
Line Code,
Framer IF
Mode
FMR0.RC, FMR0.XC, RDON (RPC)
LIM3.DRR LIM3.DRX
RDO
XDI
XDIN (XPB)
0 -> 1 or 1 Asynchron If actual values
-> 0
(Motorola of N or M in
or Intel) GCM5 or GCM6
are different to
internal settings
of the “clocking
fixed mode”
SPI or SCI If pinstrap
values are
different to
internal settings
of the “clocking
fixed mode”;
That is not
allowed!
3.6.1
Bipolar Violation Detection
If the register bit BFR.BPV is set to ´0´ and after execution of the sequence described below, Bipolar Violations
(BPV) consisting on single ´1´ pulses (separated from the previous ´1´ pulse by at least one ´0´ pulse) or on two
consecutive ´1´ pulses are detected correctly and thus counted by the bipolar violation counter. Bipolar Violations
(BPV) consisting on more than two consecutive ´1´ pulses are not detected correctly and thus not counted by the
bipolar violation counter.
Compatibel to the QuadFALC V2.1, Bipolar Violations (BPV) are not detected correctly and thus not counted by
the bipolar violation counter, if BFR.BPV is set to ´1´ (default after reset).
If the second of two consecutively received Alternate Mark Inversion (AMI) pulses is a BPV (second pulse has the
same polarity as the first pulse) and BFR.BPV is set to ´1´, the receiver converts the second AMI pulse to a logic
zero. This conversion will cause a bit error and will mask detection and counting of the BPV. In contrast, any BPV
separated from the previous ´1´ pulse by at least one ´0´ pulse is detected, counted, and recorded correctly
This BPV conversion is not expected to cause any system level problems. BPV counts, bit errors counts, and CRC
counts may be slightly inaccurate, depending on the BPV rate. Note that the special B8ZS and HDB3 substitution
do not contain consecutive BPV pulses so the conversion described above will not occur when receiving these
patterns
The behaviour of the Bipolar Violation Detection is illustrated in Figure 21.
Data Sheet
81
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
0
+1
0
-1
0
+1 -1 +1
0
+1
0
-1 +1 -1 -1
0 +1 -1 -1 -1
RL1
RL2
BPV always
detected
BPV detected if BPV detected if
BFR.BPV = ´0´ BFR.BPV = ´0´
BPV not
detected
Internal Signals:
P
N for
BFR.BPV
= ´1´
Databits set to´0´,
BPV not detected
BPV for
BFR.BPV
= ´1´
N for
BFR.BPV
= ´0´
BPV
BPV for
BFR.BPV
= ´0´
Figure 21 Behaviour of Bipolar Violation Detection
Independent from the setting of BFR.BPV all BPVs will be detected
•
•
In patterns with alternate ´1´ and ´0´ (50 % ´1´ density)
In all fixed patterns with no consecutive ´1´ (less than 50 % ´1´ density)
For BFR.BPV = ´1´ and execution of the sequence described below, variable or fixed patterns with at least two
consecutive ´1´ pulses will show reduced BPVs. Reduction of BPVs depends on densitiy of ´1´ pulses. As ´1´ pulse
density increases, BPV rate decrease until the limiting case of “all-one”. In framed “all-one” pattern no BPVs will
be detected, except a BPV following a frameing bit that is ´0´.
For BFR.BPV = ´0´ variable or fixed patterns with at maximum two consecutive ´1´ pulses will show no reduced
BPVs.
Sequence
If the register bit BFR.BPV is set to ´0´, additionally the global registers REGFP and REGFD must be written with
the following sequence to configure the best performance of the Bipolar Violation detection for all four channels:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Write ´2CH´ into REGFP
Write ´FFH´ into REGFD
Write ´ACH´ into REGFP
Write ´2BH´ into REGFP
Write ´00H´ into REGFD
Write ´ABH´ into REGFP
Write ´2AH´ into REGFP
Write ´FFH´ into REGFD
Write ´AAH´ into REGFP
Write ´29H´ into REGFP
Write ´FFH´ into REGFD
Write ´A9H´ into REGFP
Write ´28H´ into REGFP
Write ´00H´ into REGFD
Write ´A8H´ into REGFP
Write ´27H´ into REGFP
Write ´FFH´ into REGFD
Data Sheet
82
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
•
•
Write ´A7H´ into REGFP
Write ´00H´ into REGFP
Note that the configuration of the Bipolar Violation detection by these sequence is reset by a receive reset
(CMDR.RRES = ´1´)
3.7
Receive Path
An overview about the receive path of one channel of the QuadLIUTM is given in Figure 22.
RDO
Clock &
RL1/ROID
RL2
Data
Dual Receive Elastic Buffer
Equalizer
Decoder
RDON
Recovery
DPLL
internal
receive
Receive Line
Interface
FCLKR
RCLK
from other
channels
clock
J
LOS
D
Analog
Alarm
A
LOS
Detector
Detector
Recovered
clock selection
DCO-R
C
SYNC
MCLK
Master
Clocking Unit
A: controlled by CMR5.DRSS(2:0)
QLIU_F0117
C: controlledby CMR1.DCSand LIM0.MAS
D: controlled by CMR4.RS(2:0)
J: controlled by CMR2.IRSC and DIC1.RBS(1:0)
Figure 22 Receive System of one Channel
The recovered clock selection of Figure 22 (multiplexer “A”) is shown in more detail in Figure 23.
The multiplexer “C” in Figure 22 selects the mode of the receive jitter attenuator, see chapter Chapter 3.7.8.
The multiplexer “D” in Figure 22 selects if the receive clock RCLK of a channel is sourced by the recovered route
clock or by the DCO-R (see above). The appropriate control register bits are CMR4.RS(2:0) (CMR4). These
register bits selects also different DCO-R output frequencies.
The sources of the receive clock output pins of the QuadLIUTM (RCLK(4:1)), can be selected out of the receive
clocks of the channels:
The source of each of the four receive clock pins of the QuadLIUTM (RCLK(4:1)) can be independently selected
out of each of the four receive clocks of the channels by programming the registers bits GPC(2:6).RS(2:0) (GPC2),
see cross connection “B” in Figure 23.
Data Sheet
83
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
channel 1
channel 2
channel 3
channel 4
A
A
A
A
Recovered clock
Recoveredclock
Recoveredclock
Recovered clock
to
to
to
to
selection
selection
selection
selection
DCO_R
DCO_R
DCO_R
DCO_R
C
C
C
C
RCLK
RCLK
RCLK
RCLK
SYNC
pins
B
RCLK1
RCLK2
RCLK3
RCLK4
A: controlled by CMR5.DRSS(2:0)
B: controlled by GPC(2:4).RS(2:0)
Receive clock
selection
QLIU_rec_clk_sel_2
Figure 23 Recovered and Receive Clock Selection
3.7.1
Receive Line Interface
For data input, two different data types are supported:
•
Ternary coded signals received at pins RL1 and RL2 from 0 dB downto -43 dB for E1 or downto -36 dB for
T1/J1 ternary interface. The ternary interface is selected if LIM1.DRS is cleared.
Unipolar data (CMI code) on pin ROID received from an optical interface. The optical interface is selected if
LIM1.DRS is set and MR0.RC(1:0) = ´01b´.
•
3.7.2
Receive Line Coding
In E1 applications, HDB3 line code and AMI coding is provided for the data received from the ternary interface. In
T1/J1 mode, B8ZS and AMI code is supported. Selection of the receive line code is done with register bits
MR0.RC(1:0) (MR0). In case of the optical interface the CMI Code (1T2B) with HDB3 or AMI postprocessing is
provided. If CMI code is selected the receive route clock is recovered from the data stream. The CMI decoder does
not correct any errors. The HDB3 code is used along with double violation detection or extended code violation
detection (selectable by MR0.EXZE)). In AMI code all code violations are detected. The detected errors increment
the code violation counter (16 bits length).
The signal at the ternary interface is received at both ends of a transformer.
An overview of the receive line coding is given in Table 13.
3.7.3
Receive Line Interface
Each of the QuadLIUTM receivers includes an integrated switchable resistor RTERM = 300 Ω .
Only for P/PG-LBGA-160-1 package it also includes an integrated analog switch, see Figure 24. In this case the
connectors RLAS2(1:4) must not be connected to VSSX. This allows the device to support 100 Ω T1, 110 Ω J1,
120 Ω E1 and 75 Ω E1 applications with a single bill of materials (so called “generic” modes).
The 300 Ω switch is controlled by the registerbit LIM0.RTRS (LIM0). The multi purpose analog switch is controlled
by LIM2.MPAS. So a simple software controlling of both switches is possible, independent from one another.
To enable switching of the separate analog switches of all four ports in general the register bits
GPC(3:6).ENMPAS must be all set to ´1´. This is an additional protection to avoid closing of the analog switches
if its connectors RLAS2(1:4) are connected to VSSX in fully QuadLIUTM Version 1.2 hardware compatible
Data Sheet
84
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
applications. Closing of the separate analog switches if its connectors RLAS2(1:4) are connected to VSSX
the device might get demaged.
It is also possible to control both switches by using a combination of both hardware and software using one (but
not more) of the receive Multi Function Ports as a Receive Line Termination (RLT) input.
It is proposed that the Multi Function Port RPB be used for the RLT input, if this is the case then the
PC2.RPC2(3:0) register bits must be programed to ´1000b´, see Table 34.
If RLT is configured at one of the Multi Function Ports, the RTERM = 300 Ω switch is controlled by the logical function
(LIM0.RTRS == RLT) & LIM2.MPAS and the analog switch is controlled by the logical function LIM0.RTRS ==
RLT, were “==” means logical equivalence.
This enables a simple redundancy application using only one common board signal for switching between two
channels. While one channel terminates the receive line with an impedance matched to the line impedance Z0, the
other channel is in high impedance mode (both switches are óff´).
Table 14 shows the controlling of the switches (if GPC(3:6).ENMPAS = ´1111b´).
Table 14
Controlling of the Receive Interface Switches
300 Ohm
Switch
Analog
Switch
RLT is not Configured
RLT is Configured
LIM0.RTRS
LIM2.MPAS
LIM0.RTRS == RLT LIM2.MPAS
off
off
on
on
off
on
off
on
0
0
1
1
0
0
X
1
1
0
0
1
Not applicable1)
1
1
1) Because makes no sense for redundancy applications
externally
internally
RL1
RL2
Z0
RE
RTERM
RS
RLAS2
QLIU_analog_switches_1
Figure 24 General Receiver Configuration with Integrated Resistor and Analog Switches for Receive
Impedance Matching
This type of control offers very flexible receiver configurations which are described in the next chapters:
3.7.3.1
“Generic” Receiver Interface
A “generic” receiver configuration, using the same resistor RE = 100 Ω for all applications with different line
impedances Z0, is shown in Table 15.
Data Sheet
85
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Table 15
Generic Receiver Configuration Example
Line Impedance Z0 External Resistor
RE
External Resistors 300 Ohm Switch
S1 and RS2
Analog Switch
R
120 Ω
100 Ω
75Ω
100 Ω (for common
E1/T1/J1
applications)
off
off
on
----
not used
This example uses the 300 Ω switch to switch between 100 Ω and 75 Ω termination resistance for the different line
impedances, the analog switch is not used.
3.7.3.2
Receive Line Monitoring Mode (RLM)
For short-haul monitoring applications, the receive equalizer can be switched into receive line monitoring mode
(RLM) by setting of the register bit LIM0.RLM. One channel is used as a short-haul receiver while the other is used
as a short-haul monitor, see Figure 25. In this mode the receiver sensitivity of the monitor is increased to detect
an incoming signal of -20 dB resistive attenuation.
t2 : t1
RL1
E1/T1/J1
FALC®
(Receiver)
R
Receive
E
Line
RL2
LIM0.RLM=0
R3
R3
t2 : t1
RL1
RL2
FALC®
R
E
(Monitor)
resistive -20 dB network
LIM0.RLM=1
F0074
Figure 25 Principle of Receive Line Monitoring RLM (shown for one line)
3.7.3.3
Monitoring Application using RLM
A monitoring application using the receive line monitoring mode is shown in Figure 26. Both, the 300 Ω switch and
the separate analog switch are always óff´, so that in P/PG-LBGA-160-1 package the pins RLAS2 can be
connected to VSSX and HW compatibility to the QuadLIUTM V2.1 is fullfiled.
Data Sheet
86
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
RSER
XL1
E1/T1/J1
Transmit
Line
XDI
RSER
receiver
channel
XL2
RL1
E1/T1/J1
Receive
Line
RE
RDO
RSIG
RL2
XL1
R
SER
R3
XDI
R
monitor
channel
SER
XL2
RL1
RE
RDO
RSIG
RL2
QFALC_monit or_RLM
Figure 26 Monitoring Application using RLM (shown for one line)
The required resistor and transformer values are given in Table 16.
Table 16
External Component Recommendations for Monitoring Applications using RLM
Parameters of
Line Impedance Z0
Line Impedance Z0
external components1)
E1
T1
J1
75 Ohm
75 Ω
120 Ohm
120 Ω
510 Ω
100 Ohm
100 Ω
430 Ω
110 Ohm
110 Ω
470 Ω
RE (±1 %)
R3 (±1 %)
RSER
330 Ω
See Chapter 3.9.1
t2 : t1
1 :1
1 :1
1 : 1
1 : 1
1) This includes all parasitic effects caused by circuit board design.
3.7.3.4
Redundancy Application using RLM
In general for redundancy applications (“protection switching”) one channel is active while the other is in stand-by
mode.
Switching between active and stand-by mode can be done by software and by hardware.
Software controlled switching can be done on the line side in transmit direction by using the register bit XPM2.XLT.
Combined hardware and software controlled switching can be done on the line side in transmit direction by a
hardware signal if a Multi Function Port is configured as tristate input XLT. It is proposed that the Multi Function
Port XPA be used for XLT or XLT input respectively, if this is the case then the PC1.XPC1(3:0) register bits must
be programed, see Table 34. For one channel the Multi Function Port XPA must be programmed as low active
(PC1.XPC1 = ´1110b´) and for the other channel as high active (PC1.XPC1 = ´1000b´), so that no external inverter
Data Sheet
87
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
is necessary. So switching between both channels on line side is possible using only one signal as it is shown in
Figure 27.
If XLT or XLT is configured, the value of the register bit XPM2.XLT and the value of XLT are logically ored to control
the transmit line side. (That means if XPA is configured as low active then the line side is in tristate mode for
tristate = XPM2.XLT or not(XPA).
Because the register bit XPM2.XLT and the Multi Function Port XPA exist individually for every channel, switching
on the line side in transmit direction can be done between channels of different or of the same QuadLIUTM device.
This enables a simple application using only one common board signal for switching between two channels were
both transmit channels are working in parallel (see Figure 27). While one of them is driving the line, the other one
is switched into transmit line tristate mode.
The receive system interface pins RDO, RSIG, SCLKR and RFM can be set by software into tristate mode
constantly using the register bit SIC3.RRTRI. In this mode “tristate” means high impedance against VDD and VSS:
No internal pull up or pull down resistor is present.
Combined hardware and software controlling of the tristate mode can be done by a hardware signal if a Multi
Function Port is configured as RTDMT input . It is proposed that the Multi Function Port RPA be used for RTDMT,
if this is the case then the PC1.RPC1(3:0) register bits must be programed, see Table 34. If RTDMT is configured
the value of the register bit SIC3.RRTRI and the value of RTDMT are logically exored.
This enables a simple application using only one common board signal for switching between two channels. While
one of them is driving the system receive interface, the other one is switched into tristate mode.
An overview about the tristate configurations of RDO, RSIG, SCLKR and RFM is given in Table 17.
Table 17
Tristate Configurations for the RDO, RSIG, SCLKR and RFM Pins
SIC3.RRTRI /
SIC3.RTRI
Pins RDO and RSIG
Pins SCLKR and RFM
SIC3.RRTRI exor RTDMT
if RTDMT is selected on
Multi Function Port
1
X
Constant tristate (without Constant tristate (without
pull up and pull down
resistor)
pull up and pull down
resistor)
0
0
0
1
Never tristate
Never tristate
Never tristate
Tristate during inactive
channel phases (with pull
up resistor
Switching between both channels can be done on the system side in the receive direction by using the register bit
SIC3.RRTRI and with or without selection of the Multi Function Port as RTDMT. If the RTDMT function is selected,
the values of RTDMT and SIC3.RRTRI are logically exored. If in one channel SIC3.RRTRI is set, RTDMT is active
low because of the logical exor, and if in the other channel SIC3.RRTRI is cleared, RTDMT is active low because
of the logical exor. So switching between both channels on the system side in the receive direction is possible
using only one board signal.
For application using RLM for protection switching the XLT, XLT and RTDMT Multi Function Ports operate in
conjunction with the SIC3.RRTRI bits. Switching between channels can be done together on the system and the
line side with only one common board signal, connected to XPA (XLT, XLT) and RPA (RTDMT), as shown in
Figure 27 and Table 17: If this signal has low level channel 1 is active and channel 2 is in stand-by, if it has high
level channel 1 is in stand-by and channel 2 is active.
Different line impedances require different resistor values as shown in Table 16. Both switches are always off so
that LIM0.RTRS and GPC1.MPAS must be always ´0´.
If both channels are configured identically and supplied with the same system data and clocks, the transmit path
can be switched from one channel to the other without causing a synchronization loss at the remote end.
Data Sheet
88
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Table 18
Configuration for Redundancy Application using RLM, switching with only one board signal
Configuration
Register Bits
Channel 1
Channel 2
(active/stand-by)
(stand-by/active)
XLT, XLT
PC1.XPC1(3:0)
1000
1110
RTDMT
PC1.RPC1(3:0)
SIC3.RRTRI
LIM0.RLM
1101
1101
Receive system interface
RLM mode
0
0
0
0
1
1
0
0
Analog switch (always off) LIM2.MPAS
300 Ω switch (always off) LIM0.RTRSS
RSER
XL1
E1/T1/J1
Transmit
Line
XDI
RSER
active/stand-by
channel
SIC3.RRTRI = ´0´
LIM0.RLM = ´0´
XL2
RL1
E1/T1/J1
Receive
Line
RE
RDO
RSIG
RTDMT
XLT
RL2
XL1
(XPA)
(RPA)
R
SER
R3
XDI
R
active/stand-by
channel
SIC3.RRTRI = ´1´
LIM0.RLM = ´1´
SER
XL2
RL1
RE
RDO
RSIG
XLT
RTDMT
RL2
(XPA)
(RPA)
QLIU_receiver_redun_RLM
´low´/´high´
Figure 27 Redundancy Application using RLM (shown for one line)
3.7.3.5
General Redundancy Applications
Using the integrated analog switch of the QuadLIUTM general redundancy applications are possible were no
additional resistive network is necessary. Therefore, unlike in the redundancy application using RLM, long haul
redundancy applications are possible as there are no serial resistors in the receive path.
For these applications all of the hardware control functions described in Chapter 3.7.3.4 are used in the same
way. Additionally the hardware control function of the receive interface switches is used: By configuring one of the
Multi Function Ports in both of the two channels to RLT, the receive interfaces of these channels can be connected
on one receive line as shown in Figure 28.
If RLT is configured at the Multi Function Port RPB (proposed) by programming of the register bits PC2.RPC2(3:0)
the configuration for the redundancy mode application is listed in Table 19.
The analog switch is connected at the resistor RS.
Data Sheet
89
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Switching between active and stand-by modes can be achieved by a single common board signal which is
connected at the RLT, XLT and RTDMT inputs of both channels . In this application both receive channels are
working in parallel for redundancy purpose. While one of them builds an interface with a receive termination
resistance matched to the line impedance Z0 , the other one is switched into high impedance mode.
RSER
XL1
E1/T1/J1
Transmit Line
XDI
Active/stand-by
Channel
RSER
XL2
RL1
SIC3.RRTRI = ´0´
LIM0.RTRS = ´0´
E1/T1/J1
Receive Line
RLAS2
RDO
RS
RSIG
RL2
XLT
RLT RTDMT
(XPA) (RPB) (RPA)
RSER
XL1
XDI
stand-by/active
Channel
RSER
XL2
RL1
SIC3.RRTRI = ´1´
LIM0.RTRS = ´1´
RLAS2
RL2
RDO
RS
RSIG
XLT
RLT RTDMT
(XPA) (RPB) (RPA)
´low´/´high´
QLIU_longhaul_red
Figure 28 General Redundancy Application (shown for one line)
Table 19
General (proposed) Configuration for Redundancy Applications, Switching with only one
Board Signal
Configuration
Register Bits
Channel 1
Channel 2
(active/stand-by)
(stand-by/active)
XLT, XLT
PC1.XPC1(3:0)
1000
1110
RTDMT
PC1.RPC1(3:0)
PC2.RPC2(3:0)
SIC3.RRTRI
LIM0.RTRS
1101
1101
RLT
1000
1000
Receive system interface
Receive line interface
RLM mode
0
0
0
1
1
0
LIM0.RLM
Two types of general redundancy applications like shown in Figure 28 can be configured:
•
A first application were the values of the external resistors RS and RSER are dependend on the line impedance
Z0.
•
A so called “generic” redundancy application were the values of the external resistors RS and RSER are fix for
different line impedances Z0.
For both applications the general configuration shown in Table 19 is used.
Data Sheet 90
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
In the first (“non-generic”) application only the analog switch is used. These switch is ´on´ in the active and ´off´ in
the stand-by channel. The 300 Ω switch is unused (always ´off´, register bit LIM2.MPAS of both channels is always
´0´). Also the transmit interface works in a non-generic mode (see Chapter 3.9.1): The register bit PC6.TSRE of
both channels is always ´0´. The configuration (additional to that of Table 19) is shown in Table 20:
Table 20
Configuration for “non-generic” Redundancy Applications, Switching with only one Board
Signal
Line Impedance Z0
[Ohm]
RS [Ohm]
RSER [Ohm]
LIM2.MPAS
PC6.TSRE
120
110
100
75
95
70
5.5 or 0, see
Table 28
0
0
In the generic redundancy application different line impedances Z0 can be used without changing the board.
Additionally to the the analog switch the 300 Ω switch is used to match the termination resistance to the different
line impedances Z0 (register bit LIM2.MPAS of both channels). In the active channel this switch is ´on´ if the line
impedance is 75 Ω and ´off´ otherwise. In the stand-by channel this switch is always óff´, see Table 22.
Also the transmit interface works in a generic mode (see Chapter 3.9.1) using the register bit PC6.TSRE of both
channels.
The configuration (additional to that of Table 19) is shown in Table 21:
Table 21
Line Impedance Z0
[Ohm]
Configuration for “generic” Redundancy Applications, Switching with only one Board Signal
RS [Ohm]
RSER [Ohm]
LIM2.MPAS
PC6.TSRE
120
110
100
75
0
1
See Table 28
95
0
Table 22 illustrates the switching in the receive path used in the “generic” redundancy application:
Table 22
Channel
Switching in “Generic” Redundancy Application
300 Ohm Switch
Analog Switch
Active channel
Off, if Z0 is 120 Ω,110 Ω or 100 Ω (GPC1.MPAS = ´0´) On
On, if Z0 is 75 Ω (LIM2.MPAS = ´1´)
Stand-by channel
Off
Off
3.7.4
Loss-of-Signal Detection
There are different definitions for detecting Loss-Of-Signal (LOS) alarms in the ITU-T G.775 and ETS 300233. The
QuadLIUTM covers all these standards. The LOS indication is performed by generating an interrupt (if not masked)
and activating a status bit. Additionally a LOS status change interrupt is programmable by using register GCR.SCI.
•
Detection: An alarm is generated if the incoming data stream has no pulses (no transitions) for a certain
number (N) of consecutive pulse periods. A pulse with an amplitude less than Q dB below nominal is the criteria
for “no pulse” in the analog receive interface (LIM1.DRS = ´0´) (LIM1). The receive signal level Q is
programmable by three control bits LIM1.RIL(2:0) see Table 56. The number N can be set by an 8-bit register
(PCD). The contents of the PCD register is multiplied by 16, which results in the number of pulse periods, i.e.
the time which has to suspend until the alarm has to be detected. The programmable range is 16 to 4096 pulse
Data Sheet
91
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
periods. ETS300233 requires detection intervals of at least 1 ms. This time period results always in a LFA
(Loss of Frame Alignment) before a LOS is detected.
•
Recovery: In general the recovery procedure starts after detecting a logical one (digital receive interface) or a
pulse (analog receive interface) with an amplitude more than Q dB (defined by LIM1.RIL(2:0)) of the nominal
pulse. The value in the 8-bit register PCR defines the number of pulses (1 to 255) to clear the LOS alarm.
If a loss-of-signal condition is detected in long-haul mode, the data stream can optionally be cleared automatically
to avoid bit errors before LOS is indicated. The Selection is done by LIM1.CLOS = ´1´.
3.7.5
Receive Equalization Network
The QuadLIUTM automatically recovers the signals received on pins RL1 and RL2 in a range of up to -43 dB for
E1 or -36 dB for T1/J1. The maximum reachable length with a 22 AWG twisted pair cable is about 1500 m for E1
and about 2000m (~6560 ft) for T1. The integrated receive equalization network recovers signals with up to -43
dB for E1 or -36 dB for T1/J1 of cable attenuation automatically. Noise filters eliminate the higher frequency part
of the received signals. The incoming data is peak-detected and sliced to produce the digital data stream. The
slicing level is software selectable in four steps (45%, 50%, 55%, 67%), see Table 56. For typical E1 applications,
a level of 50% is used. The received data is then forwarded to the clock & data recovery unit.
3.7.6
Receive Line Attenuation Indication
Status register RES reports the current receive line attenuation
•
•
For E1 in a range from 0 to -43 dB in 25 steps of approximately 1.7 dB each.
For T1/J1 in a range from 0 to -36 dB in 25 steps of approximately 1.4 dB each.
The least significant 5-bits of this register indicate the cable attenuation in dB. These 5-bits are only valid in
combination with the most significant two bits (RES.EV(1:0) = ´01b´).
3.7.7
Receive Clock and Data Recovery
The analog received signal on pins RL1 and RL2 is equalized and then peak-detected to produce a digital signal.
The digital received signal on pins RDIP and RDIN is directly forwarded to the clock & data recovery. The so called
DPLL (digital PLL) of the receive clock & data recovery extracts the route clock from the data stream received at
the RL1/2 or ROID lines. The clock & data recovery converts the data stream into a dual-rail, unipolar bit stream.
The clock and data recovery uses an internally generated high frequency clock out of the master clocking unit
based on MCLK.
The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 UI.
3.7.8
Receive Jitter Attenuator
The receive jitter attenuator is based on the DCO-R (digital clock oscillator, receive) in the receive path. Jitter
attenuation of the received data is done in the dual receive elastic buffer. The working clock is an internally
generated high frequency clock based on the clock provided on pin MCLK. The jitter attenuator meets the E1
requirements of ITU-T I.431, G. 736 to 739, G.823 and ETSI TBR12/13 and the T1 requirements of AT&T
PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431, G.703 and G. 824.
The internal PLL circuitry DCO-R generates a "jitter-free" output clock which is directly dependent on the phase
difference of the incoming clock and the jitter attenuated clock. The receive jitter attenuator can be synchronized
either on the extracted receive clock RCLK or on a 2.048 MHz/8 kHz or 1.544 MHz/8 kHz clock provided on pin
SYNC (8 kHz in master mode only). The jitter attenuated DCO-R output clock can be output on pin RCLK and
FCLKR. Optionally an 8 kHz clock is provided on pin SEC⁄FSC.
For jitter attenuation the received data is written into the receive elastic buffer with the recovered clock sourced by
the clock & data recovery and are read out with the de-jittered clock sourced by DCO-R.
If the receive elastic buffer is read out directly with the recovered receive clock, no jitter attenuation is performed.
If the receive elastic buffer is read out with the receive framer clock FCLKR, the receive elastic buffer performs a
clock adoption from the recovered receive clock to FCLKR.
Data Sheet
92
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
The DCO-R circuitry attenuates the incoming jittered clock starting at its corner frequency with 20 dB per decade
fall-off. Wander with a jitter frequency below the corner frequency is passed unattenuated. The intrinsic jitter in the
absence of any input jitter is < 0.02 UI.
The corner frequency of the DCO-R can be configured in a wide range, see Table 23 and Figure 29. The jitter
attenuator PLL in the transmit path, so called as DCO-X, is equivalent to the DCO-R so that the principle for its
configuring is the same.
Table 23
Overview DCO-R (DCO-X) Programming
CMR6.DCOCOMPN CMR2.ECFAR LIM2.SCF
CMR3.CFAR(3:0) CMR4.IAR(3:0) Corner-
(CMR2.ECFAX) (CMR6.SCFX) (CMR3.CFAX(3:0)) (CMR5.IAX(4:0)) frequencies
of DCO-R
(DCO-X)
E1 / T1
X
X
0
0
0
1
0
1
X
Not used
Not used
Not used
Not used
Not used
2 Hz / 6 Hz
0.2 Hz / 0.6 Hz
7H´
´4H´
0.2 Hz / 0.6 Hz
2 Hz / 6 Hz
1
1
X
´0H´ ...´FH´ , used
as proportional
parameter
´00H´ ...´1FH´
used as integral ... 100 Hz
parameter
Range 0.2 Hz
´9H´
´8H´
´6H´
´4H´
´3H´
´2H´
´1H´
´19H´
´13H´
´12H´
´0FH´
´0CH´
´0AH
0.2 Hz
0.6 Hz
2 Hz
6 Hz
25 Hz
50 Hz
100 Hz
´08H´
After reset the corner frequencies are 2 Hz in E1 and 6 Hz in T1/J1 mode and can be switched to 0.2 Hz in E1
mode or 0.6 Hz n T1 mode by setting the register bit LIM2.SCF for the DCO-R or the register bit CMR5.SCFX for
the DCO-X respectively. A logical table builds the integral (I) and proportional (P) parameter for the PI filter of the
DCO-R or DCO-X, see Figure 29.
If the register bits CMR2.ECFAR or CMR2.ECFAX are set for the DCO-R or the DCO-X respectively, the corner
frequencies can be configured in a range between 2 Hz and 0.2 Hz using the register bits CMR3.CFAR(3:0) or
CMR3.CFAX(3:0) respectively, see CMR3, CMR4 and CMR5. A logical table builds the integral and proportional
parameter for the PI filter of the DCO-R or DCO-X out of the settings in CMR3.CFAR(3:0) or CMR3.CFAX(3:0)
respectively.
If additionally to CMR2.ECFAR or CMR2.ECFAX the bit CMR6.DCOCOMPN (CMR6) is set, which is valid for the
DCO-R and the DCO-X, the corner frequencies and attenuation factors can be programmed in a wide range using
the register bits CMR3.CFAR(3:0) and CMR4.IAR(4:0) for the DCO-R and CMR3.CFAX(3:0) and CMR5.IAX(4:0)
for the DCO-X. The settings in CMR3.CFAR(3:0)/CFAX(3:0) build the proportional parameter, the settings in
CMR4.IAR(4:0) and CMR5.IAX(4:0) build the integral parameter for the PI filters, independent from another.
Data Sheet
93
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
LIM2.SCF for DCO-R,
CMR6.SCFX for DCO-X
LIM2,
CMR6
ECFAX for DCO-X, ECFAR for DCO-R
CMR2
switches
corner
frequency to
0.2 Hz in E1
„Corner
frequency
adjust“
CFAX(for DCO-X)CFAR (for DCO-R) CMR3
CMR5
CMR4
IAX (for DCO-X) IAR (for DCO-R)
Table
Table
P
I
P
P
I
I
corner
frequency
corner
corner
frequency
range 8 …
sets corner
frequency to
2 Hz in E1
frequency
range 2 …
2 or 0.2 Hz
inE1
0.2 Hz in E1 0.2 Hz
CMR6
Reset
DCOCOMPN
MUX
P
I
MUX
P
I
DCO-R
(DCO-X)
QLIU_DCO_X_adjust_2
Figure 29 Principle of Configuring the DCO-R and DCO-X Corner Frequencies
The DCO-R reference clock is watched: If one, two or three clock periods of the 2.048 MHz (1.544 MHz in T1/J1
mode) clock at pin SYNC or RCLKI (in single rail digital line interface mode) are missing the DCO-R regulates it´s
output frequency. If four or more clock periods are missing
•
The DCO-R circuitry is automatically centered to the nominal bit rate if the center function of DCO-R is enabled
by CMR2.DCF = ´0´.
•
The actual DCO-R output frequency is “frozen” if the center function of DCO-R is disabled by CMR2.DCF = ´1´.
The receive jitter attenuator works in two different modes, selected by the multiplexer “C” in Figure 22:
•
Slave mode: In slave mode (LIM0.MAS = ´0´) the DCO-R is synchronized on the recovered route clock. In case
of loss of signal (LOS) the DCO-R switches automatically to Master mode. The frequency at the pin SYNC
must be 2.048 MHz (1.544 MHz). If bit CMR1.DCS is set automatic switching from the recovered route clock
to SYNC is disabled.
•
Master mode: In master mode (LIM0.MAS = ´1´) the DCO-R is in free running mode if no clock is supplied on
pin SYNC. If an external clock on the SYNC input is applied, the DCO-R synchronizes to this input. The
external frequency can be 2.048 MHz (1.544 MHz) for IPC.SSYF = ´0´ or 8.0 kHz for IPC.SSYF = ´1´.
The following table Table 24 shows this modes with the corresponding synchronization sources.
Data Sheet
94
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Table 24
Mode
Clocking Modes of DCO-R
Internal LOS SYNC Input System Clocks generated by DCO-R
Active
Master
Master
Independent Fixed to VDD DCO-R centered, if CMR2.DCF = ´0´. (CMR2.DCF should not be
set), see also CMR2
Independent 2.048 MHz
Synchronized to SYNC input (external 2.048 MHz or 1.544 MHz,
(E1) or
1.544 MHz
(T1)
IPC.SSYF = ´0´), see also IPC
Master
Independent 8.0 kHz
Synchronized to SYNC input (external 8.0 kHz, IPC.SSYF = ´1´,
CMR2.DCF = ´0´)
Slave
Slave
No
No
Fixed to VDD Synchronized to recovered line clock
2.048 MHz
(E1) or
Synchronized to recovered line clock
1.544 MHz
(T1)
Slave
Slave
Yes
Yes
Fixed to VDD CMR1.DCS = ´0´: DCO-R is centered, if CMR2.DCF = ´0´.
(CMR2.DCF should not be set)
CMR1.DCS = ´1´: Synchronized on recovered line clock
2.048 MHz
CMR1.DCS = ´0´: Synchronized to SYNC input
(external 2.048 MHz or 1.544 MHz)
CMR1.DCS = ´1´: Synchronized on recovered line clock
The receive clock output RCLK of every channel can be switched between 2 sources, see multiplexer “D” in
Figure 22:
•
If the DCO-R is the source of RCLK the following frequencies are possible: 1.544, 3.088, 6.176, and 12.352 in
T1/J1 mode and 2.048, 4.096, 8.192, and 16.384 MHz in E1 mode. Controlling of the frequency is done by the
register bits CMR4.RS(1:0).
•
If the recovered clock out (of the clock and data recovery) is the source of RCLK (see multiplexer “D” in
Figure 22), only 2.048 MHz (1.544 MHz) is possible as output frequency.
3.7.8.1
Receive Jitter Attenuation Performance
For E1 the jitter attenuator meets the jitter transfer requirements of the ITU-T I.431 and G.735 to 739 (refer to
Figure 30)
For T1/J1 the jitter attenuator meets the jitter transfer requirements of the PUB 62411, PUB 43802, TR-
TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431 and G.703 (refer to Figure 31).
Data Sheet
95
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
10
0
ITU G 736 Template
QuadLIU
-10
-20
-30
-40
-50
-60
1
10
100
1000
10000
100000
Jitter Frequency [Hz]
QLIU_jitt_att_E1
Figure 30 Jitter Attenuation Performance (E1)
10
0
PUB 62411 H
PUB 62411 L
QuadLIU
-10
-20
-30
-20 dB/decade
-40 dB/decade
-40
-50
-60
1
10
100
1000
10000
100000
Jitter Frequency [Hz]
QLIU_jitt_att_T1
Figure 31 Jitter Attenuation Performance (T1/J1)
Also the requirements of ETSI TBR12/13 are satisfied. Insuring adequate margin against TBR12/13 output jitter
limit with 15 UI input at 20 Hz the DCO-R circuitry starts jitter attenuation at about 2 Hz.
3.7.8.2
Jitter Tolerance (E1)
The QuadLIUTM receiver’s tolerance to input jitter complies with ITU for CEPT applications.
Figure 32 and Figure 33 shows the curves of different input jitter specifications stated below as well as the
QuadLIUTM performance.
Data Sheet
96
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
1000
100
PUB 62411
TR-NWT 000499 Cat II
CCITT G.823
ITU-T I.431
QuadLIU
10
1
0.1
1
10
100
1000
10000
100000
Jitter Frequency [Hz]
QLIU_jitt_tol_E1
Figure 32 Jitter Tolerance (E1)
1000
PUB 62411
TR-NWT 000499 Cat II
CCITT G.823
ITU-T I.431
QuadLIU
100
10
1
0.1
1
10
100
1000
10000
100000
Jitter Frequency [Hz]
QLIU_jitt_tol_E1
Figure 33 Jitter Tolerance (T1/J1)
Data Sheet
97
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
3.7.8.3
Output Jitter
In the absence of any input jitter the QuadLIUTM generates the intrinsic output jitter, which is specified in
theTable 25 below.
Table 25
Output Jitter
Specification
Measurement Filter Bandwidth
Intrinsic Output Jitter
(UI peak to peak)
Lower Cutoff
Upper Cutoff
100 kHz
100 kHz
100 kHz
8 kHz
ITU-T I.431
20 Hz
< 0.015
< 0.015
< 0.11
700 Hz
40 Hz
ETSI TBR 12
PUB 62411
10 Hz
< 0.015
< 0.015
< 0.015
< 0.02
8 Hz
40 kHz
10 Hz
40 kHz
Broadband
3.7.8.4
Output Wander
Figure 34 shows 2 curves for the output wander. For both, setting of the register bits of GCM1 to GCM8 is identical
to Table 49.
Curve 1 gives the default output wander were no additional programming of bits of registers GPC6, REGFP,
REGFD and WCON is necessary as described below. The corner frequency of the DCO-R is 2 Hz (see Table 23).
Figure 34 Output Wander
For further improvement of the output wander (curve 2), the following programming of register bits must be done:
•
•
GPC6. WAND_IMP = ´1´
WCON.WAND = ´03H´
After that, the global registers REGFP and REGFD must be written with the following sequence to improve the
output wander for both channels:
•
•
•
•
Write ´30H´ into REGFP
Write ´AAH´ into REGFD
Write ´B0H´ into REGFP
Write ´31H´ into REGFP
Data Sheet
98
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
•
•
•
•
•
•
•
•
Write ´00H´ into REGFD
Write ´B1H´ into REGFP
Write ´32H´ into REGFP
Write ´AAH´ into REGFD
Write ´B2H´ into REGFP
Write ´33H´ into REGFP
Write ´00H´ into REGFD
Write ´B3H´ into REGFP
Note that these wander configuration is reset by a receive reset (CMDR.RRES = ´1´)
Using this programming and 2 Hz for the corner frequency of the DCO-R, the output wander is given by curve 2.
3.7.9
Dual Receive Elastic Buffer
For jitter attenuation the received data is written into the receive elastic buffer with the recovered clock sourced by
the clock & data recovery and are read out with the de-jittered clock sourced by DCO-R, see Figure 22.
If the receive elastic buffer is read out directly with the recovered receive clock, no jitter attenuation is performed.
If the receive elastic buffer is read out with the receive framer clock FCLKR of the framer interface (FCLKR is
input), the receive elastic buffer performs a clock adoption from the recovered receive clock to FCLKR.
The receive elastic buffer can buffer two data streams so that dual rail mode is possible at the receive framer
interface (RDOP/RDON). In case of single rail mode on the receive framer interface, the bipolar violation signal
BPV is buffered in the same way as the single rail signal and is supported at multi function pin RDON.
The size of the elastic buffer can be configured independently for the receive and transmit direction. Programming
of the receive buffer size is done by DIC1.RBS(1:0), of the transmit buffer size by DIC1.XBS(1:0) see Table 26:
Table 26
Receive (Transmit) Elastic Buffer Modes
Framebuffer Maximum of Average delay
DIC1.RBS(1:0) (DIC1.XBS(1:0)) Mode
Slip
wander (UI = after performing Performance
size (bits)
648 ns)
190
140
100
74
a slip
256
193
128
96
00
01
10
11
10
01
E1
512
396
256
193
96
T1/J1
E1
Yes
No
T1/J1
11 (short buffer E1
mode)
38
48
T1/J1
E1
T1/J1
00
Bypass of the receive (transmit) elastic buffer
Bypass of the receive (transmit) elastic buffer
The functions are:
•
Clock adoption between framer receive clock (FCLKR input) and internally generated route clock (recovered
line clock), see Chapter 3.7.8.
•
•
Compensation of input wander and jitter.
Reporting and controlling of slips
In “one frame” or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or
46 bits. In bypass mode the time slot assigner is disabled. Slips are performed in all buffer modes except the
bypass mode. After a slip is detected the read pointer is adjusted to one half of the current buffer size.
Figure 35 gives an idea of operation of the dual receive elastic buffer: A slip condition is detected when the write
pointer (W) and the read pointer (R) of the memory are nearly coincident, i.e. the read pointer is within the slip
limits (S +, S –). If a slip condition is detected, a negative slip (one frame or one half of the current buffer size is
skipped) or a positive slip (one frame or one half of the current buffer size is read out twice) is performed at the
system interface, depending on the difference between RCLK and the current working clock of the receive
Data Sheet
99
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
backplane interface. I.e. on the position of pointer R and W within the memory. A positive/negative slip is indicated
in the interrupt status bits ISR3.RSP and ISR3.RSN.
Frame 2 Time Slots
R’
R
Slip
S-
S+
W
Frame 1 Time Slots
Moment of Slip Detection
W : Write Pointer (Route Clock controlled)
R : Read Pointer (System Clock controlled)
S+, S- : Limits for Slip Detection (mode dependent)
ITD10952
Figure 35 The Receive Elastic Buffer as Circularly Organized Memory
3.8
Additional Receiver Functions
3.8.1
Error Monitoring and Alarm Handling
The following error monitoring and alarm handling is supported by the QuadLIUTM
:
•
•
•
Loss-Of-Signal: Detection and recovery is flagged by bit LSR0.LOS and ISR2.LOS.
Transmit Line Shorted: Detection and release is flagged by bit LSR1.XLS and ISR1.XLSC
Transmit Ones-Density: Detection and release is flagged by bit LSR1.XLO and ISR1.XLSC
Table 27
Alarm
Summary of Alarm Detection and Release
Detection Condition
Clear Condition
Loss-Of-Signal
(LOS)
No transitions (logical zeros) in a
Programmable number of ones (1 to 256) in
programmable time interval of 16 to a programmable time interval of 16 to 4096
4096 consecutive pulse periods. consecutive pulse periods. A one is a signal
Programmable receive input signal with a level above the programmed
threshold
threshold.
Transmit Line Short
(XLS)
More than 3 pulse periods with
highly increased transmit line
current on XL1/2
Transmit line current limiter inactive, see
also Chapter 3.9.7
Transmit Ones-Density
(XLO)
32 consecutive zeros in the transmit Cleared with each transmitted pulse
data stream on XL1/2
Data Sheet
100
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
3.8.2
Automatic Modes
The following automatic modes are performed by the QuadLIUTM
:
•
Automatic clock source switching (see also: In slave mode (LIM0.MAS = ´0´) the DCO-R synchronizes to the
recovered route clock. In case of loss-of-signal (LOS) the DCO-R switches to Master mode automatically. If bit
CMR1.DCS is set, automatic switching from the recovered route clock to SYNC is disabled. See also Table 24.
Automatic transmit clock switching, see Chapter 3.9.3.
•
•
Automatic local and remote loop switching based on In-Band loop codes, see Chapter 3.11.2.
3.8.3
Error Counter
The QuadLIUTM offers two error counters where each of them has a length of 16 bit:
•
•
Code Violation Counter, status registers CVCL and CVCH
PRBS error counter, status registers BECL and BECH
The error counters are buffered. Buffer updating is done in two modes:
•
•
One-second accumulation
On demand by handshake with writing to the DEC register
In the one-second mode an internal/external one-second timer updates these buffers and resets the counter to
accumulate the error events in the next one-second period. The error counter cannot overflow. Error events
occurring during an error counter reset are not lost.
3.8.4
One-Second Timer
A one-second timer interrupt can be generated internally to indicate that the enabled alarm status bits or the error
counters have to be checked. The one-second timer signal is output on port SEC/FSC if configured by
GPC1.CSFP(1:0) (GPC1). Optionally synchronization to an external second timer is possible which has to be
provided on pin SEC/FSC. Selecting the external second timer is done with GCR.SES.
Data Sheet
101
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
3.9
Transmit Path
The transmit path of the QuadLIUTM is shown in Figure 36.
XL3
Pulse
XL1/XOID
Shaper,
XDIP
Dual Transmit Elastic Buffer
Encoder
DAC
LBO
XL2
XDIN
from
XL4
Transmit Line
Interface
DCO-R
internal
transmit
clock
recovered
receive clock
XCLK
MCLK
FCLKR
(in)
E
DCO-X
G
FCLKX
TCLK
F
H
%
Master
Clocking Unit
Automatic Transmit
Clock Switching
E: controlled by CMR2.IXSC and CMR2.IRSC
F: controlled by CMR1.DXSS and automatic transmit clock switching
G: controlled by LIM1.RL,JATT and LIM2.ELT
H: controlled by DIC1.XBS(1:0) and automatic transmit clock switching
%: divider: controlled by CMR6.STF(2:0)
QLIU_ITS10305
Figure 36 Transmit System of one Channel
The serial transmit bit stream (single rail or dual rail) is processed by the transmitter which has the following
functions:
•
•
AIS generation (blue alarm)
Generation of In-band loop-up/-down code
3.9.1
Transmit Line Interface
The transmit line interface includes two integrated serial resistors RTX as shown in Figure 37. Two application
modes are possible:
•
For non-generic applications the extermal serial resistance RSER is dependent on the operation mode
(E1/T1/J1) as shown in Table 28. The additional register bit PC6.TSRE is not used, RTX is always 2 Ω
For generic E1/T1/J1 applications with optimized return loss the transmit output resistance RTX is configured
by the register bit PC6.TSRE: The operation mode (E1/T1/J1) is selected by software without the need for
external hardware changes: Here the external resistor RSER is always 0 Ω, see Table 28.
•
In E1 mode the value of RSER in Table 28 is valid for both characteristic line impedances Z0 = 120 Ω and Z0 = 75 Ω.
Note that shorts between XL1 and XL2 cannot be detected, because the short circuit current is lower than 120 mA.
This way a short between XL1 and XL2 will not harm the device
The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the
appropriate programmable shape. The unipolar data is provided on pin XDI and the digital transmitter.
Data Sheet
102
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
externally
internally
XL1
XL2
RSER
RTX
Z0
RSER
RTX
QLIU_TX-interface
Figure 37 Transmit Line Interface
Table 28
Recommended Transmitter Configuration Values
PC6.TSRE
R
SER (Ohm), accuracy +/- 1 Application Mode
XL3, XL4
Operation
Mode
%
21)
2
Generic
1
Connected to
SER and
Xformer junction
E1
R
0
T1/J1
7.5
2
Non generic
0
0
Left open
E1
Left open
T1/J1
1) The values in this column refers to an ideal transformer without any parasitics. Any transformer resistance or other parasitic
resistances have to be taken into account when calculating the final value of the output serial resistors.
Similar to the receive line interface two different data types are supported:
•
Ternary Signal: Single-rail data is converted into a ternary signal which is output on pins XL1 and XL2.
Selection between B8ZS or simple AMI coding is provided.
•
Unipolar data on port XOID is transmitted in CMI code with or without (DIC3.CMI) preprocessed by B8ZS
coding or HDB3 precoding (MR3.CMI) to a fiber-optical interface. Clocking off data is done with the rising edge
of the transmit clock XCLK (1544 kHz) and with a programmable polarity. Selection is done by MR0.XC1 = ´0´
and LIM1.DRS = ´1´.
An overview of the transmit line coding is given in Table 13.
3.9.2
Transmit Clock TCLK
The transmit clock input TCLK (multi function port) of the QuadLIUTM can be configured for 1.544, 3.088, 6.176,
12.352 and 24.704 MHz input frequency in T1/J1 mode and 2.048, 4.096, 8.192, 16.384 and 32.768 MHz input
frequency in E1 mode. Frequency selection is done by the register bits CMR6.STF(2:0) (CMR6). See divider “%”
in Figure 36.
3.9.3
Automatic Transmit Clock Switching
The transmit clock output XCLK can be derived from TCLK
•
•
Directly. In this case the TCLK frequency must be 32.768 MHz in E1 or 24.704 MHz in T1/J1 mode. or
With using the DCO-X, were the DCO-X reference is TCLK.
If TCLK fails, the transmit clock output XCLK will also fail. To avoid this, a so called automatic transmit clock
switching can be enabled by setting the register bit CMR6.ATCS (CMR6). Then FCLKX will be used instead of
TCLK if TCLK is lost. The transmit elastic buffer must be active. Automatically switching between TCLK and
FCLKX is done in the following both cases:
•
If the TCLK input is used directly as source for the transmit clock XCLK, the output of the DCO-X is not used.
The DCO-X reference clock is FCLKX. If loss of TCLK is detected, the transmit clock XCLK will be switched
automatically (if CMR6.ATCS = ´1´) to the DCO-X output which is synchronous to FCLKX (see multiplexer “H”
in Figure 36). If XCLK was switched to the DCO-X output and TCLK becomes active, switching of XCLK (back)
Data Sheet
103
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
to TCLK is automatically performed if CMR6.ATCS = ´1´. All switchings of XCLK between TCLK and the DCO-
X output are shown in the interrupt status bit ISR7.XCLKSS0 which is masked by IMR7.XCLKSS0. These
kinds of switching cannot be done in general without causing phase jumps in the transmit clock XCLK.
Additionally after loss of TCLK the transmit clock XCLK is also lost during the “detection time” for loss of TCLK
and the transmit pulses are disturbed. If CMR6.ATCS is cleared, TCLK is used (again) as source for the
transmit clock XCLK, independent if TCLK is lost or not. The interrupt status bit ISR7.XCLKSS0 will be set also.
If the transmit clock XCLK is sourced by the DCO-X output and the DCO-X reference clock is TCLK, the DCO-
X reference will be switched automatically (if CMR6.ATCS = ´1´) to FCLKX (see multiplexer “F” in Figure 36)
after a loss of TCLK was detected. If the DCO-X reference was switched to FCLKX and TCLK becomes active,
switching of the reference (back) to TCLK is automatically performed if CMR6.ATCS = ´1´. All switchings of the
reference between TCLK and FCLKX are shown in the interrupt status bit ISR7.XCLKSS1 which is masked by
IMR7.XCLKSS1. For these kinds of automatically switching, the transmit clock XCLK fulfills the jitter-, wander-
and frequency deviation- requirements as specified for E1/T1 after the clock source of the DCO-X was
changed. If CMR6.ATCS is cleared, TCLK is used (again) as reference for the DCO-X, independent if TCLK
is lost or not. The interrupt status bit ISR7.XCLKSS1 will be set also.
•
The status register bits CLKSTAT.TCLKLOS and CLKSTAT.FCLKXLOS (CLKSTAT) show if the appropriate
clock is actual lost or not, so together with ISR7.XCLKSS1 and ISR7.XCLKSS0 the complete information
regarding the current status of the transmit clock system is provided.
3.9.4
Transmit Jitter Attenuator
The transmit jitter attenuator is based on the so called DCO-X (digital clock oscillator, transmit) in the transmit path.
Jitter attenuation of the transmit data is done in the transmit elastic buffer, see Figure 36. The DCO-X circuitry
generates a "jitter-free" transmit clock and meets the E1 requirements of ITU-T I.431, G. 736 to 739, G.823 and
ETSI TBR12/13 and the T1 requirements of AT&T PUB 62411, PUB 43802, TR-TSY 009,TR-TSY 253, TR-
TSY 499 and ITU-T I.431, G.703 and G. 824. The DCO-X circuitry works internally with the same high frequency
clock as the DCO-R. It synchronizes either to the working clock of the transmit system interface (internal transmit
clock) or the clock provided on multi function pin TCLK or the receive clock RCLK (remote loop/loop-timed). The
DCO-X attenuates the incoming jitter starting at its corner frequency with 20 dB per decade fall-off. With the jitter
attenuated clock, which is directly depending on the phase difference of the incoming clock and the jitter
attenuated clock, data is read from the transmit elastic buffer (512/386 bit) or from the JATT buffer (512/386 bit,
remote loop), see Figure 38. Wander with a jitter frequency below the corner frequency is passed transparently.
The dual transmit elastic buffer can buffer two data streams so that dual rail mode is possible at the transmit framer
interface (XDIP/XDIN).
The DCO-X is equivalent to the DCO-R so that the principle for its configuring is the same, see Figure 29 and
CMR3, CMR4 and CMR5.
The DCO-X reference clock is monitored: If one, two or three clock periods of the 2.048 MHz (1.544 MHz in T1/J1
mode) clock at FCLKX are missing the DCO-X regulates it´s output frequency. If four or more clock periods are
missing
•
The DCO-X circuitry is automatically centered to the nominal frequency of 2.048 MHz (1.544 MHz in T1/J1) if
the center function of DCO-X is enabled by CMR2.DCOXC = ´1´.
•
The actual DCO-X output frequency is “frozen” if the center function of DCO-R is disabled by
CMR2.DCOXC = ´0´.
The jitter attenuated clock is output on pin XCLK if the transmit jitter attenuator is enabled, see multiplexer “H” in
Figure 36.
The transmit jitter attenuator can be disabled. In that case data is read from the transmit elastic buffer with the
clock sourced on pin TCLK, see multiplexer “H” in Figure 36. Synchronization between FCLKX and TCLK has to
be done externally.
In the loop-timed clock configuration (LIM2.ELT) the DCO-X circuitry generates a transmit clock which is frequency
synchronized on RCLK, see Figure 38 and multiplexers “G” and “F” in Figure 36. In this configuration the transmit
elastic buffer has to be enabled.
Data Sheet
104
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Clock &
Data
RL1/ROID
RL2
Equalizer
Decoder
RDATA
Recovery
DPLL
Receive Line
Interface
JATT
Buffer
XL3
Pulse
Shaper,
LBO
XL1/XOID1
XL2
Encoder
XDATA
DAC
from
XL4
Transmit Line
Interface
DCO-R
recovered
receive clock
XCLK
FCLKR
E
DCO-X
G
FCLKX
F
H
TCLK
%
Master
Clocking Unit
MCLK
Automatic Transmit
Clock Switching
QLIU_remote_loop_clocking
Figure 38 Clocking and Data in Remote Loop Configuration
3.9.5
Dual Transmit Elastic Buffer
The received single rail bit stream from pin XDI or dual rail bit stream from the pins XDIP and XDIN are optionally
stored in the transmit elastic buffer, see Figure 36. The tansmit elastic buffer is organized as the receive elastic
buffer. The functions are also equal to the receive side. Programming of the dual transmit buffer size is done by
DIC1.XBS(1:0) in the same way as programming of the dual receive buffer size by DIC1.RBS(1:0), see Table 26:
The functions of the transmit buffer are:
•
Clock adoption between framer transmit clock (FCLKX) and internally generated transmit route clock, see
Chapter 3.9.4.
•
•
Compensation of input wander and jitter.
Reporting and controlling of slips
Writing of received data from XDIP/XDIN is controlled by the internal transmit clock. Selection of FCLKX or FCLKR
is possible, see multiplexer “E” in Figure 36. (If the DCO-R output is selected, the DCO_R output is also output at
FCLKR.)
Reading of stored data is controlled by the clock generated either by the DCO-X circuitry or the externally
generated TCLK. With the de-jittered clock data is read from the dual transmit elastic buffer and are forwarded to
the transmitter. Reporting and controlling of slips is done according to the receive direction. Positive/negative slips
are reported in interrupt status bits ISR4.XSP and ISR4.XSN. If the transmit buffer is bypassed data is directly
transferred to the transmitter.
3.9.6
Programmable Pulse Shaper and Line Build-Out
The transmitter includes a programmable pulse shaper to generate transmit pulse masks according to:
•
For T1: FCC68; ANSI T1. 403 1999, figure 4; ITU-T G703 11/2001, figure 10 (for different cable lengths), see
Figure 64 and Figure 40 for measurement configuration were Rload = 100 Ω
•
For E1: ITU-T G703 11/2001, figure 15 (for 0 m cable length) see Figure 63; ITU-T G703 11/2001, figure 20
(for DCIM mode), see Figure 39 for measurement configuration were Rload = 120 Ω or Rload = 75 Ω
The transmit pulse shape (UPULSE) is programmed either
Data Sheet
105
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
•
•
By the registers XMP(2:0) compatible to the QuadLIUTM, see Table 29 and Table 30, if the register bit
XPM2.XPDIS is cleared, see XPM2
Or by the registers TXP(16:1), see TXP1, if the register bit XPM2.XPDIS is set, see Table 31 and Table 32.
For more details see chapter “Operational Description”
To reduce the crosstalk on the received signals in long haul applications the QuadLIUTM offers the ability to place
a transmit attenuator (Line Build-Out, LBO) in the data path. This is used only in T1 mode. LBO attenuation is
selectable with the values 0, -7.5, -15 or -22.5 dB (register bits LIM2.LBO(2:1)). ANSI T1. 403 defines only 0 to -
15 dB.
XL1
RSER
R
U
PULSE
QuadLIU
load
XL2
QLIU_pulse_meas_temp_E1
Figure 39 Measurement Configuration for E1 Transmit Pulse Template
XL1
RSER
Cable, Z0
R
UPULSE
QuadLIU
load
XL2
0 to 200 m
(0to655ft)
QLIU_pulse_meas_temp_T1
Figure 40 Measurement Configuration for T1/J1 Transmit Pulse Template
3.9.6.1
QuadFALCTM V2.1 Compatible Programming with XPM(2:0) Registers
After reset XPM2.XPDIS is zero so that programming with XPM(2:0) is selected. The default setting after reset for
the registers XMP(2:0) generates the E1 pulse shape, see Table 30, but with an unreduced amplitude. No reset
value for T1 mode exists. So after switching into T1 mode, an explicit new programming like described in Table 29
is necessary.
If LBO attenuation is selected, the programming of XPM(2:0) will be ignored. Instead the pulse shape
programming is handled internally: The generated pulse shape before LBO filtering is the same as for T1 0 to 40 m.
The given values are optimized for transformer ratio: 1 : 2.4 and cable type AWG24 using transmitter
configurations listed in Table 28 and shown in Figure 37. The measurement configurations of Figure 39 with Rload
= 120 Ω and Figure 40 with Rload = 100 Ω are used.
Table 29
Recommended Pulse Shaper Programming for T1/J1 with Registers XPM(2:0) (Compatible to
QuadFALC V2.1 )
LBO
Range
(m)
Range
XPM0
XPM1
XPM2
(dB)
(ft)
Hexadecimal
0
0
0
0
0 to 40
0 to 133
133 to 266
266 to 399
399 to 533
D7
FA
3D
5F
22
26
37
3F
11
11
11
11
40 to 81
81 to 122
122 to 162
Data Sheet
106
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Table 29
Recommended Pulse Shaper Programming for T1/J1 with Registers XPM(2:0) (Compatible to
QuadFALC V2.1 (cont’d))
LBO
0
Range
Range
XPM0
XPM1
XPM2
162 to 200
533 to 655
3F
CB
11
7.5
15
---
---
---
Are not taken into account: pulse shape generation is
handled internally.
22.5
Table 30
RSER
Recommended Pulse Shaper Programming for E1 with Registers XPM(2:0) (Compatible to
QuadFALC V2.1)
Z0
Transmit Line
Interface Mode
XPM0
XPM1
XPM2
(Ω)
7.51)
7.5
---
(Ω)
Hexadecimal
120
Non generic
Non generic
9C
8D
7B
EF
03
03
03
BD
00
00
40
07
75
Reset values
DCIM Mode
7.5
Non generic
1) The values in this row refers to an ideal application without any parasitics. Any other parasitic resistances have to be taken
into account when calculating the final value of the output serial resistors.
3.9.6.2
Programming with TXP(16:1) Registers
By setting of register bit XPM2.XPDIS the pulse shape will be configured by the registers TXP(16:1) (TXP1). Every
of these registers define the amplitude value of one sampling point in the symbol. A symbol is formed by 16
sampling points.
The default setting after reset for the registers TXP(16:1) generates also the E1 pulse shape (0m), but with an
unreduced amplitude. (TXP(9:16) = ´00H´; TXP(1:8) = ´38H´= 56D´) No reset value for T1 mode exists. So after
switching into T1 mode, an explicit new programming like Table 31 is necessary.
The pulse shape configuration will be done also by the registers TXP(16:1) if a LBO attenuation is selected. The
pulse shape is then determined by both, the values of TXP(16:1) and the LBO filtering.
The given values in Table 31 and Table 32 are optimized for transformer ratio: 1 : 2.4; cable: AWG24 and
configurations listed in Table 28 and shown in Figure 37.
Table 31
LBO
Recommended Pulse Shaper Programming for T1 with Registers TXP(16:1)
Range Range TXP Values, Decimal
(dB) (m)
(ft)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
0
0 to 40
40 to 81
0 to 133
46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4
0
133 to 266 48 50 48 46 46 44 44 44 16 -17 -14 -14 -4 -4 -4 -4
0
81 to 122 266 to 399 48 50 46 44 44 44 44 44 16 -25 -17 -14 -4 -4 -4 -4
81 to 122 266 to 399 56 58 54 52 48 48 48 48 16 -25 -17 -14 -4 -4 -4 -4
122 to 162 399 to 533 63 63 58 56 52 52 51 51 16 -34 -32 -17 -4 -4 -4 -4
0
0
7.5
155
--
--
--
--
--
46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4
46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4
46 46 46 44 44 44 44 44 16 -17 -14 -14 -4 -4 -4 -4
22.5 --
Data Sheet
107
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Table 32
RSER
Recommended Pulse Shaper Programming for E1 with registers TXP(16:1)
Z0
Transmit TXP values, decimal
Line
Interface
Mode
(Ω)
21)
7.5
2
(Ω)
120
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Generic
42 40 40 40 40 40 40 42
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
120
75
Non generic 63 57 57 57 57 57 57 57 -4
Generic
Non generic 60 58 58 58 58 58 58 58
56 56 56 56 56 56 56 56
42 40 40 40 40 40 40 40
0
0
0
7.5
--
75
Reset values
2
DCIM
Mode
Generic
20 20 20 20 20 20 20 20 -20 -20 -20 -20 -20 -20 -20 -20
7.5
DCIM
mode
Non generic 28 28 28 28 28 28 28 28 -28 -28 -28 -28 -28 -28 -28 -28
1) The values in this row refers to an ideal application without any parasitics. Any other parasitic resistances have to be taken
into account when calculating the final value of the output serial resistors.
3.9.7
Transmit Line Monitor
The transmit line monitor (see principle in Figure 41) compares the transmit line current on XL1 and XL2 with an
on-chip transmit line current limiter. The monitor detects faults on the primary side of the transformer indicated by
a highly increased transmit line current (more than 120 mA for at least 3 consecutive pulses sourced by VDDX)
and protects the device from damage by setting the transmit line driver XL1/2 into high-impedance state
automatically (if enabled by XPM2.DAXLT = ´0´, see XPM2). The current limiter checks the actual current value
of XL1/2 and if the transmit line current drops below the detection limit the high-impedance state is cleared.
Two conditions are detected by the monitor:
•
•
Transmit line ones density (more than 31 consecutive zeros) indicated by LSR1.XLO (LSR1).
Transmit line high current indicated by LSR1.XLS.
In both cases a transmit line monitor status change interrupt is provided.
Shorts between XL1 or XL2 and VDD, VDDC or VDDP are not detected.
Note that shorts between XL1 and XL2 cannot be detected. This way a short between XL1 and XL2 will not harm
the device.
Line
Monitor
TRI
XL1
Pulse
Shaper
XL2
XDATA
ITS10936
Figure 41 Transmit Line Monitor Configuration
Data Sheet
108
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
3.10
Framer Interface
The framer interface of the QuadLIUTM is shown in Figure 42.
RDOP
Receive System
(see chapter 3.6)
Multi Function
Ports
RDOP
Dual Receive
Elastic Buffer
Receive
Framer
Interface
RDON/BPV
LOS
RDON/BPV
LOS
RP(A...C)
RCLK
RCLK
recovered
clock
internal
from
DCO-R
receive clock
J
FCLKR
FCLKX
1
FCLKX
internal
transmit
clock
K
XDIN
XDIP
XDIN
Dual Transmit
Eastic Buffer
XP(A...B)
TCLK
Transmit
Framer
XCLK
Transmit System
(see chapter 3.8.)
TCLK
Interface
Multi Function
Ports
XDIP
J: controlled by CMR2.IRSC and DIC1.RBS(1:0)
K: controlled by CMR2.IXSC
1: Input/output selection of FCLKR by PC5.CSRP
QLIU_framer_if
Figure 42 Framer Interface (shown for one channel)
Configuring of the framer interface consists on
•
•
Configuration of the interface mode (single/dual rail)
Configuration of the multi function ports, see Chapter 3.12
Selection of dual or single rail mode can be done in receive and transmit direction independent from each other.
In single rail mode of the receive direction (LIM3.DRR = ´0´, LIM3), the unipolar data is supported at RDOP and
the bipolar violation (BPV) is supported at the receive multifunction pins. Therefore one of the three receive
multifunction pins must be configured to RDON/BPV output (for example PC3.RPX3(3:0) = ´1110b´), seeTable 34,
if BPV output is used exernally.
If dual rail mode is selected in receive direction by setting of register bit LIM3.DRR, the positive rail of the data is
supported at RDOP and the negative rail of the data or is supported at the receive multi function pins. Therefore
one of the three receive multifunction pins must be configured to RDON/BPV output, seeTable 34.
Clocking of RDOP and RDON/BPV is done with the rising or falling edge of the internal receive clock, selected by
DIC3.RESR. The internal receive clock can be sourced either
•
By the receive clock RCLK of the receive system (CMR2.IRSC = ´1´, CMR2). To support the framer with these
clock FCLKR output pin function must be selected by PC5.CSRP = ´1´ (PC5). or
Data Sheet
109
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
•
By the FCLKR input pin. In that case FCLKR input pin function must be selected by PC5.CSRP = ´0´ to use
the receiver clock from the framer.
In single rail mode of the transmit direction (LIM3.DRX = ´0´, LIM3), the input for the unipolar data of the framer is
XDIP.
If dual rail mode is selected in transmit direction by setting of register bit LIM3.DRX, the input for the positive rail
of the data is XDIP and the input for the negative rail of the data is the multi function port XDIN. Therefore one of
the both transmit multifunction ports must be configured to XDIN (for example PC1.XPX1(3:0) = ´1101b´),
seeTable 34.
Clocking (sampling) of XDIP and XDIN is done with the rising or falling edge of the internal transmit clock, selected
by DIC3.RESX. The internal transmit clock can be sourced either
•
By the internal receive clock of the receive system (CMR2.IXSC = ´1´). To support the framer with these clock
FCLKR output pin function must be selected by PC5.CSRP = ´1´. or
•
By the FCLKX input pin (CMR2.IXSC = ´0´). In that case FCLKX is supported by the framer.
3.11
Test Functions
The following chapters describe the different test function of the QuadLIUTM
.
3.11.1
Pseudo-Random Binary Sequence Generation and Monitor
All bits of all slots in a E1T1/J1 frame are used for PRBS.
The QuadLIUTM has the ability to generate and monitor pseudo-random binary sequences (PRBS). The generated
PRBS pattern is transmitted to the remote end on pins XL1/2 and can be inverted optionally. Generating and
monitoring of PRBS pattern is done according to ITU-T O.150 and ITU-T O.151.
The PRBS monitor senses the PRBS pattern in the incoming data stream. Synchronization is done on the inverted
and non-inverted PRBS pattern. The current synchronization status is reported in status and interrupt status
registers. Enabled by bit LCR1.EPRM each PRBS bit error increments an error counter BEC (BECL).
Synchronization is reached within 400 ms with a probability of 99.9% at a bit error rate of up to 10-1.
The PRBS pattern (polynomials) can be selected to be 211-1, 215-1, 220-1or 223-1 by the register bits
TPC0.PRP(1:0) and LCR1.LLBP (LCR1), see Table 33. For definition of this polynomials see the Standards ITU-
T O.150, O.151. and TR62441. The polynomials 211-1 and 223-1 can be selected only if TPC0.PRM unequal
´00b´.
Transmission of PRBS pattern is enabled by register bit LCR1.XPRBS. With the register bit LCR1.FLLB switching
between not inverted and inverted transmit pattern can be done.
The receive monitoring of PRBS patterns is enabled by register bit LCR1.EPRM. In general, depending on bit
LCR1.EPRM the source of the interrupt status bit ISR1.LLBSC changed, see register description. The type of
detected PRBS pattern in the receiver is shown in the status register bits PRBSSTA.PRS. Every change of the
bits PRS in PRBSSTA sets the interrupt bit ISR1.LLBSC if register bit LCR1.EPRM is set. No pattern is also
detected if the mode “alarm simulation” is active.
The detection of all_zero or all_ones pattern is done over 12, 16, 21 or 24 consecutive bits, depending on the
selected PRBS polynomial (211-1, 215-1, 220-1or 223-1 respectively). The detection of all_zero or all_ones is
independent on LCR1.FLLB.
The distinction between all-ones and all-zeros pattern is possible by combination of.
•
The information about the first reached PRBS status after the PRBS monitor was enabled (“PRBS pattern
detected” or “inverted PRBS pattern detected”) with
•
The status information “all-zero pattern detected” or “all-ones pattern detected”
If an “all-one” or an “all-zero” pattern is detected by the PRBS monitor, the interrupt status bit ISR1.LLBSC is set
not only once, but is set permanent. To avoid that the LLBSC interrupt is issued permanent and the HOST micro
controller would permanent be occupied, the following proceeding is recommended:
After reading of the interrupt status bit ISR1.LLBSC , the appropriate interrupt routine should set the interrupt mask
bits IMR1.LLBSC to ´1´, after an “all-one” or an “all-zero” pattern was indicated, to avoid permanent interrupts
issued by the QuadLIUTM. The PRBS status register bits PRBSSTA.PRS should be polled to detect changes in
Data Sheet
110
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
the pattern, for example once per second, using the ISR3.SEC interrupt. In case PRBSSTA.PRS(2:1) is unequal
´11B´, the interrupt mask bits should be cleared to return to normal operation.
Because every bit error in the PRBS sequence increments the bit error counter BEC, no special status information
like “PRBS detected with errors” is given here.
Table 33
Supported PRBS Polynomials
TPC0.PRP(1:0)
TPC0.PRM
01 or 11
01 or 11
01 or 11
01 or 11
00
LCR1.LLBP
Kind of Polynomial Comment
00
01
10
11
XX
XX
X
X
X
X
0
211 -1
215 -1
220 -1
2
23 -1
215 -1
220 -1
SW compatible to
QuadLIU
00
1
3.11.2
In-Band Loop Generation, Detection and Loop Switching
Detection and generation of In-band Loop code is supported by the QuadLIUTM on the line side and on the framer
side independent from another. On the framer side it is only supported in single rail mode.
The QuadLIUTM generates and detects unframed In-band codes where the complete data stream is used by the
In-band signaling information.The so called loop-up code (for loop activation) and loop-down code (for loop
deactivation) are recognized.
The maximum allowed bit error rate within the loop codes can be up to 10-2 for proper detection of the loop codes.
One “In-band loop sequence” consists of a bit sequence of 51200 consecutive bits. The In-band loop code
detection is based on the examination of such “In-band loop sequences”.
The following In-band loop code functionality is performed by the QuadLIUTM
:
•
The necessary reception time of In-band loop codes until an automatic loop switching is performed is
configured for the system side by the register bits INBLDTR.INBLDT(1:0) (INBLDTR). Configuring for the line
side is done by INBLDTR.INBLDR(1:0). If for example INBLDTR.INBLDR(1:0) = ´00b´ a time of 16 “In-band
loop sequences” (16 x 51200 bits) is selected for the line side.
•
The interrupt status register bits ISR6.(3:0) reflects the type of detected In-band loop code. Masking can be
done by IMR6(3:0). The status bits are set after one “In-band loop sequence” is detected (no dependency on
INBLDTR).
•
•
Transmission of In-Band loop codes is enabled by programming MR3.XLD/XLU in E1 mode or MR5.XLD/XLU
in T1/J1 mode. Transmission of codes is done by the QuadLIUTM lasting for at least 5 seconds.
The QuadLIUTM also offers the ability to generate and detect flexible In-band loop-up and loop-down patterns
(LCR1.LLBP = ´1´) (LCR1). Programming of these patterns is done in registers LCR2 and LCR3 (LCR2). The
pattern length is individually programmable in length from 2 to 8 bits by LCR1.LAC(1:0) and LCR1.LDC(1:0).
A shorter pattern can be inplemented by configuring a repeating pattern in the LCR2 and LCR3.
Automatic loop switching (activation and deactivation, for remote loop, see Chapter 3.11.3 and local loop, see
Chapter 3.11.4) based on In-band Loop codes can be done. Two kinds of line loop back (LLB) codes are
defined in ANSI-T1.403, 1999 in chapter 9.4.1.1 and 9.4.1.2. respectively. Automatic loop switching must be
enabled through configuration register bits ALS.SILS for the In-Band Loop codes coming from the system side
and ALS.LILS for the In-Band Loop codes coming from the line side respectively. Masking of ISR6.(3:0) for
interrupt can be done by register bits IMR6.(3:0). The interrupt status register bits ISR6.(3:0) (ISR6) will be set
to ´1´ if an appropriate In-Band code were detected, independent if automatic loop switching is enabled.
(Because the controller knows if automatic loop switching is enabled, it knows if a loop is activated or not.)
Code detection status only for the line side is displayed in E1 mode in status register bits LSR2.LLBDD /
LLBAD and in T1/J1 mode in LSR1.LLBDD / LLBAD.
•
Only unframed In-Band loop code can be generated and detected.
Automatic loop switching is logically OR´d with the appropriate loop switching by register bits.
Data Sheet
111
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
If a remote loop is activated by an automatic loop switching the register bit LIM0.JATT controls also if the jitter
attenuator is active or not, see also Figure 38.
If ALS.LILS is set (ALS), the remote loop is activated after an activation In-Band loop code (see ANSI T1 404,
chapter 9.4.1.1.) was detected from the line side and if the local loop is not activated by LIM0.LL = ´1´. The remote
loop is deactivated after a deactivation In-Band loop code (see ANSI T1 404, chapter 9.4.1.2.) was detected from
the line side. (But if the remote loop is additionally activated by LIM0.RL = ´1´ the remote loop is still active,
because automatic loop switching is logically OR´d with the appropriate loop switching by register bits.).
If ALS.SILS is set, the local loop is activated after an activation In-Band loop code (see ANSI T1 404, chapter
9.4.1.1.) was detected from the system side. The local loop is deactivated after a deactivation In-Band loop code
(see ANSI T1 404, chapter 9.4.1.2.) was detected from the system side. (But if the local loop is additionally
activated by LIM0.LL = ´1´ the local loop is still active, because automatic loop switching is logically OR´d with the
appropriate loop switching by register bits.).
ALS.SILS and ALS.LILS both must not be set to ´1´ simultaneous.
If ALS.SILS or ALS.LILS are set after an In-Band loop code was detected, no automatic loop switching is
performed.
If ALS.LILS is cleared, an automatic activated remote loop is deactivated.
If ALS.SILS is cleared, an automatic activated local loop is deactivated.
The kind of detected In-Band loop codes is shown in the interrupt status register bits ISR6.(3:0).
To avoid deadlocks in the QuadLIUTM an activation of the remote loop is not possible by In-band loop codes if the
local loop (see Chapter 3.11.4) is closed (LIM0.LL is set).
3.11.3
Remote Loop
In the remote loop-back mode the clock and data recovered from the line inputs RL1/2 or ROID are routed back
to the line outputs XL1/2 or XOID through the analog or digital transmitter, see Figure 43 and Figure 38. As in
normal mode they are also sent to the framer interface. The remote loop-back mode is activated by
•
•
Control bit LIM1.RL or
After detection of the appropriate In-band loop code, if enabled by ALS.LILS and if LIM0.LL = ´0´ (LIM0) (to
avoid deadlocks), see Chapter 3.11.2.
Received data can be looped with or without the jitter attenuator (JATT buffer) dependent on LIM1.JATT (LIM1).
Clock &
RL1/ROID
Data
Recovery
DPLL
Equalizer
Decoder
RDATA
RL2
Receive Line
Interface
JATT
clocking
Buffer
Pulse
XL1/XOID
XL2
Shaper,
LBO
Encoder
XDATA
DAC
Transmit Line
Interface
QLIU_remote_loop
Figure 43 Remote Loop
Data Sheet
112
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
3.11.4
Local Loop
The local loop-back is activated by
•
•
The control bit LIM0.LL (LIM0).
After detection of the appropriate In-band loop code, if enabled by ALS.SILS, see Chapter 3.11.2.
The local loop-back mode disconnects the receive lines RL1/2 or ROID from the receiver. Instead of the signals
coming from the line the data provided by the framer interface is routed through the analog receiver back to the
framer interface. However, the bit stream is transmitted undisturbed on the line at XL1/2. However, an AIS to the
distant end can be enabled by setting MR1.XAIS = ´1´ without influencing the data looped back to the framer
interface.
The signal codes for transmitter and receiver have to be identical.
RDOP
Clock &
RL1/ROID
RL2
Data
Dual Receive Elastic Buffer
Equalizer
Decoder
RDON
Recovery
DPLL
internal
Receive Line
Interface
J
receive clock
Local Loop
RCLK
D
A
DCO-R
C
XL3
Pulse
Shaper,
LBO
XL1
XL2
XDIP
XDIN
Dual Transmit Elastic Buffer
Encoder
DAC
XL4
Transmit Line
Interface
internal
transmit
clock
recovered
receive clock
E
DCO-X
G
FCLKX
TCLK
F
H
%
QLIU_local_loop
Figure 44 Local Loop
3.11.5
Payload Loop-Back
The payload loop-back is activated by setting MR2.PLB (MR2).
During activated payload loop-back the data stream is looped from the receiver section back to transmitter section.
The looped data passes the complete receiver including the wander and jitter compensation in the receive elastic
buffer and is output on pin RDO. Instead of the data an AIS signal (MR2.SAIS) can be sent to the framer interface.
If the PLB is enabled the transmitter and the data on pins XL1/2 or XDOP/XDON are clocked with FCLKR instead
of FCLKX. All the received data is processed normally.
Data Sheet
113
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
RDOP
Clock &
Data
Dual Receive Elastic Buffer
Equalizer
Decoder
RDON
RL1/ROID
RL2
Recovery
DPLL
FCLKR
internal
receive
clock
Receive Line
Interface
J
RCLK
D
A
DCO-R
C
Payload Loop
XL3
Pulse
XL1
XL2
XDIP
Shaper,
LBO
Dual Transmit Elastic Buffer
Encoder
DAC
XDIN
XL4
Transmit Line
Interface
internal
transmit
clock
recovered
receive clock
E
DCO-X
G
FCLKX
TCLK
F
H
%
QLIU_payload_loop
Figure 45 Payload Loop
3.11.6
Alarm Simulation
Alarm simulation does not affect the normal operation of the device. However, possible real alarm conditions are
not reported to the micro controller or to the remote end when the device is in the alarm simulation mode.
The alarm simulation and setting of the appropriate status bists is initiated by setting the bit MR0.SIM. For details
(differences between E1 and T1/J1 mode) see description in MR0. The following alarms are simulated:
•
•
•
Loss-Of-Signal (LOS)
Alarm Indication Signal (AIS)
Code violation counter (HDB3 Code)
Error counting and indication occurs while this bit is set. After it is reset all simulated error conditions disappear,
but the generated interrupt statuses are still pending until the corresponding interrupt status register is read.
Alarms like AIS and LOS are cleared automatically. Interrupt status registers and error counters are automatically
cleared on read.
3.12
Multi Function Ports
Several signals are available on the multi function ports, see Table 34 and PC1. After reset, no function is selected
(´0000b´).
Four multi function ports (MFP) for RX - so called as RPA, RPB, RPC, RPC - and four MFPs for TX - XPA to XPD
- are implemented for every channel. The port levels are reflected in the appropriate bits of the register MFPI, see
MFPID
The functions of RPA, RPB, RPC and RPC are configured by PC1.RPC1(3:0) , PC2.RPC2(3:0), PC3.RPC2(3:0)
and PC4.RPC3(3:0) respectively. The functions of XPA to XPD are configured by PC1.XPC1(3:0) to
PC4.XPC2(3:0) respectively.
The actual logical state of the 8 multifunction ports can be read out using the register MFPI. This function together
with static output signal options in Table 34 offers general purpose I/O functionality on unused multi function port
pins.
If a port is configured as GPOH or GPOL the port level is set fix to high or low-level respectively.
Data Sheet
114
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Functional Description
Each of the input functions may only be selected once in a channel except for the GPI functionality. No input
function must be selected twice or more.
Table 34
Multi Function Port Selection
Selection
RFP Signal Available RFP Function
on port
XFP Signal Available XFP Function
on port
0000
0001
0010
0011
0100
0101
0110
0111
1000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RLT
Reserved
Reserved
Reserved
Reserved
Reserved
TCLK
Reserved
Reserved
Reserved
Reserved
Reserved
A, B, C, D Transmit clock input
Reserved
Reserved
Reserved
Reserved
Reserved
XCLK
Reserved
Reserved
Reserved
Reserved
Reserved
A, B, C, D Transmit clock output
A, B, C, D Receive line
XLT
A, B, C, D Transmit line tristate
control, high active
termination; logically
OR´d with
LIM0.RTRS
1001
1010
1011
1100
1101
GPI
A, B, C, D General purpose
input
GPI
A, B, C, D General purpose
input
GPOH
GPOL
LOS
A, B, C, D General purpose
output high
GPOH
GPOL
Reserved
XDIN
A, B, C, D General purpose
output high
A, B, C, D General purpose
output low
A, B, C, D General purpose
output low
A, B, C, D Loss of signal
indication output
A, B, C, D Reserved
RTDMT
A, B, C, D Receive framer
interface tristate for
pins RDOP and
A, B, C, D Transmit data
negative input
RCLK; logically OR´d
with DIC3.RRTRI
1110
1111
RDON
RCLK
A, B, C, D Receive data
negative output or
bipolar violation
output
XLT
A, B, C, D Transmit line tristate
control, low active
A, B, C, D RCLK output
Reserved
Reserved
Data Sheet
115
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
4
Register Description
To maintain easy readability this chapter is divided into separate control register and status register sections.
The higher address part of all global registers is ´00H´, that of the port (channel) specific ones include the channel
number 0 to 3 and is marked in the following tables with ´xxH´. So ´xxH´ has the values ´00H´ up to ´03H´.
Note:“RES” in the register schematics means reserved, not reset. If these bits are written then the value must be
´0´.
Note:In all bit fields used in the register schematics and also in the table descriptions the most significant bit is the
left one and the least significant bit is the right one. Sometimes in the text a bit field with the name
“bitfieldname” is denoted as <bitfieldname>(MSB:LSB). For example: In register GPC2 the bit field FSS
consists on MDS(2:0).
4.1
Detailed Control Register Description
Table 35
Registers Overview
Register Short Name
IPC
GCR
GPC1
GPC2
GCM1
GCM2
GCM3
GCM4
GCM5
GCM6
GCM7
GCM8
GIMR
Register Long Name
Offset Address Page Number
Interrupt Port Configuration
Global Configuration Register
Global Port Configuration 1
Global Port Configuration Register 2
Global Clock Mode Register 1
Global Clock Mode Register 2
Global Clock Mode Register 3
Global Clock Mode Register 4
Global Clock Mode Register 5
Global Clock Mode Register 6
Global Clock Mode Register 7
Global Clock Mode Register 7
Global Interrupt Mask Register
Register Field Pointer
0008H
0046H
0085H
008AH
0092H
0093H
0094H
0095H
0096H
0097H
0098H
0099H
00A7H
00BBH
00BCH
00D3H
00D4H
00D5H
00D6H
00D7H
xx02H
xx15H
xx16H
xx17H
xx18H
xx1AH
121
158
164
166
167
168
170
171
172
173
175
176
177
179
180
183
184
185
186
187
120
122
122
122
122
122
REGFP
REGFD
GPC3
GPC4
GPC5
Register Field Data
Global Port Configuration Register 3
Global Port Configuration Register 4
Global Port Configuration Register 5
Global Port Configuration Register 6
In-Band Loop Detection Time Register
Command Register
Interrupt Mask Register 1
Interrupt Mask Register 2
Interrupt Mask Register 3
Interrupt Mask Register 4
GPC6
INBLDTR
CMDR
IMR1
IMR2
IMR3
IMR4
IMR6
Interrupt Mask Register 6
Data Sheet
116
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
Table 35
Registers Overview (cont’d)
Register Short Name
MR0
MR1
MR2
LOOP
MR4
Register Long Name
Mode Register 0
Mode Register 1
Mode Register 2
Loop-Back Register
Mode Register 4
Framer Mode Register 5
Receive Control 0
Transmit Pulse Mask0
Transmit Pulse Mask1
Transmit Pulse Mask2
Clear Channel Register 1
Clear Channel Register 2
Mode Register 3
Clear Channel Register 3
Line Interface Mode 0
Line Interface Mode 1
Pulse Count Detection Register
Pulse Count Recovery
Line Interface Mode 2
Loop Code Register 1
Loop Code Register 2
Loop Code Register 3
Digital Interface Control 1
Digital Interface Control 2
Digital Interface Control 3
Clock Mode Register 4
Clock Mode Register 5
Clock Mode Register 6
Clock Mode Register 1
Clock Mode Register 2
Clock Mode Register 3
Port Configuration 1
Offset Address Page Number
xx1CH
xx1DH
xx1EH
xx1FH
xx20H
xx21H
xx24H
xx26H
xx27H
xx28H
xx2FH
xx30H
xx31H
xx31H
xx36H
xx37H
xx38H
xx39H
xx3AH
xx3BH
xx3CH
xx3DH
xx3EH
xx3FH
xx40H
xx41H
xx42H
xx43H
xx44H
xx45H
xx48H
xx80H
xx81H
xx82H
xx83H
xx84H
xx86H
xxA8H
xxBDH
xxC1H
xxC2H
124
126
127
128
129
130
131
132
133
134
135
135
136
135
137
139
140
141
142
143
145
146
147
148
149
151
152
153
155
156
159
160
162
162
162
163
165
178
181
182
182
MR5
RC0
XPM0
XPM1
XPM2
CCB1
CCB2
MR3
CCB3
LIM0
LIM1
PCD
PCR
LIM2
LCR1
LCR2
LCR3
DIC1
DIC2
DIC3
CMR4
CMR5
CMR6
CMR1
CMR2
CMR3
PC1
PC2
PC3
PC4
PC5
PC6
TPC0
BFR
TXP1
TXP2
Port Configuration Register 2
Port Configuration Register 3
Port Configuration Register 4
Port Configuration 5
Port Configuration 6
Test Pattern Control Register 0
Bugfix Register
TX Pulse Template Register 1
TX Pulse Template Register 2
Data Sheet
117
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
Table 35
Registers Overview (cont’d)
Register Short Name
TXP3
TXP4
TXP5
TXP6
TXP7
TXP8
TXP9
TXP10
TXP11
TXP12
TXP13
TXP14
TXP15
TXP16
ALS
Register Long Name
Offset Address Page Number
TX Pulse Template Register 3
TX Pulse Template Register 4
TX Pulse Template Register 5
TX Pulse Template Register 6
TX Pulse Template Register 7
TX Pulse Template Register 8
TX Pulse Template Register 9
TX Pulse Template Register 10
TX Pulse Template Register 11
TX Pulse Template Register 12
TX Pulse Template Register 13
TX Pulse Template Register 14
TX Pulse Template Register 15
TX Pulse Template Register 16
Automatic Loop Switching Register
Interrupt Mask Register 7
xxC3H
xxC4H
xxC5H
xxC6H
xxC7H
xxC8H
xxC9H
xxCAH
xxCBH
xxCCH
xxCDH
xxCEH
xxCFH
xxD0H
xxD9H
xxDFH
xxE2H
xxE8H
182
182
182
182
182
182
182
182
182
182
182
182
182
182
188
122
189
190
IMR7
LIM3
WCON
LIU Mode Register 3
Wander Configuration Register
The register is addressed wordwise.
Data Sheet
118
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
Table 36
Mode
Basic Access Types
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
Register is read and writable by SW
read/write
rw
Register is used as input for the HW
read/write
virtual
rwv
Physically, there is no new register in Register is read and writable by SW (same
the generated register file. The real
readable and writable register resides
in the attached hardware.
as rw type register)
read
r
Register is written by HW (register
Value written by SW is ignored by HW; that
between input and output -> one cycle is, SW may write any value to this field
delay)
Same as r type register
Physically, there is no new register in Value written by SW is ignored by HW; that
without affecting HW behavior
Same as r type register
read only
read virtual
ro
rv
the generated register file. The real
readable register resides in the
attached hardware.
is, SW may write any value to this field
without affecting HW behavior (same as r
type register)
write
w
Register is written by software and
affects hardware behavior with every
write by software.
Register is writable by SW. When read, the
register does not return the value that has
been written previously, but some constant
value instead.
write virtual
wv
rwh
Physically, there is no new register in Register is writable by SW (same as w type
the generated register file. The real
writable register resides in the attached
hardware.
register)
read/write
hardware
affected
Register can be modified by hardware Register can be modified by HW and SW,
and software at the same time. A but the priority SW versus HW has to be
priority scheme decides, how the value specified.
changes with simultaneous writes by
hardware and software.
SW can read the register.
Special Access Types
Latch high,
self clearing
lhsc
Latch high signal at high level, clear on SW can read the register
read
Latch low,
self clearing
llsc
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
lhmk
llmk
ihsc
ilsc
Latch high signal at high level, register SW can read the register, with write mask
mask clearing
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Latch high signal at low-level, register SW can read the register, with write mask
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
the register can be cleared (1 clears)
SW can read the register
Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
Interrupt low,
mask clearing
ihmk
ilmk
Differentiate the input signal (high-
SW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Data Sheet
119
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionCommand Register
Table 36
Mode
Registers Access Types (cont’d)
Symbol Description Hardware (HW)
Description Software (SW)
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset lor
rw register, value is latched after first
clock cycle after reset
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the HW,
Writing to the register generates a strobe
the register will be cleared due to a HW signal for the HW (1 pdi clock cycle)
mechanism.
Register is read and writable by SW.
4.1.1
Control Registers
Command Register
CMDR
Command Register
Offset
xx02H
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
;5(6
Z
ꢄ
ꢅ
ꢆ
ꢇ
5HV
55(6
5HV
5HV
Z
Field
Bits
Type
Description
RRES
6
w
Receiver Reset
The receive line interface except the clock and data recovery unit (DPLL)
is reset. However the contents of the control registers is not deleted.
A receiver reset should be made after switching from power down to
power up (GCR.PD = ´1´ -> ´0´).
XRES
4
w
Transmitter Reset
The transmit framer and transmit line interface excluding the system
clock generator and the pulse shaper are reset. However the contents of
the control registers is not deleted.
Data Sheet
120
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Port Configuration
Interrupt Port Configuration
See Chapter 3.5.3 and Table 10.
Note:Unused bits have to be cleared.
IPC
Offset
0008H
Reset Value
00H
Interrupt Port Configuration
ꢀ
9,63//
UZ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
66<)
UZ
,&
UZ
Field
Bits
Type
Description
VISPLL
7
rw
Masked PLL Interrupts Visible
See also Chapter 3.5.3
0B
1B
Masked interrupt status bits PLLLC and PLLIC are not visible in
register GIS2.
Masked interrupt status bits PLLLC and PLLIC are visible in GIS2,
but they are not visible in registers GIS.
SSYF
IC
2
rw
rw
Select SYNC Frequency
Only applicable in master mode (LIM0.MAS = ´1´) and bit CMR2.DCF is
cleared, see also Table 9.
0B
1B
Reference clock on port SYNC is 2.048 MHz
Reference clock on port SYNC is 8 kHz
1:0
Interrupt Port Configuration
These bits define the function of the interrupt output pin INT.
X0B Open drain output
01B Push/pull output, active low
11B Push/pull output, active high
Data Sheet
121
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Mask Register 1
Interrupt Mask Register 1
Each interrupt source can generate an interrupt signal on port INT (characteristics of the output stage are defined
by register IPC). A “1” in a bit position of IMR(1:4), IMR(6:7) sets the mask active for the interrupt status in ISR(1:4),
ISR(6:7). Masked interrupt statuses neither generate a signal on INT, nor are they visible in register GIS.
Moreover, they are- not displayed in the interrupt status register if bit GCR.VIS is cleared- displayed in the interrupt
status register if bit GCR.VIS is set, see Chapter 3.5.3.
Note:After reset, all interrupts are disabled.
IMR1
Offset
xx15H
Reset Value
FFH
Interrupt Mask Register 1
ꢀ
//%6&
UZ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
;/6&
UZ
5HV
Field
LLBSC
Bits
7
Type
rw
Description
Interrupt Mask Bit LLBSC
Each interrupt source can generate an interrupt signal on port INT.
Characteristics of the output stage are defined by register IPC. A ´1´ in a
bit position of IMR(7:0) sets the mask active for the interrupt status in the
registers ISR. Mask interrupt statuses neither generate a signal on INT,
not are they visible in register GIS. Moreover they are not displayed in the
interrupt status register if bit GCR.VIS is cleared; they are displayed in the
interrupt status register if bit GCR.VIS is set.
The bit IMR1.LLBSC is only valid in E1 mode. For T1/J1 mode the
equivalent bit is in IMR3.LLBSC.
XLSC
1
rw
Interrupt Mask Bit XLSC
The other Interrupt Mask Registers have the same description.
The Offset Addresses are listed in IMRn Overview, for bit names and layout refer to Interrupt Mask Registers.
Table 37
IMRn Overview
Register Short Name
Register Long Name
Offset Address Page Number
IMR2
IMR3
IMR4
IMR6
IMR7
Interrupt Mask Register 2
Interrupt Mask Register 3
Interrupt Mask Register 4
Interrupt Mask Register 6
Interrupt Mask Register 7
xx16H
xx17H
xx18H
xx1AH
xxDFH
Table 38
bit number
IMR1
Interrupt Mask Registers
7
6
5
4
3
2
1
0
LLBSC
(E1 only)
XLSC
Data Sheet
122
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
Table 38
IMR2
IMR3
Interrupt Mask Registers (cont’d)
AIS
LOS
LTC
SEC
LLBSC
(T1/J1
only)
RSN
RSP
IMR4
IMR6
IMR7
XSP
XSN
LILSU
LILSD
XCLKSS1 XCLKSS0
Data Sheet
123
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMode Register 0
Mode Register 0
MR0
Mode Register 0
Offset
xx1CH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
;&
UZ
5&
(;=(
UZ
$/0
UZ
5HV
6,0
UZ
UZ
Field
XC
Bits
Type
Description
Transmit Code
Serial line code for the transmitter, independent of the receiver.
After changing XC(1:0), a transmitter software reset is required
(CMDR.XRES = 1). See Chapter 3.9.1.
00B reserved
01B CMI (1T2B+HDB3), (optical interface)
10B AMI (ternary or digital dual-rail interface)
11B HDB3 Code in E1 or B8ZS code in T1/J1 mode (ternary or digital
dual-rail interface)
Receive Code
Serial line code for the receiver, independent of the transmitter.
After changing RC(1:0), a receiver software reset is required
(CMDR.RRES = ´1´). See Chapter 3.7.2.
00B reserved
01B CMI (1T2B+HDB3), (optical interface)
10B AMI (ternary or digital dual-rail interface)
11B HDB3 Code in E1 or B8ZS code in T1/J1 mode (ternary or digital
dual-rail interface)
7:6
5:4
3
rw
rw
rw
RC
EXZE
Extended HDB3 Error Detection, E1 only
Selects error detection mode in E1 mode. In T1/J1 mode this bit is
reserved.
0B
1B
Only double violations are detected.
Extended code violation detection: 0000 strings are detected
additionally. Incrementing of the code violation counter CVC is
done after receiving four zeros. Errors are indicated by LSR1.EXZD
= ´1´.
Data Sheet
124
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMode Register 0
Field
Bits
Type
Description
ALM
2
rw
Alarm Mode, E1 only
Selects the AIS alarm detection mode in E1 mode. In T1/J1 mode this bit
is reserved.
0B
The AIS alarm is detected according to ETS300233. Detection: An
AIS alarm is detected if the incoming data stream contains less than
3 zeros within a period of 512 bits and a loss of frame alignment is
indicated. Recovery: The alarm is cleared if 3 or more zeros within
512 bits are detected or the FAS word is found.
1B
The AIS alarm is detected according to ITU-T G.775 Detection: An
AIS alarm is detected if the incoming data stream contains less than
3 zeros in each doubleframe period of two consecutive
doubleframe periods (1024 bits). Recovery: The alarm is cleared if
3 or more zeros are detected within two consecutive doubleframe
periods.
SIM
0
rw
Alarm Simulation, in E1 mode
SIM has to be held stable at high or low level for at least one receive clock
period before changing it again.
0B
1B
Normal operation.
Initiates internal error simulation of AIS, loss-of-signal and code
violations.
Alarm Simulation, in T1/J1 mode
Setting/resetting of SIM initiates internal error simulation of AIS (blue
alarm), loss-of-signal (red alarm) and code violations. The error counter
CVC is incremented.The selection of simulated alarms is done by the
error simulation counter: LSR2.ESC(2:0) which is incremented with each
setting of bit SIM. For complete checking of the alarm indications eight
simulation steps are necessary (LSR2.ESC(2:0) = ´0´ after a complete
simulation).
SIM has to be held stable at high or low level for at least one receive clock
period before changing it again.
Data Sheet
125
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMode Register 1
Mode Register 1
MR1
Mode Register 1
Offset
xx1DH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
302'
UZ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
5HV
;$,6
UZ
Field
PMOD
Bits
4
Type
rw
Description
PCM Mode
This bit decides between E1 and T1/J1 mode. Switching from E1 to T1 or
vice versa the device needs up to 20 µs to settle up to the internal
clocking.
0B
1B
PCM 30 or E1 mode.
PCM 24 or T1/J1 mode .
XAIS
0
rw
Transmit AIS Towards Remote End
Sends AIS on ports XL1, XL2, XOID towards the remote end. The
outgoing data stream which can be looped back through the local loop to
the system interface is not affected.
Data Sheet
126
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMode Register 2
Mode Register 2
MR2
Mode Register 2
Offset
xx1EH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
570
UZ
'$,6
UZ
5HV
3/%
UZ
5HV
Field
Bits
Type
Description
RTM
5
rw
Receive Transparent Mode, E1 only
For E1 mode this bit must be set to ´1´ for proper operation.
0B
1B
reserved
DAIS
PLB
4
rw
Disable AIS to Framer Interface
This bit must be set to ´1´ for proper operation.
0B
1B
AIS is automatically inserted into the data stream to RDO if
QuadLIUTM is in asynchronous state.
Automatic AIS insertion is disabled. Furthermore, AIS insertion can
be initiated by programming bit MR2.SAIS.
2
rw
Payload Loop-Back
See Chapter 3.11.5.
0B
1B
Normal operation. Payload loop is disabled.
The payload loop-back loops the data stream from the receiver
section back to transmitter section. Looped data is output on pin
RDO. Data received on port XDI, XSIG, SYPX and XMFS is
ignored.
Data Sheet
127
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLoop-Back Register
Loop-Back Register
LOOP
Loop-Back Register
Offset
xx1FH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
570
UZ
5HV
Field
RTM
Bits
6
Type
rw
Description
Receive Transparent Mode, T1 only
For T1/J1 mode this bit must be set to ´1´ for proper operation.
0B
1B
reserved
Data Sheet
128
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMode Register 4
Mode Register 4
MR4
Mode Register 4
Offset
xx20H
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
70
UZ
5HV
Field
TM
Bits
6
Type
rw
Description
Transparent Mode, T1 only
For T1/J1 mode this bit must be set to ´1´ for proper operation.
0B
1B
reserved
Data Sheet
129
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMode Register 5
Mode Register 5
MR5
Offset
xx21H
Reset Value
00H
Framer Mode Register 5
ꢀ
ꢁ
ꢂ
;/'B77ꢀ
UZ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
;/8
UZ
5HV
;70
UZ
5HV
Field
XLD_TT0
Bits
Type
rw
Description
5
4
2
XLD, Transmit Line Loop-Back (LLB) Down Code, T1/J1 only
The equivalent bit in E1 mode is MR3.XLD.
0B
1B
Normal operation.
A one in this bit position causes the transmitter to replace normal
transmit data with the LLB down (deactivate) Code continuously
until this bit is reset. The LLB down code is overwritten by the
framing/DL/CRC bits optionally.
TT0, Transmit Transparent Mode, E1 only
For proper operation this bit must be set to ´1´ in E1 mode.
XLU
rw
rw
Transmit LLB Up Code, T1/J1 only
This bit is not valid in E1 mode. The equivalent bit in E1 mode is
MR3.XLU.
0B
1B
Normal operation.
A one in this bit position causes the transmitter to replace normal
transmit data with the LLB up (activate) code continuously until this
bit is reset. The LLB up code is optionally overwritten by the
framing/DL/CRC bits. For proper operation bit MR5.XLD must be
cleared.
XTM
Transmit Transparent Mode
For proper operation this bit must be set to ´1´.
Data Sheet
130
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionReceive Control 0
Receive Control 0
RC0
Offset
xx24H
Reset Value
00H
Receive Control 0
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
5',6
UZ
5HV
Field
RDIS
Bits
3
Type
rw
Description
Receive Data Input Sense
Configures the input polarity of the digital receive inputs.
0B
1B
in dual rail mode RDI, RDIN are active low, in DCIM mode ROID is
active high.
in dual rail mode RDI, RDIN are active high, in DCIM mode ROID
is active low.
Data Sheet
131
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionTransmit Pulse Mask 0
Transmit Pulse Mask 0
See Chapter 3.9.6.1 and Chapter 3.9.6.2. The transmit pulse shape which is defined in ITU-T G.703 is output on
pins XL1 and XL2. The level of the pulse shape can be programmed by registers XPM(2:0) if XPM2.XPDIS is set
to ´0´ to create a custom waveform. If XPM2.XPDIS is set to ´1´, the custom waveform can be programed by the
registers TXP(16:1) and the register bits of XPM(2:0) are unused with exception of the bits XPM2.XLT,
XPM2.DAXLT and XPM2.XPDIS. In order to get an optimized pulse shape for the external transformers each
pulse shape is internally divided into four sub pulse shapes if XPM2.XPDIS is set to ´0´. In each sub pulse shape
a programmed 5-bit value defines the level of the analog voltage on pins XL1/2. Together four 5-bit values have
to be programmed to form one complete transmit pulse shape. The four 5-bit values are sent in the following
sequence:
XP04 to 00: First pulse shape level
XP14 to 10: Second pulse shape level
XP24 to 20: Third pulse shape level
XP34 to 30: Fourth pulse shape level
Changing the LSB of each subpulse in registers XPM(2:0) changes the amplitude of the differential voltage on
XL1/2 by approximately 80 mV. Recommended values for standard applications are given in Table 22 and
Table 23.
Note that in the special cases were the LBO pulse masks are performed in T1 mode, the programming of the pulse
masks is done internally, independent on the settings in XPM(2:0).
XPM0
Transmit Pulse Mask0
Offset
xx26H
Reset Value
7BH
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
;3ꢀꢁ
UZ
;3ꢀꢀ
UZ
;3ꢀꢂ
UZ
;3ꢂꢃ
UZ
;3ꢂꢄ
UZ
;3ꢂꢁ
UZ
;3ꢂꢀ
UZ
;3ꢂꢂ
UZ
Field
Bits
Type
Description
XP12
XP11
XP10
XP04
XP03
XP02
XP01
XP00
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
Bit 2 of second pulse shape level
Bit 1 of second pulse shape level
Bit 0 (LSB) of second pulse shape level
Bit 4 (MSB) of first pulse shape level
Bit 3 of first pulse shape level
Bit 2 of first pulse shape level
Bit 1 of first pulse shape level
Bit 0 (LSB) of first pulse shape level
Data Sheet
132
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionTransmit Pulse Mask 1
Transmit Pulse Mask 1
For description see Transmit Pulse Mask 0
XPM1
Transmit Pulse Mask1
Offset
xx27H
Reset Value
03H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
;3ꢀꢁ
UZ
;3ꢂꢃ
UZ
;3ꢂꢀ
UZ
;3ꢂꢂ
UZ
;3ꢂꢄ
UZ
;3ꢂꢁ
UZ
;3ꢄꢃ
UZ
;3ꢄꢀ
UZ
Field
Bits
Type
Description
XP30
XP24
XP23
XP22
XP21
XP20
XP14
XP13
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
Bit 0 (LSB) of fourth pulse shape level
Bit 4 (MSB) of third pulse shape level
Bit 3 of third pulse shape level
Bit 2 of third pulse shape level
Bit 1of third pulse shape level
Bit 0 (LSB) of third pulse shape level
Bit 4 (MSB) of second pulse shape level
Bit 3 of second pulse shape level
Data Sheet
133
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionTransmit Pulse Mask 2
Transmit Pulse Mask 2
For description see Transmit Pulse Mask 0
XPM2
Transmit Pulse Mask2
Offset
xx28H
Reset Value
40H
ꢀ
ꢀ
U
ꢁ
ꢂ
'$;/7
UZ
ꢃ
;3',6
UZ
ꢄ
ꢅ
ꢆ
ꢇ
;/7
UZ
;3ꢁꢂ
UZ
;3ꢁꢁ
UZ
;3ꢁꢃ
UZ
;3ꢁꢄ
UZ
Field
0
Bits
7
Type
r
Description
Always ´0´
XLT
6
rw
Transmit Line Tristate
See also Chapter 3.9.1.
0B
1B
Normal operation
Transmit line XL1 and XL2 are switched into high-impedance state.
If this bit is set the transmit line monitor status information is frozen
(default value after hardware reset).
DAXLT
5
rw
Disable Automatic Tristating of XL1/2
See Chapter 3.9.7.
0B
1B
Normal operation. If a short is detected on pins XL1/2 the transmit
line monitor sets the XL1/2 outputs into a high-impedance state.
If a short is detected on XL1/2 pins automatic setting these pins into
a high-impedance (by the XL-monitor) state is disabled.
XPDIS
XP34
4
3
rw
rw
Disable XPM Values
See Chapter 3.9.6.
0B
1B
XP values from registers XPM(2:0) are used for pulse shaping.
TXP values from registers TXP(16:1) are used for pulse shaping.
Bit 4 (MSB) of second pulse shape level
See Chapter 3.9.6.1.
XP33
XP32
XP31
2
1
0
rw
rw
rw
Bit 3 of fourth pulse shape level
Bit 2 of fourth pulse shape level
Bit 1 of fourth pulse shape level
Data Sheet
134
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClear Channel Register 1
Clear Channel Register 1
The registers CCB(1:3) are only valid in T1/J1 mode.
CCB1
Offset
xx2FH
Reset Value
00H
Clear Channel Register 1
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
&+ꢀ
UZ
&+ꢁ
UZ
&+ꢂ
UZ
&+ꢃ
UZ
&+ꢄ
UZ
&+ꢅ
UZ
&+ꢆ
UZ
&+ꢇ
UZ
Field
Bits
Type
rw
Description
Channel Selection Bits
If AMI code is selected, all bits must be set to ´1´ for proper operation.
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
7
6
5
4
3
2
1
0
0B
1B
Normal operation. Bit robbing information and zero code
suppression (ZCS, B7 stuffing) can change contents of the selected
speech/data channel if assigned modes are enabled by bits
MR5.EIBR and MR0.XC(1:0).
Clear channel mode. Contents of selected speech/data channel
are not overwritten by internal or external bit robbing and ZCS
information. Transmission of channel assigned signaling and
control of pulse-density is applied by the user.
Registers CCB2 and CCB3 have the same description.
The Offset Addresses are listed in CCBn Overview, for layout and bit names refer to Clear Channel Registers
Table 39
CCBn Overview
Register Short Name
Register Long Name
Offset Address Page Number
CCB2
CCB3
Clear Channel Register 2
Clear Channel Register 3
xx30H
xx31H
Table 40
Clear Channel Registers
7
6
5
4
3
2
1
0
CCB1
CCB2
CCB3
CH1
CH9
CH17
CH2
CH10
CH18
CH3
CH11
CH19
CH4
CH12
CH20
CH5
CH13
CH21
CH6
CH14
CH22
CH7
CH15
CH23
CH8
CH16
CH24
Data Sheet
135
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMode Register 3
Mode Register 3
Only valid in E1 mode.
MR3
Mode Register 3
Offset
xx31H
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
;/'
UZ
;/8
UZ
&0,
UZ
5HV
Field
Bits
Type
Description
XLD
5
rw
Transmit LLB Down Code, E1 only
This bit is not valid in T1/J1 mode. In T1/J1 mode the bis MR5.XLD is
used instead.
0B
1B
Normal operation.
A one in this bit position causes the transmitter to replace normal
transmit data with the LLB down (deactivate) Code continuously
until this bit is reset. The LLB down Code is optionally overwritten
by the time slot 0 depending on bit LCR1.FLLB.
XLU
CMI
4
rw
Transmit LLB UP Code, E1 only
This bit is not valid in T1/J1 mode. In T1/J1 mode the bit MR5.XLU is used
instead.
0B
1B
Normal operation.
A one in this bit position causes the transmitter to replace normal
transmit data with the LLB UP Code continuously until this bit is
reset. The LLB UP Code is overwritten by the time slot 0 depending
on bit LCR1.FLLB. For proper operation bit MR3.XLD must be
cleared.
3
rw
Select CMI Precoding, E1 only
This bit is not valid in T1/J1 mode. In T1/J1 mode the similar bit for B8ZS
precoding is DIC3.CMI.
In E1 mode only valid if CMI code (MR0.XC(1:0) = ´01b´) is selected. This
bit defines the CMI precoding and influences transmit and receive data.
Note: Before local loop is selected, HDB3 precoding has to be disabled.
0B
1B
CMI with HDB3 precoding
CMI without HDB3 precoding
Data Sheet
136
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Interface Mode 0
Line Interface Mode 0
LIM0
Offset
xx36H
Reset Value
00H
Line Interface Mode 0
ꢀ
ꢁ
;'26
UZ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
;)%
UZ
5756
UZ
'&,0
UZ
5HV
5/0
UZ
//
UZ
0$6
UZ
Field
Bits
Type
Description
XFB
7
rw
Transmit Full Bauded Mode
Only applicable for dual-rail mode (bit LIM1.DRS = ´1´).
Note: If CMI coding is selected (MR0.XC(1:0) = ´01b´) this bit has to be
cleared.
0B
1B
Output signals XDO/XDON are half bauded.
Output signals XDO/XDON are full bauded.
XDOS
6
rw
Transmit Data Out Sense
Note: If CMI coding is selected (MR0.XC(1:0) = ´01b´) this bit has to be
cleared. The transmit frame marker XFM is independent of this bit.
0B
Output signals XDO/XDON are active low. Output XOID is active
high (normal operation).
1B
Output signals XDO/XDON are active high. Output XOID is active
low.
RTRS
5
4
rw
rw
Receive Termination Resistance Selection
This bit controls switching of the internal 300 Ω resistance at the receive
line interface, see also Chapter 3.7.3.
Note: If the RLT functionality is selected at one of the multi function ports,
the 300 Ω resistance is switched off, independend from RTRS and
the level at RLT. If RLT functionality is not configured at one of the
multi function ports, the 300 Ω switch is controlled only by RTRS.
0B
1B
300 Ω resistance is switched off.
300 Ω resistance is switched on.
DCIM
Digital Clock Interface Mode
Note: DCO-X must be used in DCIM mode (CMR1.DXJA = ´0´).
0B
1B
normal operation.
enables the digital Clock Interface Mode (synchronization interface
mode) according to ITU-T G.703, Section 13.
A 2048/1544 kHz clock is expected on RL1/2. On XL1/2 a
2048/1544 kHz output clock is driven. The transmit clock signal on
XL1/2 is derived from the clock supplied on FCLKX
(CMR1.DXSS = ´0´).
Data Sheet
137
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Interface Mode 0
Field
Bits
Type
Description
RLM
2
rw
Receive Line Monitoring
See Chapter 3.7.3.2.
0B
1B
Normal receiver mode
Receiver mode for receive line monitoring; the receiver sensitivity
is increased to detect resistively attenuated signals of -20 dB (short-
haul mode only)
LL
1
rw
Local Loop
See Chapter 3.11.4.
0B
1B
Normal operation
Local loop active. The local loop back mode disconnects the
receive lines RL1/RL2 or ROID from the receiver. Instead of the
signals coming from the line the data provided by system interface
are routed through the analog receiver back to the system interface.
The unipolar bit stream is transmitted undisturbed on the line.
Receiver and transmitter coding must be identical. Operates in
analog and digital line interface mode. In analog line interface mode
data is transferred through the complete analog receiver.
MAS
0
rw
Master Mode
See also Table 24.
0B
1B
Slave mode
Master mode on. Setting this bit the DCO-R circuitry is frequency
synchronized to the clock (2.048 MHz or 8 kHz, see IPC.SSYF)
supplied by SYNC. If this pin is connected to VSS or VDD (or left
open and pulled up to VDD internally) the DCO-R circuitry is
centered and no receive jitter attenuation is performed (only if
2.048 MHz clock is selected by resetting bit IPC.SSYF). The
generated clocks are stable.
Data Sheet
138
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Interface Mode 1
Line Interface Mode 1
LIM1
Offset
xx37H
Reset Value
80H
Line Interface Mode 1
ꢀ
&/26
UZ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5,/ꢀ
UZ
5,/ꢁ
UZ
5,/ꢂ
UZ
5HV
-$77
UZ
5/
UZ
'56
UZ
Field
Bits
Type
Description
CLOS
7
rw
Clear Data in Case of LOS
0B
Normal receiver mode, receive data stream is transferred normally
in long-haul mode
1B
received data is cleared (driven to low level), as soon as LOS is
detected
RIL2
RIL1
RIL0
6
5
4
rw
rw
rw
Receive Input Threshold
Only valid if analog line interface is selected (LIM1.DRS = ´0´).“No signal”
is declared if the voltage between pins RL1 and RL2 drops below the
limits programmed by bits RIL(2:0) and the received data stream has no
transition for a period defined in the PCD register.
See DC characteristics for detail.
JATT
2
rw
Transmit Jitter Attenuator
Note: JATT is only used to define the jitter attenuation during remote loop
operation. Remote loop operation can be set by LIM1.RL Jitter
attenuation during normal operation is not affected by JATT.
0B
Transmit jitter attenuator is disabled for remote Loop. Transmit
data bypasses the remote loop jitter attenuator buffer.
Jitter attenuator is active for remote loop. Received data from pins
RL1/2 or ROID is sent "jitter-free" on ports XL1/2 or XOID. The de-
jittered clock is generated by the DCO-X circuitry.
1B
RL
1
0
rw
rw
Remote Loop
Note: RL is logically OR´d with automatic loop switching by BOM
messages.
0B
1B
Normal operation.
Remote Loop active.
DRS
Dual-Rail Select
0B
The ternary interface is selected. Ports RL1/2 and XL1/2 become
analog in/outputs.
1B
The digital dual-rail interface is selected. Received data is latched
on ports RDIP/RDIN while transmit data is output on pins
XDOP/XDON.
Data Sheet
139
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPulse Count Detection Register
Pulse Count Detection Register
PCD
Offset
xx38H
Reset Value
00H
Pulse Count Detection Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
3&'
UZ
Field
PCD
Bits
7:0
Type
rw
Description
Pulse Count Detection
A LOS alarm is detected if the incoming data stream has no transitions
for a programmable number T consecutive pulse positions. The number
T is programmable by the PCD register and can be calculated as follows:
T = 16 x (N+1); with 0 ≤ N ≤ 255.The maximum time is: 256 x 16 x 488 ns
= 2 ms. Every detected pulse resets the internal pulse counter. The
counter is clocked with the receive clock RCLK.
Data Sheet
140
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPulse Count Recovery
Pulse Count Recovery
PCR
Offset
xx39H
Reset Value
00H
Pulse Count Recovery
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
3&5
UZ
Field
PCR
Bits
7:0
Type
rw
Description
Pulse Count Recovery
A LOS alarm is cleared if a pulse-density is detected in the received bit
stream. The number of pulses M which must occur in the predefined PCD
time interval is programmable by the PCR register and can be calculated
as follows: M = N+1; with 0 ≤ N ≤ 255.The time interval starts with the first
detected pulse transition. With every received pulse a counter is
incremented and the actual counter is compared to the contents of PCR
register. If the pulse number is higher or equal to the PCR value the LOS
alarm is reset otherwise the alarm stays active. In this case the next
detected pulse transition starts a new time interval.
Data Sheet
141
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Interface Mode 2
Line Interface Mode 2
LIM2
Offset
xx3AH
Reset Value
20H
Line Interface Mode 2
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
03$6
UZ
ꢇ
5HV
6/7ꢀ
UZ
6/7ꢁ
UZ
6&)
UZ
(/7
UZ
5HV
Field
SLT1
SLT0
Bits
5
4
Type
rw
rw
Description
Receive Slicer Threshold
00B The receive slicer generates a mark (digital one) if the voltage at
RL1/2 exceeds 55% of the peak amplitude.
01B The receive slicer generates a mark (digital one) if the voltage at
RL1/2 exceeds 67% of the peak amplitude (recommended in some
T1/J1 applications).
10B The receive slicer generates a mark (digital one) if the voltage at
RL1/2 exceeds 50% of the peak amplitude (default, recommended
in E1 mode).
11B The receive slicer generates a mark (digital one) if the voltage at
RL1/2 exceeds 45% of the peak amplitude.
SCF
ELT
3
2
rw
rw
Select Corner Frequency of DCO-R
Setting this bit reduces the corner frequency of the DCO-R circuit by the
factor of ten to 0.2 Hz. See Chapter 3.7.8.
Note: Reducing the corner frequency of the DCO-R circuitry increases the
synchronization time before the frequencies are synchronized.
Enable Loop-Timed
0B
1B
Normal operation
Transmit clock is generated from the clock supplied by MCLK
which is synchronized to the extracted receive route clock. In this
configuration the transmit elastic buffer has to be enabled. For
correct operation of loop timed the remote loop (bit LIM1.RL = ´0´)
must be inactive and bit CMR1.DXSS must be cleared.
MPAS
1
rw
Multi Purpose Analog Switch
Controls the multi purpose analog switch at receive line interface if
GPC(3:6).ENMPAS are all set to ´1´ . If RLT is not configured at any multi
function port, only MPAS controls the switch. If RLT is configured at one
of the multi function ports see Table 14 for contrrolling.
0B
1B
multi purpose analog switch is óff´.
multi purpose analog switch is on´.
Data Sheet
142
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLoop Code Register 1
Loop Code Register 1
LCR1
Loop Code Register 1
Offset
xx3BH
Reset Value
00H
ꢀ
(350
UZ
ꢁ
;35%6
UZ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
/'&
/$&
)//%
UZ
//%3
UZ
UZ
UZ
Field
Bits
Type
Description
EPRM
7
rw
Enable Pseudo-Random Binary Sequence Monitor
See Chapter 3.11.1.
0B
1B
Pseudo-Random Binary Sequence (PRBS) monitor is disabled.
PRBS is enabled. Setting this bit enables incrementing the CEC2
error counter with each detected PRBS bit error. With any change
of state of the PRBS internal synchronization status an interrupt
ISR1.LLBSC is generated. The current status of the PRBS
synchronizer is indicated by bit LSR2.LLBAD.
XPRBS
LDC
6
rw
rw
Transmit Pseudo-Random Binary Sequence
A one in this bit position enables transmission of a pseudo-random binary
sequence to the remote end. Depending on bit LLBP the PRBS is
generated according to 215 -1 or 220 -1 with a maximum-14-zero
restriction (ITU-T O. 151). See Chapter 3.11.1.
5:4
Length Deactivate (Down) Code
These bits defines the length of the LLB deactivate code which is
programmable in register LCR2.
00B Length: 5 bit
01B Length: 6 bit, 2 bit, 3 bit
10B Length: 7 bit
11B Length: 8 bit, 2 bit, 4bit
LAC
3:2
rw
Length Activate (Up) Code
These bits defines the length of the LLB activate code which is
programmable in register LCR3.
00B Length: 5 bit
01B Length: 6 bit, 2 bit, 3 bit
10B Length: 7 bit
11B Length: 8 bit, 2 bit, 4 bit
FLLB
LLBP
1
0
rw
rw
Framed Line Loop-Back/Invert PRBS
Depending on bit LCR1.XPRBS this bit enables different functions:
LCR1.XPRBS = ´0´: Table 41.
Note: Invert PRBS LCR1.XPRBS = ´1´: see Table 42
Line Loop-Back Pattern
See Chapter 3.11.2
LCR1.XPRBS = ´0´: see Table 43
LCR1.XPRBS = ´1´ or LCR1.EPRM = ´1´: see Table 44
Data Sheet
143
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
Table 41
FLLB Constant Values (Case 1)
Name and Description
Value
Framed Line Loop-Back/Invert PRBS
The line loop-back code is transmitted including framing bits. LLB code overwrites the
FS/DL-bits.
0B
Framed Line Loop-Back/Invert PRBS
The line loop-back code is transmitted unframed. LLB code does not overwrite the FS/DL-
bits.
1B
Table 42
FLLB Constant Values (Case 2)
Name and Description
Value
Framed Line Loop-Back/Invert PRBS
The generated PRBS is transmitted not inverted.
0B
Framed Line Loop-Back/Invert PRBS
The PRBS is transmitted inverted.
1B
Table 43
LLBP Constant Values (Case 1)
Name and Description
Value
Line Loop-Back Pattern
Fixed line loop-back code according to ANSI T1. 403.
0B
Line Loop-Back Pattern
Enable user-programmable line loop-back code by register LCR2/3.
1B
Table 44
LLBP Constant Values (Case 2)
Name and Description
Value
Line Loop-Back Pattern
0B
215 -1
Line Loop-Back Pattern
1B
220 -1
Data Sheet
144
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLoop Code Register 2
Loop Code Register 2
LCR2
Loop Code Register 2
Offset
xx3CH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
/'&
UZ
Field
LDC
Bits
7:0
Type
rw
Description
Line Loop-Back Deactivate Code
If enabled by bit MR3.XLD = ´1´ in E1 or MR5.XLD = ´1´ in T1/J1 mode
the LLB deactivate code automatically repeats until the LLB generator is
stopped. Transmit data is overwritten by the LLB code. LDC0 is
transmitted last. For correct operations bit LCR1.XPRBS has to cleared.
If LCR2 is changed while the previous deactivate code has been detected
and is still received, bit LSR2.LLBDD in E1 or LSR1.LLBDD in T1/J1
mode will stay active until the incoming signal changes or a receiver reset
is initiated (CMDR.RRES = ´1´).
Data Sheet
145
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLoop Code Register 3
Loop Code Register 3
LCR3
Loop Code Register 3
Offset
xx3DH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
/$&
UZ
Field
LAC
Bits
7:0
Type
rw
Description
Line Loop-Back Activate Code
If enabled by bit MR3.XLD = ´1´ in E1 or MR5.XLD = ´1´ in T1/J1 mode
the LLB activate code automatically repeats until the LLB generator is
stopped. Transmit data is overwritten by the LLB code. LAC0 is
transmitted last. For correct operations bit LCR1.XPRBS has to cleared.If
LCR3 is changed while the previous activate code has been detected and
is still received, bit LSR2.LLBAD in E1 or LSR1.LLBAD in T1/J1 mode will
stay active until the incoming signal changes or a receiver reset is
initiated (CMDR.RRES = ´1´).
Data Sheet
146
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionDigital Interface Control 1
Digital Interface Control 1
See Chapter 3.7.9.
DIC1
Offset
xx3EH
Reset Value
00H
Digital Interface Control 1
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
5%6
5HV
%,0
UZ
;%6
UZ
UZ
Field
Bits
Type
Description
RBS
5:4
rw
Receive Buffer Size
See Table 26.
00B Buffer size: 2 frames
01B Buffer size: 1 frame
10B Buffer size: 96 bits
11B bypass of receive elastic store
BIM
2
rw
rw
Bit Interleaved Mode
0B
1B
Byte interleaved mode
Bit interleaved mode
XBS
1:0
Transmit Buffer Size
See Table 26.
00B Bypass of transmit elastic store
01B Buffer size: 1 frame
10B Buffer size: 2 frames
11B Buffer size: 96 bits
Data Sheet
147
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionDigital Interface Control 2
Digital Interface Control 2
DIC2
Offset
xx3FH
Reset Value
00H
Digital Interface Control 2
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
&5%
UZ
5HV
Field
CRB
Bits
5
Type
rw
Description
Center Receive Elastic Buffer
Only applicable if the time slot assigner is disabled (PC(3:1).RPC(3:0) =
´0001b´), no external or internal synchronous pulse receive is generated.
A transition from low to high forces a receive slip and the read- pointer of
the receive elastic buffer is centered. The delay through the buffer is set
to one half of the current buffer size. It should be hold high for at least two
2.048 MHz periods before it is cleared.
Data Sheet
148
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionDigital Interface Control 3
Digital Interface Control 3
DIC3
Offset
xx40H
Reset Value
00H
Digital Interface Control 3
ꢀ
ꢁ
5575,
UZ
ꢂ
ꢃ
ꢄ
ꢅ
5(65
UZ
ꢆ
ꢇ
&0,
UZ
575,
UZ
)6&7
UZ
5(6;
UZ
5HV
Field
Bits
Type
Description
CMI
7
rw
Select CMI Precoding (T1 only)
Only valid if CMI code (MR0.XC(1:0) = ´01b´) is selected. This bit defines
the CMI precoding and influences transmit and receive data.
Note: Before local loop is closed, B8ZS precoding has to be switched off.
0B
1B
CMI with B8ZS precoding
CMI without B8ZS precoding
RRTRI
RTRI
6
5
rw
RDO Tristate Mode
See Chapter 3.7.3.4
Note: RRTRI is logically exored with RTDMT multi function port, if this
function is selected. RTDMT exor RRTRI sets additionally RCLK
into tristate.
00B normal operation (RDOP is switched to low level during inactive
channel/bit phases).
01B RDO is switched into tristate mode during inactive channel/bit
phases.
10B RDO is tristate constantly (and also RCLK).
11B RDO is tristate constantly (and also RCLK).
FSCT
RESX
4
3
rw
rw
FSC Tristate Mode
0B
1B
normal operation of FSC pin.
FSC is switched into tristate mode.
Rising Edge Synchronous Transmit
Depending on this bit all transmit framer interface data are clocked
(outputs) or sampled (inputs) with the selected active edge of the
selected framer transmit clock.
Only valid if CMR2.IXSC = ´0´:
Note: CMR2.IXSC = ´1´: value of RESX bit has no impact on the selected
edge of the system interface clock but value of RESR bit is used as
RESX. Example: If RESR = ´0´, the rising edge of system interface
clock is the selected one for sampling data on XDI and vice versa.
0B
Clocked or sampled with the first falling edge of the selected framer
interface transmit clock.
Clocked or sampled the first rising edge of the selected framer
interface transmit clock.
1B
Data Sheet
149
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionDigital Interface Control 3
Field
Bits
Type
Description
RESR
2
rw
Rising Edge Synchronous Receive
Depending on this bit all receive framer interface data are clocked
(outputs) or sampled (inputs) with the selected active edge.
0B
Clocked or sampled with the first falling edge of the selected framer
interface receive clock.
1B
Clocked or sampled with the first rising edge of the selected framer
interface receive clock.
Data Sheet
150
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 4
Clock Mode Register 4
CMR4
Clock Mode Register 4
Offset
xx41H
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
,$5
UZ
56
UZ
Field
Bits
Type
Description
IAR
7:3
rw
Integral Parameter Selection
(Corner frequency and attenuation selection) for the DCO-R
Only valid if CMR6.DCOCOMPN = ´1´and CMR2.ECFAR = ´1´, see
Chapter 3.7.8.
RS
2:0
rw
Receive Clock (RCLK) Frequency Selection
See also Chapter 3.7.
000B clock recovered from the line through the DPLL drives RCLK.
001B clock recovered from the line through the DPLL drives RCLK.
logically OR´d with the incoming LOS signal.
010B 2.048 MHz, dejitered, sourced by DCO-R.
011B 4.096 MHz, dejitered, sourced by DCO-R.
100B 8.192 MHz, dejitered, sourced by DCO-R.
101B 16.384 MHz, dejitered, sourced by DCO-R.
110B 2.048 MHz logically OR´d with LOS.
111B 16.384 MHz logically OR´d with LOS.
Data Sheet
151
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 5
Clock Mode Register 5
Note:The reset value depends on the channel, so that for the DCO-R the current channel is selected by the bits
DRSS (for example for channel 3 the reset value is ´40´H).
CMR5
Clock Mode Register 5
Offset
xx42H
Reset Value
00H
ꢀ
ꢁ
'566
UZ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
,$;
UZ
Field
Bits
Type
Description
DRSS
7:5
rw
DCO-R Channel Selection
See Chapter 3.7.
000B receive reference clock generated by the DPLL of channel 1.
001B receive reference clock generated by the DPLL of channel 2.
010B receive reference clock generated by the DPLL of channel 3.
011B receive reference clock generated by the DPLL of channel 4.
1xxB reserved.
IAX
4:0
rw
Integral Parameter Selection
(Corner frequency and attenuation selection) for the DCO-X
Only valid if CMR6.DCOCOMPN = ´1´ and CMR2.ECFAX = ´1´, see
Chapter 3.7.8.
Data Sheet
152
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 6
Clock Mode Register 6
CMR6
Clock Mode Register 6
Offset
xx43H
Reset Value
00H
ꢀ
ꢁ
65(65
UZ
ꢂ
65(6;
UZ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
'&2&203
1
67)
UZ
6&);
UZ
$7&6
UZ
UZ
Field
Bits
Type
Description
DCOCOMPN
7
rw
Compatibility Programming of DCO-R/DCO-X Disable
Only applicable if CMR2.ECFAR/ECFAX is set. See Chapter 3.7.8,
Table 23.
0B
programming of corner frequencies of DCO-R/DCO-X is done with
registers CMR3.CFAR (3:0) /CFAX(3:0), compatible to the
QuadLIU. Register bits CMR5.IAX(4:0)/CMR4.IAR(4:0) are not
valid.
1B
programming of corner frequencies and attenuation factors of
DCO-R/DCO-X is done with registers CMR3.CFAR
(3:0)/CFAX(3:0) and CMR4.IAR(4:0)/CMR5.IAX(4:0) in the range
0.2 ... 20 Hz.
SRESR
SRESX
STF
6
rw
rw
rw
Soft Reset of DCO-R
By setting this bit a soft reset of the DCO-R will be performed: The initial
phase error is set to zero and the loop filter is cleared. To enable the
DCO-R lock functionality, this bit must be cleared subsequently. See
Chapter 3.7.8.
0B
1B
DCO-R enabled (normal lock functionality).
soft reset of DCO-R, no lock functionality.
5
Soft Reset of DCO-X
By setting this bit a soft reset of the DCO-X will be performed: The initial
phase error is set to zero and the loop filter is cleared. To enable the
DCO-X lock functionality, this bit must be cleared subsequently. See
Chapter 3.7.8.
0B
1B
DCO-X enabled (normal lock functionality).
soft reset of DCO-X, no lock functionality.
4:2
Transmit Clock (TCLK) Frequency Selection
See Chapter 3.9.2. Note that frequencies are not in ascent ordering.
000B 2.048 MHz.
001B 8.192 MHz.
010B 4.096 MHz.
011B 16.384 MHz.
100B 32.768 MHz.
101B reserved.
110B reserved.
111B reserved.
Data Sheet
153
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 6
Field
Bits
Type
Description
SCFX
1
rw
Select Corner Frequency of DCO-X
Only applicable if CMR2.EXFAX = ´0´. See Chapter 3.7.8 and
Chapter 3.9.4.
0B
1B
corner frequency of DCO-X is 2 Hz.
corner frequency of DCO-X is 0.2 Hz.
ATCS
0
rw
Automatic Transmit Clock Switching
See Chapter 3.9.3. If TCLK is lost, automatically switching to FCLKX can
be performed.
Note: Kind of used transmit clock source is shown in status register
XCLKS.
0B
1B
automatic clock switching is disabled.
automatic clock switching is enabled.
Data Sheet
154
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 1
Clock Mode Register 1
CMR1
Clock Mode Register 1
Offset
xx44H
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
'&6
UZ
5HV
';-$
UZ
';66
UZ
Field
Bits
Type
Description
DCS
3
1
0
rw
rw
rw
Disable Clock-Switching
In Slave mode (LIM0.MAS = ´0´) the DCO-R is synchronized on the
recovered route clock. In case of loss-of-signal LOS the DCO-R switches
automatically to the clock sourced by port SYNC.
0B
1B
automatic switching from RCLK to SYNC is enabled
automatic switching from RCLK to SYNC is disabled
DXJA
DXSS
Disable Internal Transmit Jitter Attenuation
Setting this bit disables the transmit jitter attenuation. Reading the data
out of the transmit elastic buffer and transmitting on XL1/2
(XDOP/N/XOID) is done with the clock provided on pin TCLK. In transmit
elastic buffer bypass mode the transmit clock is taken from FCLKX,
independent of this bit.
DCO-X Synchronization Clock Source
0B
The DCO-X circuitry synchronizes to the internal reference clock
which is sourced by FCLKX/R or RCLK. Since there are many
reference clock opportunities the following internal prioritizing in
descending order from left to right is realized: LIM1.RL >
CMR1.DXSS > LIM2.ELT > current working clock of transmit
system interface. If one of these bits is set the corresponding
reference clock is taken.
DCO-X synchronizes to an external reference clock provided on
multi function port XPA or XPB pin function TCLK, if no remote loop
is active. TCLK is selected by PC(2:1).XPC(3:0) = ´0011B´.
1B
Data Sheet
155
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 2
Clock Mode Register 2
CMR2
Clock Mode Register 2
Offset
xx45H
Reset Value
00H
ꢀ
(&)$;
UZ
ꢁ
(&)$5
UZ
ꢂ
'&2;&
UZ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
'&)
UZ
,563
UZ
,56&
UZ
5HV
,;6&
UZ
Field
Bits
Type
Description
ECFAX
7
rw
Enable Corner Frequency Adjustment for DCO-X
See Chapter 3.7.8.
Note: DCO-X must be activated.
0B
1B
adjustment is disabled (only 2 Hz and 0.2 Hz are possible).
adjustment is enabled as programmed in CMR3.CFAX(3:0) and
CMR4.IAX(4:0).
ECFAR
6
rw
Enable Corner Frequency Adjustment for DCO-R
See Chapter 3.7.8.
Note: DCO-R must be activated.
0B
1B
adjustment is disabled (only 2 Hz and 0.2 Hz are possible).
adjustment is enabled as programmed in CMR3.CFAR(3:0) and
CMR5.IAR(4:0).
DCOXC
DCF
5
4
rw
rw
DCO-X Center-Frequency Enable
See Chapter 3.7.8
0B
1B
The center function of the DCO-X circuitry is disabled.
The center function of the DCO-X circuitry is enabled. DCO-X
centers to 2.048 MHz related to the master clock reference (MCLK),
if reference clock (e.g. FCLKX) is missing.
DCO-R Center- Frequency Disabled
See also Table 24.
0B
The DCO-R circuitry is frequency centered in master mode if no
2.048 MHz reference clock on pin SYNC is provided or in slave
mode if a loss-of-signal occurs in combination with no 2.048 MHz
clock on pin SYNC or a gapped clock is provided on pin RCLKI and
this clock is inactive or stopped.
The center function of the DCO-R circuitry is disabled. The
generated clock (DCO-R) is frequency frozen in that moment when
no clock is available on pin SYNC or pin RCLKI. The DCO-R
circuitry starts synchronization as soon as a clock appears on pins
SYNC or RCLKI.
1B
Data Sheet
156
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 2
Field
Bits
Type
Description
IRSP
3
rw
Internal Receive System Frame Sync Pulse
Note: Recommendation: This bit should be set to ´1´.
0B
The frame sync pulse is derived from RDOP output signal internally
(free running).
The frame sync pulse for the receive system interface is internally
sourced by the DCO-R circuitry. This internally generated frame
sync signal can be output (active low) on multifunction ports RP(A
to D) (RPC(3:0) = ´0001H´).
1B
IRSC
IXSC
2
0
rw
rw
Internal Receive Digital (Framer) Clock
0B
The working clock for the receive framer interface is sourced by
FCLKR or in receive elastic buffer bypass mode from the
corresponding extracted receive clock RCLK.
1B
The working clock for the receive framer interface is sourced
internally by DCO-R or in bypass mode by the extracted receive
clock. FCLKR is ignored.
Internal Transmit Digital (Framer) Clock
0B
The working clock for the transmit framer interface is sourced by
FCLKX.
The working clock for the transmit framer interface is sourced
internally by the working clock of the receive framer interface.
FCLKX is ignored.
1B
Data Sheet
157
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Configuration Register
Global Configuration Register
GCR
Offset
0046H
Reset Value
00H
Global Configuration Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
9,6
UZ
6&,
UZ
5HV
3'
UZ
Field
Bits
Type
Description
VIS
7
rw
Masked Interrupts Visible
See also Chapter 3.5.3
0B
1B
Masked interrupt status bits are not visible in registers ISR(7:0).
Masked interrupt status bits are visible in ISR(7:0), but they are not
visible in register GIS.
SCI
PD
6
rw
Status Change Interrupt
0B
Interrupts are generated either on activation or deactivation of the
internal interrupt source.
1B
The following interrupts are activated both on activation and
deactivation of the internal interrupt source: ISR2.LOS, ISR2.AIS,
ISR3.LMFA16.
0
rw
Power Down
Switches between power-up and power-down mode. After switching from
power down to power up a receiver reset should be made by setting of
CMDR.RRES.
0B
1B
Power up
Power down: All outputs are driven inactive; multifunction ports are
driven high by the weak internal pull-up device.
Data Sheet
158
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Mode Register 3
Clock Mode Register 3
CMR3
Clock Mode Register 3
Offset
xx48H
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
&)$;
&)$5
UZ
UZ
Field
Bits
Type
Description
CFAX
7:4
rw
Corner Frequency Adjustment for DCO-X
see Chapter 3.7.8.
Note: DCO-X must be activated and CMR2.ECFAX must be set
(adjustment must be enabled).
CFAR
3:0
rw
Corner Frequency Adjustment for DCO-R
See Chapter 3.7.8.
Note: DCO-R must be activated and CMR2.ECFAR must be set
(adjustment must be enabled).
Data Sheet
159
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPort Configuration 1
Port Configuration 1
See Chapter 3.12.
PC1
Offset
xx80H
Reset Value
00H
Port Configuration 1
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
53&ꢀ
;3&ꢀ
UZ
UZ
Field
Bits
Type
Description
RPC1
7:4
rw
Receive Multifunction Port Configuration
See Chapter 3.12. The multifunction ports RP(A to D) are bidirectional.
After Reset the ports RPA and RPB are reserved, the port RPC is
configured as RCLK output. With the selection of the pin function the
In/Output configuration is also achieved. Register PC1 configures port
RPA, while PC2 configures port RPB, PC3 configures port RPC and PC4
configures port RPD.
See RPC1 Constant Values
XPC1
3:0
rw
Transmit Multifunction Port Configuration
See Chapter 3.12. The multifunction ports XP(A to D) are bidirectional.
After Reset these ports are configured as inputs. With the selection of the
pin function the In/Output configuration is also achieved. Each of the
three different input functions (TCLK, XLT and XLT) may only be selected
once. No input function must be selected twice or more. Register PC1
configures port XPA, PC2 configures port XPB, PC3 configures port XPC
and PC4 the port XPD.
See XPC1 Constant Values
Table 45
RPC1 Constant Values
Name and Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Value
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
RLT: Receive line termination (input)
“Hardware” switching of receive line termination, see Chapter 3.7.3 and LIM0.
GPI: general purpose input
Value of this input is stored in register MFPI.
1001B
Data Sheet
160
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
Table 45
RPC1 Constant Values (cont’d)
Name and Description
Value
GPOH: General purpose output, high level
Pin is set fixed to high level
1010B
GPOL: General purpose output, low level
1011B
1100B
1101B
1110B
1111B
Pin is set fixed to low level
LOS: Loss of signal
Loss of signal indication output
RTDMT: Receive TDM tristate (input)
Receive TDM i/f tristate (RDOP, RCLK).
RDON: Receive data out negative
Negative receive data out in dual rail mode or bipolar violation out in LIU single rail mode
RCLK: RCLK output
Table 46
XPC1 Constant Values
Name and Description
Reserved
Reserved
Reserved
TCLK: Transmit Clock (Input)
A 2.048/8.192 MHz clock has to be sourced by the system if the internal generated transmit
clock (DCO-X) is not used. Optionally this input is used as a synchronization clock for the
DCO-X circuitry with a frequency of 2.048 MHz.
Value
0000B
0001B
0010B
0011B
Reserved
Reserved
Reserved
XCLK: Transmit Line Clock (Output)
Frequency: 2.048 MHz
0100B
0101B
0110B
0111B
XLT: Transmit Line Tristate control input, high active
With a high level on this port the transmit lines XL1/2 or XDOP/N are set directly into tristate.
This pin function is logically OR´d with register XPM2.XLT. See Chapter 3.9.1.
1000B
GPI: General Purpose Input, low level
1001B
1010B
1011B
Value of this input is stored in register MFPI.
GPOH: General Purpose Output, high level
Pin is set fixed to high level
GPOL: General Purpose Output, low level
Pin is set fixed to low level
Reserved
1100B
1101B
XDIN: Transmit Data In Negative
Negative transmit data in for dual rail mode
XLT: Transmit Line Tristate control input, low active
1110B
1111B
See XLT
Reserved
Only one of the ports RPA, RPB, RPC or RPD must be configured as RTDMT.
Only one of the ports XPA, XPB, XPC or XPD must be configured as XLT or XLT.
Data Sheet
161
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
The registers PC1, PC2 and PC4 have the reset values ´00H´, PC3 has the reset value ´F0H´.
The Offset Addresses are listed in PCn Overview, for bit names refer to Port Configuration Registers.
Table 47
PCn Overview
Register Short Name
Register Long Name
Offset Address Page Number
PC2
PC3
PC4
Port Configuration Register 2
Port Configuration Register 3
Port Configuration Register 4
xx81H
xx82H
xx83H
Table 48
Port Configuration Registers
7
6
5
4
3
2
1
0
PC1
PC2
PC3
PC4
RPC13
RPC23
RPC33
RPC43
RPC12
RPC22
RPC32
RPC42
RPC11
RPC21
RPC31
RPC41
RPC10
RPC20
RPC30
RPC40
XPC13
XPC23
XPC33
XPC43
XPC12
XPC22
XPC32
XPC42
XPC11
XPC21
XPC31
XPC41
XPC10
XPC20
XPC30
XPC40
Data Sheet
162
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPort Configuration 5
Port Configuration 5
PC5
Offset
xx84H
Reset Value
00H
Port Configuration 5
ꢀ
3+'6;
UZ
ꢁ
3+'65
UZ
ꢂ
ꢃ
ꢄ
ꢅ
ꢀ
ꢆ
&653
UZ
ꢇ
5HV
&53
UZ
UZ
Field
Bits
Type
Description
PHDSX
7
rw
Phase Decoder Switch for DCO-X
See formulas in GCM6.
0B
1B
switch phase decoder by 1/3
switch phase decoder by 1/6
PHDSR
6
rw
Phase Decoder Switch for DCO-R
See formulas in GCM6.
0B
1B
switch phase decoder by 1/3
switch phase decoder by 1/6
0
2
1
rw
rw
Fixed 0
CSRP
Configure FCLKR Port
0B
1B
FCLKR: Input
FCLKR: Output
CRP
0
rw
Configure RCLK Port
0B
1B
RCLK: Input
RCLK: Output
Data Sheet
163
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Port Configuration 1
Global Port Configuration 1
GPC1
Offset
0085H
Reset Value
00H
Global Port Configuration 1
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
&6)3
5HV
UZ
Field
CSFP
Bits
6:5
Type
rw
Description
Configure SEC/FSC Port
The FSC pulse is generated if the DCO-R circuitry of the selected channel
is active (CMR2.IRSC = ´1´ or CMR1.RS(1:0) = ´10b´ or ´11b´), see
Chapter 3.8.4
00B SEC: Input, active high
01B SEC: Output, active high
10B FSC: Output, active high
11B FSC: Output, active low
Data Sheet
164
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPort Configuration 6
Port Configuration 6
PC6
Offset
xx86H
Reset Value
00H
Port Configuration 6
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
765(
UZ
5HV
Field
TSRE
Bits
6
Type
rw
Description
Transmit Serial Resistor Enable
0B
1B
Internal serial resistors are disabled.
Internal serial resistors are enabled.
Data Sheet
165
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Port Configuration Register 2
Global Port Configuration Register 2
GPC2
Offset
008AH
Reset Value
00H
Global Port Configuration Register 2
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
)66
UZ
5HV
5ꢀ6
UZ
Field
Bits
Type
Description
FSS
6:4
rw
FSC Source Selection
See Chapter 3.8.4.
000B FSC sourced by channel 1.
001B FSC sourced by channel 2.
010B FSC sourced by channel 3.
011B FSC sourced by channel 4.
1xxB reserved.
R1S
2:0
rw
RCLK1 Source Selection
See Chapter 3.7.
000B RCLK1 sourced by channel 1.
001B RCLK1 sourced by channel 2.
010B RCLK1 sourced by channel 3.
011B RCLK1 sourced by channel 4.
1xxB reserved.
Data Sheet
166
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 1
Global Clock Mode Register 1
GCM1
Offset
0092H
Reset Value
00H
Global Clock Mode Register 1
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
3+'B(ꢀ
UZ
Field
PHD_E1
Bits
7:0
Type
rw
Description
Frequency Adjust for E1 lower 8 bits, for highest 4 bits see GCM2)
For details see calculation formulas in register GCM6 and Table 49.
Data Sheet
167
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 2
Global Clock Mode Register 2
GCM2
Offset
0093H
Reset Value
10H
Global Clock Mode Register 2
ꢀ
3+6'(0
UZ
ꢁ
3+6',5
UZ
ꢂ
3+6'6
UZ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
9)5(4B(
1
3+'B(ꢀ
UZ
UZ
Field
Bits
Type
Description
PHSDEM
7
rw
rw
rw
rw
RX Phase Decoder Demand
0B
1B
default operation
see formulas in GCM6.
PHSDIR
6
5
4
RX Phase Decoder Direction
0B
1B
default operation
see formulas in GCM6.
PHSDS
RX Phase Decoder Switch
0B
1B
default operation
see formulas in GCM6.
VFREQ_EN
Variable Frequency Enable
If “fixed mode” mode is selected the clock frequency at the pin MCLK
must be 2.048 for E1 or 1.544 MHz for T1/J1 respectively. The setting of
the whole clock mode is done automatically: Register bits of GCM1,
GCM2.PHSDEM, PHDIR, PHSDS, PHD_E1 and GCM3 to GCM8 are
unused. If “fixed mode” mode is selected and the SPI- or SCI-interface is
used as controller interface, the pinstrapping values at D(15:5) are also
not used. See also Chapter 3.5.5.
Note: If “fixed mode “ is enabled all of the four ports must work in the same
mode, either in T1 or in E1 mode. A switching between E1 and T1
modes causes a reset of the whole clock system. If “fixed mode“ is
disabled a switching between E1 and T1 mode (which can be done
in this case individually for every port) causes not a reset of the
whole clock system.
0B
1B
Fixed clock frequency of 2.048 (E1) or 1.544 MHz (T1/J1)
Variable master clock frequency (normal operation, operation after
reset)
Data Sheet
168
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 2
Field
Bits
Type
Description
PHD_E1
3:0
rw
Frequency Adjust for E1
(highest 4 bits, for lower 8 bits see GCM1)
The 12 bit frequency adjust value is in the decimal range of -2048 to
+2047. Negative values are represented in 2s-complement format. For
details see calculation formulas in register GCM6 and Table 49.
100000000000B -2048
...B
000000000000B 0
...B
011111111111B +2047
Data Sheet
169
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 3
Global Clock Mode Register 3
GCM3
Offset
0094H
Reset Value
00H
Global Clock Mode Register 3
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
3+'B7ꢀ
UZ
Field
PHD_T1
Bits
7:0
Type
rw
Description
Frequency Adjust for T1
(lower 8 bits, for highest 4 bits see GCM4)
The 12 bit frequency adjust value is in the decimal range of -2048 to
+2047. Negative values are represented in 2s-complement format. For
details see calculation formulas in register GCM6 and Table 49.
100000000000B -2048
...B
000000000000B 0
...B
011111111111B +2047
Data Sheet
170
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 4
Global Clock Mode Register 4
GCM4
Offset
0095H
Reset Value
00H
Global Clock Mode Register 4
ꢀ
ꢁ
'90B7ꢀ
UZ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
3+'B7ꢀ
UZ
Field
Bits
Type
Description
DVM_T1
7:5
rw
Divider Mode for T1
This bits can be write and read to be software compatible to QuadLIU, but
has no influence on the clock system
PHD_T1
3:0
rw
Frequency Adjust for T1
(highest 4 bits, for lower 8 bits see GCM3)
The 12 bit frequency adjust value is in the decimal range of -2048 to
+2047. Negative values are represented in 2s-complement format. For
details see calculation formulas in register GCM6 and Table 49.
100000000000B -2048
...B
000000000000B 0
...B
011111111111B +2047
Data Sheet
171
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 5
Global Clock Mode Register 5
Note:Write operations to GCM5 and GCM6 initiate a PLL reset if the asynchronous interface is selected (IM(1:0)
= ´0x´) and if the “flexible master clocking mode” is selected (GCM2.VFREQ_EN = ´1´), see Chapter 3.5.5.
GCM5
Offset
0096H
Reset Value
00H
Global Clock Mode Register 5
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
3//B0
UZ
ꢆ
ꢇ
0&/.B/2
:
5HV
UZ
Field
Bits
Type
Description
MCLK_LOW
7
rw
Master Clock Range Low
This bit can be write and read to be software compatible to QuadLIU, but
has no influence on the clock system.
PLL_M
4:0
rw
PLL Dividing Factor M
For details see calculation formulas in register GCM6 and Table 49.
00001B 1
...B
11111B 31
Data Sheet
172
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 6
Global Clock Mode Register 6
Note:Write operations to GCM5 and GCM6 initiate a PLL reset if the asynchronous interface is selected (IM(1:0)
= ´0x´) and if the “flexible master clocking mode” is selected (GCM2.VFREQ_EN = ´1´), see Chapter 3.5.5.1.
GCM6
Offset
0097H
Reset Value
00H
Global Clock Mode Register 6
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
3//B1
UZ
ꢆ
ꢇ
5HV
Field
PLL_N
Bits
4:0
Type
rw
Description
PLL Dividing Factor N
For details see calculation formulas below and Table 49.
000001B 1
...B
111111B 63
Flexible Clock Mode Settings:
If “flexible master clock mode” is used (VFREQ_EN = ´1´), the according register settings can be calculated as
follows (a windows-based program for automatic calculation is available, see Chapter 8.3. For some of the
standard frequencies see the table below.
1. The master clock MCLK must be in the following frequency range:
1.02 MHz ≤ fMCLK ≤ 20 MHz
2. Generally the PLL of the master clocking unit includes an input divider with a dividing factor PLL_M +1 and a
feedback divider with a dividing factor 4 x (PLL_N +1). So it generates a clock fPLL of about
fPLL = fMCLK x 4 x (PLL_N +1) / (PLL_M +1).
3. The selection of PLL_N and PLL_M must be done in the following way:
The PLL frequency fPLL must be in the following range:
200 MHz ≤ fPLL ≤ 300 MHz.
The combinations of the values PLL_M and PLL_M must fulfill the equations:
2 MHz ≤ fMCLK / (PLL_M +1) ≤ 6 MHz , if PLL_N is in the range 25 to 63.
5 MHz ≤ fMCLK / (PLL_M +1) ≤ 15 MHz , if PLL_N is in the range 1 to 24.
4. In E1 mode, the selection of PHSN_E1 and PHSX_E1 must be done in such a manner that the frequency for
the receiver fRX_E1 has nearly the value 16 x fDATA_E1 x (1 + 100ppm) = 32.7713 MHz:
fRX_E1 = fPLL / {PHSN_E1 + (PHSX_E1 / 6)}.
In T1/J1 mode, the selection of PHSN_T1 and PHSX_T1 must be done in such a manner that the frequency for
the receiver fRX_T1 has nearly the value 16 x fDATA_T1 x (1 + 100ppm) = 24.706 MHz:
fRX_T1 = fPLL / {PHSN_T1 + (PHSX_T1 / 6)}.
GCM2.PHSDEM, GCM2.PHSDIR, GCM2.PHSDS, PC5.PHDSX and PC5.PHDSR must be left to ´0´
Data Sheet
173
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
5. To bring the “characteristic E1 frequency” foutE1 exact to 16 x fDATA_E1 = 32.7680 MHz a correction value PHD_E1
is necessary:
PHD_E1 = round (12288 x { [PHSN_E1 + (PHSX_E1 / 6)] - [ fpll / (16 x fDATA_E1)] }).
To bring the “characteristic T1 frequency” foutT1 exact to 16 x fDATA_T1 = 24.704 MHz a correction value PHD_T1 is
necessary:
PHD_T1 = round (12288 x { [PHSN_T1 + (PHSX_T1 / 6)] - [ fpll / (16 x fDATA_T1)] }).
Example: fMCLK = 2.048 MHz
PLL_N = 33; PLL_M = 0 : fPLL = 278.528 MHz
PHSN_E1 = 8; PHSN_E1 = 2: fRX_E1 = 33.42 MHz
PHD_E1 = -2048: foutE1 = 32.768 MHz
Table 49
Clock Mode Register Settings for E1 or T1/J1
fMCLK [MHz] GCM1
GCM2
15H
18H
18H
18H
GCM3
00H
FBH
FBH
FBH
GCM4
08H
0BH
0BH
0BH
GCM5
00H
00H
00H
01H
GCM6
3FH
2FH
0BH
0BH
GCM7
9CH
DBH
DBH
DBH
GCM8
DFH
DFH
DFH
DFH
1.5440
2.0480
8.1920
16.3840
00H
00H
00H
00H
Data Sheet
174
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 7
Global Clock Mode Register 7
GCM7
Offset
0098H
Reset Value
80H
Global Clock Mode Register 7
ꢀ
ꢀ
U
ꢁ
ꢂ
3+6;B(ꢀ
UZ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
3+61B(ꢀ
UZ
Field
1
Bits
7
Type
r
Description
Fixed ´1´
PHSX_E1
6:4
rw
Frequency Adjustment value E1
For details see calculation formulas in register GCM6 and Table 49.
000B
...B
0
101B
5
PHSN_E1
3:0
rw
Frequency Adjustment value E1
For details see calculation formulas in register GCM6 and Table 49.
0001B 1
...B
1111B 15
Data Sheet
175
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Clock Mode Register 7
Global Clock Mode Register 7
GCM8
Offset
0099H
Reset Value
80H
Global Clock Mode Register 7
ꢀ
ꢀ
U
ꢁ
ꢂ
3+6;B7ꢀ
UZ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
3+61B7ꢀ
UZ
Field
1
Bits
7
Type
r
Description
Fixed ´1´
PHSX_T1
6:4
rw
Frequency Adjustment Value T1
For details see calculation formulas in register GCM6 and Table 49.
000B
...B
0
101B
5
PHSN_T1
3:0
rw
Frequency Adjustment Value T1
For details see calculation formulas in register GCM6 and Table 49.
0001B 1
...B
1111B 15
Data Sheet
176
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Interrupt Mask Register
Global Interrupt Mask Register
GIMR
Offset
00A7H
Reset Value
FFH
Global Interrupt Mask Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
3///
UZ
Field
PLLL
Bits
0
Type
rw
Description
PLL Locked Interrupt Mask
0B
1B
GIS2.PLLLC is enabled.
GIS2.PLLLC is disabled.
Data Sheet
177
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionTest Pattern Control Register 0
Test Pattern Control Register 0
See Chapter 3.11.1.
TPC0
Offset
xxA8H
Reset Value
00H
Test Pattern Control Register 0
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
353
5HV
UZ
Field
PRP
Bits
5:4
Type
rw
Description
PRBS Pattern Selection
00B PRBS11 pattern.
01B PRBS15 pattern.
10B PRBS20 pattern.
11B PRBS23 pattern.
Data Sheet
178
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionRegister Field Pointer
Register Field Pointer
This register is used to set a pointer (address) onto the internal register field. After a pointer is set, data can be
written into one register of the register field (that register with the address REGFP.FP) by writing data into the
register REGFD. The registers REGFP and REGFD must be used only as described in Chapter 3.6.1 and
Chapter 3.7.8.4. Note that all registers of the register field are reset by a receive reset (CMDR.RRES = ´1´).
REGFP
Register Field Pointer
Offset
00BBH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
)3
Z
Field
FP
Bits
7:0
Type
w
Description
Field Pointer
This bitfield is a pointer onto one rtegister in the internal registerfield.
Data Sheet
179
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionRegister Field Data
Register Field Data
See REGFP and Chapter 3.6.1. for further description.
REGFD
Register Field Data
Offset
00BCH
Reset Value
00H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
'$7$
UZ
Field
DATA
Bits
7:0
Type
rw
Description
Data
Data of one register of the internal register field, pointed with the pointer
FP.
Data Sheet
180
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionBugfix Register
Bugfix Register
See Chapter 3.5.1.
BFR
Bugfix Register
Offset
xxBDH
Reset Value
08H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
%39
UZ
5HV
Field
BPV
Bits
3
Type
rw
Description
Bipolar Violation Detection
This bit selects the kind of Bipolar Violation Detection.
0B
Improved Bipolar Violation Detection: Bipolar Violations (BPV)
consisting on single ´1´ pulses or on two consecutive ´1´ pulses are
detected.
1B
Same behaviour of Bipolar Violation Detection as in the QuadLIUTM
V2.1.
Data Sheet
181
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionTX Pulse Template Register 1
TX Pulse Template Register 1
See Chapter 3.9.6.1 and Chapter 3.9.6.2. This register contains the transmit amplitude of the 1st 1/16 of the
transmit pulse. The contents of this register is ignored unless bit XPM2.XPDIS is set. By default, the values
programmed in XPM0 to XPM2 are used to control the transmit pulse template.
TXP1
Offset
xxC1H
Reset Value
00H
TX Pulse Template Register 1
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
7;3ꢀ
UZ
Field
TXP1
Bits
6:0
Type
rw
Description
Transmit Pulse Amplitude
Two´s Complement number of pulse amplitude.
Registers TXP1to TXP16 have the same description and layout. Every register TXPn defines the amplitude of the
part n of 16 of the transmit pulse. An overview is given is the next table.
Note that the reset values of the registers TXP1 to TXP8 are ´38H´, that of the registers TXP9 to TXP16 are ´00H´.
Table 50
TXP Overview
Register Short Name
TXP2
TXP3
TXP4
TXP5
TXP6
TXP7
TXP8
TXP9
TXP10
TXP11
TXP12
TXP13
TXP14
TXP15
TXP16
Register Long Name
Offset Address Page Number
TX Pulse Template Register 2
TX Pulse Template Register 3
TX Pulse Template Register 4
TX Pulse Template Register 5
TX Pulse Template Register 6
TX Pulse Template Register 7
TX Pulse Template Register 8
TX Pulse Template Register 9
TX Pulse Template Register 10
TX Pulse Template Register 11
TX Pulse Template Register 12
TX Pulse Template Register 13
TX Pulse Template Register 14
TX Pulse Template Register 15
TX Pulse Template Register 16
xxC2H
xxC3H
xxC4H
xxC5H
xxC6H
xxC7H
xxC8H
xxC9H
xxCAH
xxCBH
xxCCH
xxCDH
xxCEH
xxCFH
xxD0H
Data Sheet
182
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Port Configuration Register 3
Global Port Configuration Register 3
See Chapter 3.7.
GPC3
Offset
00D3H
Reset Value
21H
Global Port Configuration Register 3
ꢀ
(103$6
UZ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5ꢀ6
UZ
5HV
5ꢁ6
UZ
Field
Bits
Type
Description
ENMPAS
7
rw
Enable Multi Purpose Analog Switches
GPC(3:6).ENMPAS must be set all to ´1´ to enable in general the
switching of the separate analog switches of all ports.
0B
switching to ón´ of the separate analog switches of all ports is
disabled.
1B
switching to ón´ of the separate analog switches of all ports is
enabled (together with GPC(4:6).MPAS).
R3S
R2S
6:4
2:0
rw
rw
RCLK3 Source Selection
000B RCLK3 sourced by channel 1.
001B RCLK3 sourced by channel 2.
010B RCLK3 sourced by channel 3.
011B RCLK3 sourced by channel 4.
1xxB reserved.
RCLK2 Source Selection
000B RCLK2 sourced by channel 1.
001B RCLK2 sourced by channel 2.
010B RCLK2 sourced by channel 3.
011B RCLK2 sourced by channel 4.
1xxB reserved.
Data Sheet
183
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Port Configuration Register 4
Global Port Configuration Register 4
See Chapter 3.7.
GPC4
Offset
00D4H
Reset Value
03H
Global Port Configuration Register 4
ꢀ
(103$6
UZ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
5ꢀ6
UZ
Field
ENMPAS
Bits
7
Type
rw
Description
Enable Multi Purpose Analog Switches
GPC(3:6).ENMPAS must be set all to ´1´ to enable in general the
switching of the separate analog switches of all ports.
0B
switching to ón´ of the separate analog switches of all ports is
disabled.
1B
switching to ón´ of the separate analog switches of all ports is
enabled (together with GPC(3,5,6).MPAS).
R4S
2:0
rw
RCLK4 Source Selection
000B RCLK4 sourced by channel 1.
001B RCLK4 sourced by channel 2.
010B RCLK4 sourced by channel 3.
011B RCLK4 sourced by channel 4.
1xxB reserved.
Data Sheet
184
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Port Configuration Register 5
Global Port Configuration Register 5
GPC5
Offset
00D5H
Reset Value
65H
Global Port Configuration Register 5
ꢀ
(103$6
UZ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
Field
ENMPAS
Bits
7
Type
rw
Description
Enable Multi Purpose Analog Switches
GPC(3:6).ENMPAS must be set all to ´1´ to enable in general the
switching of the separate analog switches of all ports.
0B
switching to ón´ of the separate analog switches of all ports is
disabled.
switching to ón´ of the separate analog switches of all ports is
enabled (together with GPC(3,4,6).MPAS).
1B
Data Sheet
185
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Port Configuration Register 6
Global Port Configuration Register 6
GPC6
Offset
00D6H
Reset Value
07H
Global Port Configuration Register 6
ꢀ
(103$6
UZ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
&203B',
6
5HV
5HV
UZ
Field
ENMPAS
Bits
7
Type
rw
Description
Enable Multi Purpose Analog Switches
GPC(3:6).ENMPAS must be set all to ´1´ to enable in general the
switching of the separate analog switches of all ports.
0B
switching to ón´ of the separate analog switches of all ports is
disabled.
switching to ón´ of the separate analog switches of all ports is
enabled (together with GPC(3:5).MPAS).
1B
COMP_DIS
5
rw
Compatibility Mode Disable
Setting of this bit disables the compatibility mode. SeeChapter 3.2.
0B
1B
“Compatibility mode”: The QuadLIUTM is fully software compatibel
to the version 2.1.
“Generic mode”: The QuadLIUTM is not fully software compatibel to
the version 2.1 and additional clock configuration features are
available.
Data Sheet
186
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionIn-Band Loop Detection Time Register
In-Band Loop Detection Time Register
INBLDTR
Offset
00D7H
Reset Value
00H
In-Band Loop Detection Time Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
,1%/'5
5HV
,1%/'7
UZ
UZ
Field
INBLDR
Bits
5:4
Type
rw
Description
In-Band Loop Detection Time for Line Side
See Chapter 3.11.2.
00B at least 16 consecutive in-band loop pattern must be valid for
detection and to perform automatic loop switching.
01B at least 32 consecutive in-band loop pattern must be valid for
detection and to perform automatic loop switching.
10B in-band loop pattern must be valid for at least 4 seconds for
detection and to perform automatic loop switching.
11B in-band loop pattern must be valid for at least 5 seconds for
detection and to perform automatic loop switching.
INBLDT
1:0
rw
In-Band Loop Detection Time for Framer Side
See Chapter 3.11.2
00B at least 16 consecutive “In-band loop sequences” must be valid to
perform automatic loop switching.
01B at least 32 consecutive “In-band loop sequences” must be valid to
perform automatic loop switching.
10B “In-band loop sequences” must be valid for at least 4 seconds to
perform automatic loop switching.
11B “In-band loop sequences” must be valid for at least 5 seconds to
perform automatic loop switching.
Data Sheet
187
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionAutomatic Loop Switching Register
Automatic Loop Switching Register
Enabling of automatic loop switching by In-band loop codes, see Chapter 3.11.2, is performed by this register.
ALS
Offset
xxD9H
Reset Value
00H
Automatic Loop Switching Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
6,/6
UZ
/,/6
UZ
Field
SILS
Bits
1
Type
rw
Description
Framer (System) In-Band Loop Switching (Local Loop)
This bit controls if automatic switching of the local loop will be done by In-
Band loop codes from the framer side, see Chapter 3.11.2. The
necessary receiption time of In-band loop codes until an automatic loop
switching is performed is configured by INBLDTR.INBLDT(1:0).
Note: This feature is not described in E1/T1/J1 standards. Generation of
an interrupt when loop up or down code is detected can be selected
by demasking (register IMR6). Setting both, SILS and LILS to ´1´ is
forbidden.
0B
automatic switching of local loop (“on framer side”) is disabled
(default).
automatic switching of local loop (“on framer side”) by In-band loop
codes detected from the framer side is enabled.
1B
LILS
0
rw
Line In-Band Loop Switching (Remote Loop)
This bit controls if automatic switching of the remote loop will be done by
In-Band loop codes from the line side, see Chapter 3.11.2.
Note: Generation of an interrupt when loop up or down code is detected
can be selected by demasking (register IMR6). Setting both, SILS
and LILS to ´1´ is forbidden.
0B
automatic switching of remote loop (“on line side”) is disabled
(default).
automatic switching of remote loop (“on line side”) by In-band loop
codes detected from the line side is enabled if local loop is not
activated by LIM0.LL = ´1´.
1B
Data Sheet
188
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLIU Mode Register 3
LIU Mode Register 3
LIM3
Offset
xxE2H
Reset Value
00H
LIU Mode Register 3
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
'55
UZ
'5;
UZ
Field
Bits
Type
Description
DRR
1
rw
Dual-Rail mode on digital side, receive direction
0B
1B
single rail mode on framer receive side.
dual rail mode on framer receive side.
DRX
0
rw
Dual-Rail mode on digital side, transmit direction
0B
1B
single rail mode on framer transmit side.
dual rail mode on framer transmit side.
Data Sheet
189
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionWander Configuration Register
Wander Configuration Register
This register is only valid if register bit GPC6.WAN_IMP is set. See Chapter 3.6.1. for further description.
WCON
Offset
xxE8H
Reset Value
00H
Wander Configuration Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
:$1'
UZ
Field
WAND
Bits
7:0
Type
rw
Description
Wander Improovement
This bitfield configures the internal PLLs for output wander improvement
if register bit GPC6.WAN_IMP is set.The value must be set to ´03H´.
Data Sheet
190
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionWander Configuration Register
4.2
Detailed Status Register Description
Table 51
Registers Overview
Register Short Name
VSTR
CIS
GIS2
DSTR
RBD
RES
LSR0
LSR1
LSR3
Register Long Name
Version Status Register
Channel Interrupt Status Register
Global Interrupt Status 2
Device Status Register
Receive Buffer Delay
Receive Equalizer Status
Line Status Register 0
Line Status Register 1
Line Status Register 3
Offset Address Page Number
004AH
006FH
00ADH
00E7H
xx49H
xx4BH
xx4CH
xx4DH
xx4EH
xx4FH
xx52H
xx53H
xx58H
xx59H
xx69H
xx6AH
xx6BH
xx6CH
xx6EH
xxABH
xxACH
xxD8H
xxDAH
xxFEH
195
212
215
218
194
196
197
198
200
202
203
204
205
206
207
208
209
210
211
213
214
216
217
219
LSR2
Line Status Register 2
CVCL
CVCH
BECL
BECH
ISR1
ISR2
ISR3
ISR4
GIS
MFPI
ISR6
ISR7
PRBSSTA
CLKSTAT
Code Violation Counter Lower Byte
Code Violation Counter Higher Byte
PRBS Bit Error Counter Lower Bytes
PRBS Bit Error Counter Higher Bytes
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Status Register 3
Interrupt Status Register 4
Global Interrupt Status Register
Multi Function Port Input Register
Interrupt Status Register 6
Interrupt Status Register 7
PRBS Status Register
Clock Status Register
The register is addressed wordwise.
Data Sheet
191
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionWander Configuration Register
Table 52
Mode
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
Basic Access Types
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read/write
virtual
rwv
Physically, there is no new register in Register is read and writable by SW (same
the generated register file. The real
readable and writable register resides
in the attached hardware.
as rw type register)
read
r
Register is written by HW (register
Value written by SW is ignored by HW; that
between input and output -> one cycle is, SW may write any value to this field
delay)
Same as r type register
Physically, there is no new register in Value written by SW is ignored by HW; that
without affecting HW behavior
Same as r type register
read only
read virtual
ro
rv
the generated register file. The real
readable register resides in the
attached hardware.
is, SW may write any value to this field
without affecting HW behavior (same as r
type register)
write
w
Register is written by software and
affects hardware behavior with every
write by software.
Register is writable by SW. When read, the
register does not return the value that has
been written previously, but some constant
value instead.
write virtual
wv
rwh
Physically, there is no new register in Register is writable by SW (same as w type
the generated register file. The real
writable register resides in the attached
hardware.
register)
read/write
hardware
affected
Register can be modified by hardware Register can be modified by HW and SW,
and software at the same time. A but the priority SW versus HW has to be
priority scheme decides, how the value specified.
changes with simultaneous writes by
hardware and software.
SW can read the register.
Special Access Types
Latch high,
self clearing
lhsc
Latch high signal at high level, clear on SW can read the register
read
Latch low,
self clearing
llsc
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
lhmk
llmk
ihsc
ilsc
Latch high signal at high level, register SW can read the register, with write mask
mask clearing
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Latch high signal at low-level, register SW can read the register, with write mask
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
the register can be cleared (1 clears)
SW can read the register
Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
Interrupt low,
mask clearing
ihmk
ilmk
Differentiate the input signal (high-
SW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Data Sheet
192
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionWander Configuration Register
Table 52
Mode
Registers Access Types (cont’d)
Symbol Description Hardware (HW)
Description Software (SW)
Interrupt enable ien
Enables the interrupt source for
SW can read and write this register
Register is read and writable by SW
Writing to the register generates a strobe
register
interrupt generation
latch_on_reset lor
rw register, value is latched after first
clock cycle after reset
Read/write
self clearing
rwsc
Register is used as input for the HW,
the register will be cleared due to a HW signal for the HW (1 pdi clock cycle)
mechanism.
Register is read and writable by SW.
Data Sheet
193
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionReceive Buffer Delay
4.2.1
Status Registers
Receive Buffer Delay
RBD
Offset
xx49H
Reset Value
00H
Receive Buffer Delay
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
5%'
U
Field
RBD
Bits
5:0
Type
r
Description
Receive Elastic Buffer Delay
These bits informs the user about the current delay (in time slots) through
the receive elastic buffer. The delay is updated every 512 or 256 bits
(DIC1.RBS(1:0)). Before reading this register the user has to set bit
DEC.DRBD in order to halt the current value of this register. After reading
RBD updating of this register is enabled. Not valid if the receive buffer is
bypassed.
000000B Delay < 1 time slot
...B
111111B Delay > 63 time slot
Data Sheet
194
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionVersion Status Register
Version Status Register
VSTR
Offset
004AH
Reset Value
Version Status Register
H
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
9675
U
Field
VSTR
Bits
7:0
Type
r
Description
Version Number of Chip
Status information depends on the setting of GPC6.COMP_DIS:
00000101B for COMP_DIS = ´0´
00100000B for COMP_DIS = ´1´
Data Sheet
195
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionReceive Equalizer Status
Receive Equalizer Status
RES
Offset
xx4BH
Reset Value
00H
Receive Equalizer Status
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
(9
5(6
U
U
Field
Bits
Type
Description
EV
7:6
r
Equalizer Status Valid
These bits informs the user about the current state of the receive
equalization network.
00B Equalizer status not valid, still adapting
01B Equalizer status valid
10B Equalizer status not valid
11B Equalizer status valid but high noise floor
RES
5:0
r
Receive Equalizer Status
The current line attenuation status in steps of about 1.7 dB for E1 and 1.4
dB for T1/J1 mode are displayed in these bits. Only valid if bits EV(1:0) =
´01b´. Accuracy: ± 2 digits, based on temperature influence and noise
amplitude variations.
00000B
...B
11001B
Minimum attenuation: 0 dB
Maximum attenuation: -43 dB (E1), -36 dB (T1/J1)
Data Sheet
196
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Status Register 0
Line Status Register 0
LSR0
Offset
xx4CH
Reset Value
00H
Line Status Register 0
ꢀ
/26
U
ꢁ
$,6
U
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
Field
LOS
Bits
7
Type
r
Description
Loss-of-Signal
•
Detection: This bit is set when the incoming signal has “no transitions”
(analog interface) or logical zeros (digital interface) in a time interval
of T consecutive pulses, where T is programmable by register PCD.
Total account of consecutive pulses: 16 ≤ T ≤ 4096. Analog interface:
The receive signal level where “no transition” is declared is defined by
the programmed value of LIM1.RIL(2:0).
Recovery: Analog interface: The bit is reset in short-haul mode when
the incoming signal has transitions with signal levels greater than the
programmed receive input level (LIM1.RIL(2:0)) for at least M pulse
periods defined by register PCR in the PCD time interval. In long-haul
mode additionally bit RES.6 must be set for at least 250 µs. Digital
interface: The bit is reset when the incoming data stream contains at
least M ones defined by register PCR in the PCD time interval. With
the rising edge of this bit an interrupt status bit (ISR2.LOS) is set. The
bit is also set during alarm simulation and reset, if MR0.SIM is cleared
and no alarm condition exists.
•
AIS
6
r
Alarm Indication Signal
The function of this bit is determined by MR0.ALM.
•
MR0.ALM = ´0´: This bit is set when two or less zeros in the received
bit stream are detected in a time interval of 250 ms and the
QuadLIUTM is in asynchronous state (LSR0.LFA = ´1´). The bit is reset
when no alarm condition is detected (according to ETSI standard).
MR0.ALM = ´1´: This bit is set when the incoming signal has two or
less Zeros in each of two consecutive double frame period (512 bits).
This bit is cleared when each of two consecutive doubleframe periods
contain three or more zeros or when the frame alignment signal FAS
has been found. (ITU-T G.775)
•
The bit is also set during alarm simulation and reset if MR0.SIM is cleared
and no alarm condition exists.With the rising edge of this bit an interrupt
status bit (ISR2.AIS) is set.
Data Sheet
197
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Status Register 1
Line Status Register 1
LSR1
Offset
xx4DH
Reset Value
xxH
Line Status Register 1
ꢀ
(;='
U
ꢁ
3'(1
U
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
;/6
U
ꢇ
;/2
U
5HV
//%''
//%$'
5HV
U
U
Field
Bits
Type
Description
EXZD
7
r
Excessive Zeros Detected
Significant only, if excessive zero detection has been enabled
(MR0.EXZE = ´1´). Set after detection of more than 3 (HDB3 code) or 15
(AMI code) contiguous zeros in the received data stream.This bit is
cleared on read.
PDEN
6
r
Pulse-Density Violation Detected
The pulse-density of the received data stream is below the requirement
defined by ANSI T1. 403 or more than 14 consecutive zeros are detected.
With the violation of the pulse-density this bit is set and remains active
until the pulse-density requirement is fulfilled for 23 consecutive "1"-
pulses. Additionally an interrupt status ISR0.PDEN is generated with the
rising edge of PDEN.
LLBDD
LLBAD
4
3
r
r
Line Loop-Back Deactivation Signal Detected, only valid in T1 mode
In E1 mode the equivalent bit is LSR2.LLBDD.
This bit is set in case of the LLB deactivate signal is detected and then
received over a period of more than 33,16 ms with a bit error rate less
than 10-2. The bit remains set as long as the bit error rate does not exceed
10-2. If framing is aligned, the first bit position of any frame is not taken
into account for the error rate calculation.Any change of this bit causes an
LLBSC interrupt.
Line Loop-Back Activation Signal Detected, only valid in T1 mode
In E1 mode the equivalent bit is LSR2.LLBAD.
Depending on bit LCR1.EPRM the source of this status bit changed.
•
LCR1.EPRM = ´0´: This bit is set in case of the LLB activate signal is
detected and then received over a period of more than 33,16 ms with
a bit error rate less than 10-2. The bit remains set as long as the bit
error rate does not exceed 10-2. If framing is aligned, the first bit
position of any frame is not taken into account for the error rate
calculation. Any change of this bit causes an LLBSC interrupt.
LCR1.EPRM = ´1´: The current status of the PRBS synchronizer is
indicated in this bit. It is set high if the synchronous state is reached
even in the presence of a bit error rate of up to 10-3. A data stream
containing all zeros or all ones with/without framing bits is also a valid
pseudo-random binary sequence.
•
Data Sheet
198
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Status Register 1
Field
Bits
Type
Description
XLS
1
r
Transmit Line Short
See Chapter 3.9.7. Significant only if the ternary line interface is selected
by LIM1.DRS = ´0´.
0B
1B
Normal operation. No short is detected.
The XL1 and XL2 are shortened for at least 3 pulses. As a reaction
of the short the pins XL1 and XL2 are automatically forced into a
high-impedance state if bit XPM2.DAXLT is reset. After 128
consecutive pulse periods the outputs XL1/2 are activated again
and the internal transmit current limiter is checked. If a short
between XL1/2 is still further active the outputs XL1/2 are in high-
impedance state again. When the short disappears pins XL1/2 are
activated automatically and this bit is reset. With any change of this
bit an interrupt ISR1.XLSC is generated. In case of XPM2.XLT is
set this bit is frozen.
XLO
0
r
Transmit Line Open
See also Chapter 3.9.7.
0B
1B
Normal operation
This bit is set if at least 32 consecutive zeros were sent on pins
XL1/XL2 or XDOP/XDON. This bit is reset with the first transmitted
pulse. With the rising edge of this bit an interrupt ISR1.XLSC is set.
In case of XPM2.XLT is set this bit is frozen.
Data Sheet
199
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Status Register 3
Line Status Register 3
LSR3
Offset
xx4EH
Reset Value
xxH
Line Status Register 3
ꢀ
ꢁ
(6&
U
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
Field
ESC
Bits
7:5
Type
r
Description
Error Simulation Counter, T1 only
This three-bit counter is incremented by setting bit MR0.SIM. The state of
the counter determines the function to be tested. For complete checking
of the alarm indications, eight simulation steps are necessary (LSR3.ESC
= ´000b´ after a complete simulation).
Table 53
Alarm Simulation States
Tested Alarms ESC(2:0) =
0
1
2
3
4
5
6
7
LFA
LMFA
x
x
x
x
RRA (bit2 = 0)
RRA (S-bit frame 12)
RRA (DL-pattern)
LOS1)
x
x
x
x
x
x
x
x
x
x
x
x
EBC2) (F12,F72)
EBC2) (only ESF)
AIS1)
(x)
(x)
x
x
x
x
x
FEC2)
CVC
CEC (only ESF)
RSP
(x)
x
x
x
x
x
x
RSN
x
XSP
x
x
XSN
x
x
BEC1)
x
x
COEC
x
1) Only active during FMR0.SIM = 1
2) FEC is counting +2 while EBC is counting +1 if the framer is in synchronous state; if asynchronous in state 2 but
synchronous in state 6, counters are incremented during state 6
Data Sheet
200
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register Description
Some of these alarm indications are simulated only if the QuadLIUTM is configured in the appropriate mode. At
simulation steps 0, 3, 4, and 7 pending status flags are reset automatically and clearing of the error counters and
interrupt status registers ISR(7:0) should be done. Incrementing the simulation counter should not be done at time
intervals shorter than 1.5 ms (F4, F12, F72) or 3 ms (ESF). Otherwise, reactions of initiated simulations might
occur at later steps. Control bit FMR0.SIM has to be held stable at high or low level for at least one receive clock
period before changing it again.
Data Sheet
201
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionLine Status Register 2
Line Status Register 2
LSR2
Offset
xx4FH
Reset Value
xxH
Line Status Register 2
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
//%''
//%$'
5HV
U
U
Field
Bits
Type
Description
LLBDD
4
r
Line Loop-Back Deactivation Signal Detected
Only valid in E1 mode
In T1/J1 mode the equivalent bit is LSR1.LLBDD.
This bit is set in case of the LLB deactivate signal is detected and then
received over a period of more than 25 ms with a bit error rate less than
10-2. The bit remains set as long as the bit error rate does not exceed 10-2.
If framing is aligned, the time slot 0 is not taken into account for the error
rate calculation.Any change of this bit causes an LLBSC interrupt.
LLBAD
3
r
Line Loop-Back Activation Signal Detected
Only valid in E1 mode
In T1/J1 mode the equivalent bit is LSR1.LLBAD.
Depending on bit LCR1.EPRM the source of this status bit changed.
•
LCR1.EPRM = ´0´: This bit is set in case of the LLB activate signal is
detected and then received over a period of more than 25 ms with a
bit error rate less than 10-2. The bit remains set as long as the bit error
rate does not exceed 10-2. If framing is aligned, the time slot 0 is not
taken into account for the error rate calculation. Any change of this bit
causes an LLBSC interrupt.
LCR1.EPRM = ´1´: The current status of the PRBS synchronizer is
indicated in this bit. It is set high if the synchronous state is reached
even in the presence of a bit error rate of 10-1. A data stream
containing all zeros or all ones with/without framing bits is also a valid
pseudo-random binary sequence.
•
Data Sheet
202
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionCode Violation Counter Lower Byte
Code Violation Counter Lower Byte
CVCL
Offset
xx52H
Reset Value
00H
Code Violation Counter Lower Byte
ꢀ
&9ꢀ
U
ꢁ
&9ꢁ
U
ꢂ
&9ꢂ
U
ꢃ
&9ꢃ
U
ꢄ
&9ꢄ
U
ꢅ
&9ꢅ
U
ꢆ
&9ꢆ
U
ꢇ
&9ꢇ
U
Field
Bits
Type
Description
CV7
CV6
CV5
CV4
CV3
CV2
CV1
CV0
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
Code Violations
If the HDB3 or the CMI code with HDB3-precoding is selected, the 16-bit
counter is incremented when violations of the HDB3 code are detected.
The error detection mode is determined by programming the bit
MR0.EXTD. If simple AMI coding is enabled (MR0.RC(1:0) = ´01b´) all
bipolar violations are counted. The error counter does not roll over.During
alarm simulation, the counter is incremented every four bits received up
to its saturation. Clearing and updating the counter is done according to
bit MR1.ECM. If this bit is reset the error counter is permanently updated
in the buffer. For correct read access of the error counter bit DEC.DCVC
has to be set. With the rising edge of this bit updating the buffer is stopped
and the error counter is reset. Bit DEC.DCVC is reset automatically with
reading the error counter high byte. If MR1.ECM is set every second
(interrupt ISR3.SEC) the error counter is latched and then automatically
reset. The latched error counter state should be read within the next
second.
Data Sheet
203
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionCode Violation Counter Higher Byte
Code Violation Counter Higher Byte
CVCH
Offset
xx53H
Reset Value
00H
Code Violation Counter Higher Byte
ꢀ
&9ꢀꢁ
U
ꢁ
&9ꢀꢂ
U
ꢂ
&9ꢀꢃ
U
ꢃ
&9ꢀꢄ
U
ꢄ
&9ꢀꢀ
U
ꢅ
&9ꢀꢅ
U
ꢆ
&9ꢆ
U
ꢇ
&9ꢇ
U
Field
Bits
Type
Description
CV15
CV14
CV13
CV12
CV11
CV10
CV9
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
Code Violations
If the HDB3 or the CMI code with HDB3-precoding is selected, the 16-bit
counter is incremented when violations of the HDB3 code are detected.
The error detection mode is determined by programming the bit
MR0.EXTD. If simple AMI coding is enabled (MR0.RC(1:0) = ´01b´) all
bipolar violations are counted. The error counter does not roll over.During
alarm simulation, the counter is incremented every four bits received up
to its saturation. Clearing and updating the counter is done according to
bit MR1.ECM. If this bit is reset the error counter is permanently updated
in the buffer. For correct read access of the error counter bit DEC.DCVC
has to be set. With the rising edge of this bit updating the buffer is stopped
and the error counter is reset. Bit DEC.DCVC is reset automatically with
reading the error counter high byte. If MR1.ECM is set every second
(interrupt ISR3.SEC) the error counter is latched and then automatically
reset. The latched error counter state should be read within the next
second.
CV8
Data Sheet
204
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPRBS Bit Error Counter Lower Bytes
PRBS Bit Error Counter Lower Bytes
BECL
Offset
xx58H
Reset Value
00H
PRBS Bit Error Counter Lower Bytes
ꢀ
%(&ꢀ
U
ꢁ
%(&ꢁ
U
ꢂ
%(&ꢂ
U
ꢃ
%(&ꢃ
U
ꢄ
%(&ꢄ
U
ꢅ
%(&ꢅ
U
ꢆ
%(&ꢆ
U
ꢇ
%(&ꢇ
U
Field
Bits
Type
Description
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
PRBS Bit Error Counter
If the PRBS monitor is enabled by LCR1.EPRM = ´1´ this 16-bit counter
is incremented with every received PRBS bit error in the PRBS
synchronous state LSR1.LLBAD = ´1´.
The error counter does not roll over.During alarm simulation, the counter
is incremented continuously with every second received bit. Clearing and
updating the counter is done according to bit MR1.ECM.If this bit is reset
the error counter is permanently updated in the buffer. For correct read
access of the PRBS bit error counter bit DEC.DBEC has to be set. With
the rising edge of this bit updating the buffer is stopped and the error
counter is reset.
Bit DEC.DBEC is automatically reset with reading the error counter high
byte. If MR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error counter
state should be read within the next second.
Data Sheet
205
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPRBS Bit Error Counter Higher Bytes
PRBS Bit Error Counter Higher Bytes
BECH
Offset
xx59H
Reset Value
00H
PRBS Bit Error Counter Higher Bytes
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
%(&ꢀꢀ
U
ꢅ
ꢆ
%(&ꢆ
U
ꢇ
%(&ꢇ
U
%(&ꢀꢁ
%(&ꢀꢂ
%(&ꢀꢃ
%(&ꢀꢄ
%(&ꢀꢅ
U
U
U
U
U
Field
Bits
7
6
5
4
3
2
1
0
Type
Description
PRBS Bit Error Counter
If the PRBS monitor is enabled by LCR1.EPRM = ´1´ this 16-bit counter
is incremented with every received PRBS bit error in the PRBS
synchronous state LSR1.LLBAD = ´1´.
The error counter does not roll over.During alarm simulation, the counter
is incremented continuously with every second received bit. Clearing and
updating the counter is done according to bit MR1.ECM.If this bit is reset
the error counter is permanently updated in the buffer. For correct read
access of the PRBS bit error counter bit DEC.DBEC has to be set. With
the rising edge of this bit updating the buffer is stopped and the error
counter is reset.
BEC15
BEC14
BEC13
BEC12
BEC11
BEC10
BEC9
r
r
r
r
r
r
r
r
BEC8
Bit DEC.DBEC is automatically reset with reading the error counter high
byte. If MR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error counter
state should be read within the next second.
Data Sheet
206
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Status Register 1
Interrupt Status Register 1
All bits are reset when ISR1 is read. If bit GCR.VIS is set, interrupt statuses in ISR1 are flagged although they are
masked by register IMR1. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see Chapter 3.5.3.
ISR1
Offset
xx69H
Reset Value
00H
Interrupt Status Register 1
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
//%6&
UVF
5HV
;/6&
UVF
5HV
Field
LLBSC
Bits
7
Type
rsc
Description
Line Loop-Back Status Change, E1 only
In T1/J1 mode this bit is not valid and ISR3.LLBSC is used instead.
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
•
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively, is detected over a period of 25 ms with
a bit error rate less than 10-2. The LLBSC bit is also set, if the current
detection status is left, i.e., if the bit error rate exceeds 10-2. The actual
detection status can be read from the LSR2.LLBAD / LSR2.LLBDD in
E1 or LSR1.LLBAD / LSR1.LLBDD in T1/J1 mode, respectively.
PRBS Status Change LCR1.EPRM = ´1´: With any change of state of
the PRBS synchronizer this bit is set. The current status of the PRBS
synchronizer is indicated in LSR2.LLBAD (E1) or LSR1.LLBAD
(T1/J1).
•
XLSC
1
rsc
Transmit Line Status Change
XLSC is set with the rising edge of the bit LSR1.XLO or with any change
of bit LSR1.XLS.
The actual status of the transmit line monitor can be read from the
LSR1.XLS and LSR1.XLO.
Data Sheet
207
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Status Register 2
Interrupt Status Register 2
All bits are reset when ISR2 is read. If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are
masked by register IMR2. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS. See Chapter 3.5.3
ISR2
Offset
xx6AH
Reset Value
00H
Interrupt Status Register 2
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
$,6
U
ꢅ
/26
U
ꢆ
ꢇ
5HV
5HV
Field
Bits
Type
Description
AIS
3
r
Alarm Indication Signal (Blue Alarm)
This bit is set when an alarm indication signal is detected and bit
LSR0.AIS is set. If GCR.SCI is set high this interrupt status bit is activated
with every change of state of LSR0.AIS.It is set during alarm simulation.
LOS
2
r
Loss-of-Signal (Red Alarm)
This bit is set when a loss-of-signal alarm is detected in the received data
stream and LSR0.LOS is set. If GCR.SCI is set high this interrupt status
bit is activated with every change of state of LSR0.LOS. It is set during
alarm simulation.
Data Sheet
208
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Status Register 3
Interrupt Status Register 3
All bits are reset when ISR3 is read. If bit GCR.VIS is set, interrupt statuses in ISR3 are flagged although they are
masked by register IMR3. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see Chapter 3.5.3.
ISR3
Offset
xx6BH
Reset Value
00H
Interrupt Status Register 3
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
6(&
UVF
5HV
//%6&
UVF
5HV
561
UVF
563
UFV
Field
SEC
Bits
6
Type
rsc
Description
Second Timer
The internal one-second timer has expired. The timer is derived from
clock RCLK or external pin SEC/FSC.
LLBSC
3
rsc
Line Loop-Back Status Change, T1/J1 only
In E1 mode this bit is not valid and ISR1.LLBSC is used instead.
Depending on bit LCR1.EPRM the source of this interrupt status
changed:
•
LCR1.EPRM = 0: This bit is set, if the LLB activate signal or the LLB
deactivate signal, respectively, is detected over a period of 25 ms with
a bit error rate less than 10-2. The LLBSC bit is also set, if the current
detection status is left, i.e., if the bit error rate exceeds 10-2. The actual
detection status can be read from the LSR2.LLBAD / LSR2.LLBDD in
E1 or LSR1.LLBAD / LSR1.LLBDD in T1/J1 mode, respectively.
PRBS Status Change LCR1.EPRM = ´1´: With any change of state of
the PRBS synchronizer this bit is set. The current status of the PRBS
synchronizer is indicated in LSR2.LLBAD (E1) or LSR1.LLBAD
(T1/J1).
•
RSN
RSP
1
0
rsc
rcs
Receive Slip Negative
The frequency of the receive route clock is greater than the frequency of
the receive system interface working clock based on 2.048 MHz. A frame
is skipped. It is set during alarm simulation. See Chapter 3.7.9.
Receive Slip Positive
The frequency of the receive route clock is less than the frequency of the
receive system interface working clock based on 2.048 MHz. A frame is
repeated. It is set during alarm simulation. See Chapter 3.7.9.
Data Sheet
209
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Status Register 4
Interrupt Status Register 4
All bits are reset when ISR4 is read. If bit GCR.VIS is set, interrupt statuses in ISR4 are flagged although they are
masked by register IMR4. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see Chapter 3.5.3.
ISR4
Offset
xx6CH
Reset Value
00H
Interrupt Status Register 4
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
;63
UVF
;61
UVF
5HV
Field
Bits
Type
Description
XSP
7
rsc
Transmit Slip Positive
The frequency of the transmit clock is less than the frequency of the
transmit system interface working clock based on 2.048 MHz. A frame is
repeated. After a slip has performed writing of register XC1 is not
necessary.
XSN
6
rsc
Transmit Slip Negative
The frequency of the transmit clock is greater than the frequency of the
transmit system interface working clock based on 2.048 MHz. A frame is
skipped. After a slip has performed writing of register XC1 is not
necessary.
Data Sheet
210
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Interrupt Status Register
Global Interrupt Status Register
This status register points to pending interrupts sourced by ISR(1:4) and ISR(6:7), see Chapter 3.5.3.
GIS
Offset
xx6EH
Reset Value
00H
Global Interrupt Status Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
,65ꢀ
UVF
,65ꢁ
UVF
,65ꢂ
UVF
,65ꢃ
UVF
,65ꢄ
UVF
,65ꢅ
UVF
,65ꢆ
UVF
,65ꢇ
UVF
Field
Bits
Type
Description
ISR7
7
rsc
Interrupt Status Register 7 Pointer
0B
1B
no interrupt is pending in ISR6.
at least one interrupt is pending in ISR6.
ISR6
6
rsc
Interrupt Status Register 6 Pointer
0B
1B
no interrupt is pending in ISR6.
at least one interrupt is pending in ISR6.
ISR5
ISR4
5
4
rsc
rsc
Interrupt Status Register 5 Pointer
Always ´0´, because no ISR5 exists
Interrupt Status Register 4 Pointer
0B
1B
no interrupt is pending in ISR4.
at least one interrupt is pending in ISR4.
ISR3
ISR2
ISR1
ISR0
3
2
1
0
rsc
rsc
rsc
rsc
Interrupt Status Register 3 Pointer
0B
1B
no interrupt is pending in ISR3.
at least one interrupt is pending in ISR3.
Interrupt Status Register 2Pointer
0B
1B
no interrupt is pending in ISR2.
at least one interrupt is pending in ISR2.
Interrupt Status Register 1 Pointer
0B
1B
no interrupt is pending in ISR1.
at least one interrupt is pending in ISR1.
Interrupt Status Register 0 Pointer
Always ´0´, because no ISR0 exists.
Data Sheet
211
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionChannel Interrupt Status Register
Channel Interrupt Status Register
This status register points to pending interrupts of channels 1to 4, see Chapter 3.5.3.
CIS
Offset
006FH
Reset Value
00H
Channel Interrupt Status Register
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
3///
UVF
5HV
*,6ꢀ
UVF
*,6ꢁ
UVF
*,6ꢂ
UVF
*,6ꢃ
UVF
Field
Bits
Type
Description
PLLL
7
rsc
PLL Lock Status
This bit shows the lock status of the internal PLL.
Note: PLLL has the same value as PLLLS in register GIS2 (which is used
for GPC6.COMP_DIS = 1B).
0B
1B
PLL is unlocked.
PLL is locked.
GIS4
GIS3
GIS2
GIS1
3
2
1
0
rsc
rsc
rsc
rsc
Global Interrupt Status of Channel 4
0B
1B
no interrupt is pending on channel 4.
at least one interrupt is pending on channel 4, read GIS of channel
4 for more information.
Global Interrupt Status of Channel 3
0B
1B
no interrupt is pending on channel 3.
at least one interrupt is pending on channel 3, read GIS of channel
3 for more information.
Global Interrupt Status of Channel 2
0B
1B
no interrupt is pending on channel 2.
at least one interrupt is pending on channel 2, read GIS of channel
2 for more information.
Global Interrupt Status of Channel 1
0B
1B
no interrupt is pending on channel 1.
at least one interrupt is pending on channel 1, read GIS of channel
1 for more information.
Data Sheet
212
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionMulti Function Port Input Register
Multi Function Port Input Register
This register always reflects the state of the multi function ports, see Chapter 3.12. If used as an input, the
according port should be switched to general purpose input mode. If not, the programmed output signal can be
monitored through this register (see registers PC1 to PC3).
MFPI
Offset
xxABH
Reset Value
xxH
Multi Function Port Input Register
ꢀ
ꢁ
53&
U
ꢂ
53%
U
ꢃ
53$
U
ꢄ
ꢅ
ꢆ
;3%
U
ꢇ
;3$
U
5HV
5HV
Field
Bits
Type
Description
RPC
RPB
RPA
XPB
XPA
6
5
4
1
0
r
r
r
r
r
RPC Input Level
0B
1B
Low level on pin RPC.
High level on pin RPC.
RPB Input Level
0B
1B
Low level on pin RPB.
High level on pin RPB.
RPA Input Level
0B
1B
Low level on pin RPA.
High level on pin RPA.
XPB Input Level
0B
1B
Low level on pin XPB.
High level on pin XPB.
XPA Input Level
0B
1B
Low level on pin XPA.
High level on pin XPA.
Data Sheet
213
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Status Register 6
Interrupt Status Register 6
ISR6
Offset
xxACH
Reset Value
00H
Interrupt Status Register 6
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
6,/68
UVF
6,/6'
UVF
/,/68
UVF
/,/6'
UVF
Field
Bits
Type
Description
SILSU
SILSD
LILSU
3
2
1
rsc
rsc
rsc
Framer (System) In-Band Loop Switching Up detected
See Chapter 3.11.2.
System loop up code detected and payload loop is switched on if
ALS.SILS is set.
Framer (System) In-Band Loop Switching Down detected
See Chapter 3.11.2.
System loop down code detected and payload loop is switched off if
ALS.SILS is set.
Line In-Band Loop Switching Up Interrupt
See Chapter 3.11.2.
0B
1B
no line loop up code detected.
line loop up code detected and line loop is switched on if ALS.LILS
is set.
LILSD
0
rsc
Line In-Band Loop Switching Down Interrupt
See Chapter 3.11.2.
0B
1B
no line loop down code detected.
line loop down code detected and line loop is switched off if
ALS.LILS is set.
Data Sheet
214
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionGlobal Interrupt Status 2
Global Interrupt Status 2
Interrupt status register for the PLL of the master clocking unit.
GIS2
Offset
00ADH
Reset Value
00H
Global Interrupt Status 2
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
3///6
U
ꢇ
5HV
3///&
UVF
Field
PLLLS
Bits
1
Type
r
Description
PLL Locked Status Information
Note: PLLLS is only a status bit, not an interrupt status bit, so type is r and
not rsc. This bit is valid independent on value of COMP. For COMP
= ´0´ this bit must be used instead of bit 7 of register CIS which has
then the function GIS8.
0B
1B
PLL is unlocked.
PLL is locked
PLLLC
0
rsc
PLL Locked Status Change
0B
1B
no change of PLL lock status since last read of this register.
PLL lock status has changed since last read. Status information is
available in bit PLLLS.
Data Sheet
215
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionInterrupt Status Register 7
Interrupt Status Register 7
All bits are reset when ISR7 is read. If bit GCR.VIS is set, interrupt statuses in ISR7 are flagged although they are
masked by register IMR7. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS, see Chapter 3.5.3.
ISR7
Offset
xxD8H
Reset Value
00H
Interrupt Status Register 7
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
5HV
;&/.66ꢀ
;&/.66ꢁ
UVF
5HV
UVF
Field
Bits
Type
Description
XCLKSS1
4
rsc
XCLK Source Switched 1
See Chapter 3.9.3. Shows if an automatically switching of the DCO-X
reference between TCLK and FCLKX was performed. If automatically
switching is not enabled (CMR6.ATCS = ´0´), this bit is always ´0´. Note
that the status of TCLK is shown independent on CMR6.ATC in
CLKSTAT.TCLKLOS.
0B
1B
DCO-X reference not switched.
DCO-X reference has switched between TCLK and FCLKX. The
XCLK is always sourced by the DCO-X output.
XCLKSS0
3
rsc
XCLK Source Switched 0
See Chapter 3.9.3. Shows if an automatically switching of the XCLK
source between TCLK and DCO-X output was performed. If automatically
switching is not enabled (CMR6.ATCS = ´0´), this bit is always ´0´. Note
that the status of TCLK is shown independent on CMR6.ATC in
CLKSTAT.TCLKLOS.
0B
1B
XCLK source not switched.
XCLK source has switched automatically from TCLK to DCO-X
output in case of TCLK loss or automatically switched back from
DCO-X output to TCLK in case that TCLK is active again. The
DCO-X is always sourced by FCLKX.
Data Sheet
216
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionPRBS Status Register
PRBS Status Register
PRBSSTA
PRBS Status Register
Offset
xxDAH
Reset Value
0xH
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
356
U
ꢇ
5HV
Field
PRS
Bits
2:0
Type
r
Description
PRBS Status Information
Note: Every change of the bits PRS sets the interrupt bit ISR1.LLBSC if
register bit LCR1.EPRM is set. No pattern is also detected if signal
“alarm simulation” is active. Detection of all_zero or all_ones is
done over 12, 16, 21 or 24 consecutive bits, dependent on the
choosed PRBS polynomial (11, 15, 20 or 23). Because every bit
error in the PRBS increments the bit error counter BEC, no special
status information like “PRBS detected with errors” is given here
000B no pattern detected.
001B reserved.
010B PRBS pattern detected.
011B inverted PRBS pattern detected.
100B reserved.
101B reserved.
110B all-zero pattern detected.
111B all-ones pattern detected.
Data Sheet
217
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionDevice Status Register
Device Status Register
.
DSTR
Device Status Register
Offset
00E7H
Reset Value
0xH
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
&203
U
5HV
Field
Bits
Type
Description
COMP
0
r
COMPatibility Status
0B
1B
GPC6.COMP_DIS = ´1´, generic mode is selected.
GPC6.COMP_DIS = ´0´, QuadFALC® v2.1 compatibility mode is
selected.
Data Sheet
218
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Register DescriptionClock Status Register
Clock Status Register
The bits show the current status of the input clocks TCLK and FCLKX.
CLKSTAT
Clock Status Register
Offset
xxFEH
Reset Value
xxH
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
)&/.;/2
6
5HV
7&/./26
5HV
U
U
Field
Bits
Type
Description
TCLKLOS
4
r
Loss of TCLK
Status of TCLK.
Note: See Chapter 3.9.3 for more detail.
0B
1B
TCLK is active.
TCLK is lossed.
FCLKXLOS
3
r
Loss of FCLKX
Status of FCLKX.
Note: See Chapter 3.9.3 for more detail.
0B
1B
FCLKX is active.
FCLKX is lossed.
Data Sheet
219
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Package Outlines
5
Package Outlines
Figure 46 shows the Ball Grid Array Packages.
13 x 1 = 13
A13
B14
A2
Index Marking
B1
N1
1
P2
0.25
C
160x
±0.1
ø0.6
0.2
C
M
ø0.25
C A B
C
M
ø0.1
A
Index Marking
±0.1
15
B
GPA01100
Figure 46 P/PG-LBGA-160-1 (Plastic Green Low Profile Ball Grid Array Package)
Dimensions in mm.
Data Sheet
220
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Package Outlines
Figure 47 shows the Flat Thin Pack package.
H
0.5
±0.15
0.6
17.5
C
2)
0.08
±0.05
0.22
M
0.08 A-B D C 144x
22
0.2 A-B D 144x
0.2 A-B D H 4x
201)
D
B
A
144
Index Marking
1
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
Figure 47 PG-TQFP-144-17 (Plastic Thin Quad Flat Package)
Dimensions in mm
Data Sheet
221
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
6
Electrical Characteristics
In Table 54 the absolute maximum ratings of the QuadLIUTM are listed.
Table 54
Absolute Maximum Ratings
Symbol
Parameter
Values
Typ.
Unit
Note / Test
Condition
Min.
Max.
Ambient temperature under
bias
TA
-40
–
85
°C
–
Storage temperature
Tstg
-65
–
–
–
125
225
°C
°C
–
Moisture Level 3 temperature TML3
According to IPS
J-STD 020
245
°C
According to Infineon
internal standard
IC supply voltage (pads, digital) VDD
IC supply voltage (core, digital) VDDC
-0.5
-0.5
-0.4
3.3
1.8
–
4.5
2.4
4.5
V
V
V
–
–
–
IC supply voltage receive
(analog)
VDDR
IC supply voltage transmit
(analog)
VDDX
-0.4
-0.8
-0.4
–
–
–
–
–
–
4.5
V
V
V
V
–
Receiver input signal with
respect to ground
VRLmax
4.5
RL1, RL2
Voltage on any pin with respect Vmax
to ground
ESD robustness1) HBM:
1.5 kΩ, 100 pF
4.5
Except RL1, RL2
VESD,HBM
VESD,CDM
2000
500
–
–
ESD robustness2) CDM
–
1) According to JEDEC standard JESD22-A114.
2) According to ESD Association Standard DS5.3.1 - 1999
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Attention: To avoid demage of the QuadLIUTM during power up, use the following sequence for biasing:
•
•
•
Core voltage
Pad voltage not before core voltage
Signal voltage not before Pad voltage
If this sequence does not meet your requirements make sure that
•
•
The inverse current per signal pad is lower than 10 mA
The current per supply domain is lower than 100 mA
Table 55 defines the maximum values of voltages and temperature which may be applied to guarantee proper
operation of the QuadLIUTM
.
Data Sheet
222
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 55
Operating Range
Parameter
Symbol
Values
Typ.
Unit
Note / Test
Condition
Min.
-40
Max.
85
Ambient temperature
TA
–
°C
–
Supply voltage digital pads
VDD
3.13
3.30
3.46
V
3.3 V ± 5 %
1)
Supply voltage digital core
VDDC
VDDR
1.62
3.13
3.13
0
1.80
3.30
3.30
–
1.98
3.46
3.46
V
V
V
V
1.8 V ±10 %
2)
Supply voltage analog receiver
3.3 V ±5 %
3)
Supply voltage analog transmitter VDDX
3.3 V ±5 %
4)
Analog input voltages
VRL
VID
VDDR
+0.3
RL1, RL2
Digital input voltages
Ground
-0.4
0
–
–
3.46
0
V
V
V
DD = 3.3 V ±5 %
VSS
–
VSSR
VSSX
1) Voltage ripple on analog supply less than 50 mV
2) Voltage ripple on analog supply less than 50 mV
3) Voltage ripple on analog supply less than 50 mV
4) Voltage ripple on analog supply less than 50 mV
Note:In the operating range, the functions given in the circuit description are fulfilled.
VDD, VDDR and VDDX have to be connected to the same voltage level,
VSS, VSSR and VSSX have to be connected to ground level.
Table 56
DC Characteristics
Parameter
Symbol
Values
Unit Note / Test
Condition
Min.
-0.4
2.0
Typ.
Max.
0.8
1)
Input low voltage
Input high voltage
Output low voltage
Output high voltage
VIL
–
–
–
–
V
1)
VIH
VOL
VOH
3.46
0.45
VDD
V
VSS
2.4
V
V
I
I
OL = +2 mA2)
OH = -2 mA 2)
Data Sheet
223
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 56
DC Characteristics (cont’d)
Parameter
Symbol
Values
Typ.
–
Unit Note / Test
Condition
Min.
Max.
Medium power supply current IDD33E1
at 3.3 V supply
–
230
mA
E1 application 3)
LIM1.DRS = ´0´,
(analog line interface mode)
All-one´s pattern; 16 MHz at
system interface; VSEL = 0
IDD33E1
IDD33T1
IDD33T1
–
–
–
–
–
–
200
215
190
E1 application 4)
LIM1.DRS = ´0´, PRBS pattern;
2 MHz at system interface;
VSEL = 0
T1 application5)
LIM1.DRS = ´0´, all-one´s pattern;
12 MHz at system interface;
VSEL = 0
T1 application 6)
LIM1.DRS = ´0´, PRBS pattern;
1.5 MHz at system interface;
VSEL = 0
Medium power supply current IDD18E1
at 1.8 V supply
(digital line interface mode)
–
–
–
–
220
20
mA
mA
E1 application 7)
LIM1.DRS = ´1´, all-one´s pattern;
16 MHz at system interface;
VSEL = 0
Medium power supply current IDD33T1
at 3.3 V supply
(digital line interface mode)
Input leakage current
Input leakage current
Input pullup current
Output leakage current
IIL11
IIL12
IIP
–
–
2
–
–
–
–
–
1
µA
µA
µA
µA
VIN =VDD8); all except RDO
VIN = VSS 6); all except RDO
VIN = VSS
1
15
1
IOZ1
V
V
OUT = tristate1)
SS < Vmeas < VDD
measured against VDD and VSS; all
except XL1/2
Transmitter leakage current
ITL
–
–
–
–
–
–
–
30
µA
XL1/2 = VDDX; XPM2.XLT = ´1´
XL1/2 = VSSX; XPM2.XLT = ´1´
Applies to XL1and XL29)
XL1, XL2
30
Transmitter output impedance RX
–
3
Ω
Transmitter output current
IX
–
105
2.15
mA
V
Differential peak voltage of a
mark
VX
–
–
(between XL1 and XL2)
Receiver peak voltage of a
mark
(at RL1 or RL2)
VRL12
VRL12
ZR
-0.45
-0.75
–
–
3.8
4.1
V
RL1, RL2
RZ signals; must only be applied
during T1 pulse over/undershoot
according to ANSI T1.403-1999
Receiver differential peak
voltage of a mark
(between RL1 and RL2)
–
–
–
4.0
V
V
RL1, RL2
4.63
RZ signals; must only be applied
during T1 pulse over/undershoot
according to ANSI T1.403-1999
9)
Receiver input impedance
Data Sheet
50
–
kΩ
224
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 56
DC Characteristics (cont’d)
Parameter
Symbol
Values
Typ.
Unit Note / Test
Condition
Min.
Max.
Receiver internal termination
resistor
RTERM
255
300
345
Ω
Internal termination enabled
Multi Purpose Analog Switch
RDSON
RDSOFF
RDSONDC
RDSON
SRSH
2.7
100
–
–
–
–
–
–
7.1
–
Ω
–
kΩ
mA
mA
dB
–
2
@ 125 oC
–
25
10
@ 50% duty cycle
Receiver sensitivity
Receiver sensitivity
0
RL1, RL2 LIM0.EQON = ´0´
(short-haul)
SRLH
-43
-36
–
–
0
0
dB
RL1, RL2 LIM0.EQON = ´1´ (E1,
long-haul)
RL1, RL2 LIM0.EQON = ´1´
(T1/J1, long-haul)
Receiver input threshold
VRTH
–
–
45
50
–
–
%
LIM2.SLT(1:0) = ´11b´ 9)
LIM2.SLT(1:0) = ´10b´ 9)
default setting
–
55
67
–
–
LIM2.SLT(1:0) = ´00b´ 9)
LIM2.SLT(1:0) = ´01b´ 9)
RIL(2:0) = ´000b´ 9)
RIL(2:0) = ´001b´ 9)
RIL(2:0) = ´010b´10)
RIL(2:0) = ´011b´ 9)
RIL(2:0) = ´100b´ 9)
RIL(2:0) = ´101b´ 9)
RIL(2:0) = ´110b´ 9)
RIL(2:0) = ´111b´ 9)
–
–
Loss-Of-signal (LOS) detection VLOS
limit
1560
790
430
220
125
65
1710
960
500
260
130
70
mV
–
–
–
–
–
35
–
40
10
–
15
1) Applies to all input pins except analog pins RLx
2) Applies to all output pins except pins XLx
3) Wiring conditions and external circuit configuration according to Figure 67 and Table 72.
4) Wiring conditions and external circuit configuration according to Figure 67 and Table 72.
5) Wiring conditions and external circuit configuration according to Figure 67 and Table 73.
6) Wiring conditions and external circuit configuration according to Figure 67 and Table 72.
7) Wiring conditions and external circuit configuration according to Figure 67 and Table 72.
8) Pin leakage is measured in a test mode with all internal pullups disabled. RDO pins are not tristatable, no leakage is
measured.
9) Parameter not tested in production
10) Value measured in production to fulfil ITU-T G.775
Note:Typical characteristics specify mean values expected over the production spread. If not specified otherwise,
typical characteristics apply at TA = 25 °C and 3.3 V supply voltage.
Data Sheet
225
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
6.1
AC Characteristics
Master Clock Timing
6.1.1
Figure 48 shows the timing and Table 57 the appropriate timing parameter values of the master clock at the pin
MCLK. The accuracy is required to fulfill the jitter requirements, see Chapter 3.7.8.1 and Chapter 3.9.4.
1
2
3
MCLK
F0007
Figure 48 MCLK Timing
Table 57
MCLK Timing Parameter Values
Parameter
Symbol
Min.
Values
Typ.
Unit
Note / Test
Condition
Max.
Clock period of MCLK
1
–
488
648
–
–
ns
E1, fixed mode
–
–
T1/J1, fixed mode
50
40
980.4
–
E1/T1/J1, flexible mode
High phase of MCLK
Low phase of MCLK
Clock accuracy
2
3
–
–
%
–
–
–
40
321)
–
–
282)
%
–
ppm
1) If clock divider programming fits without rounding
2) If clock divider programming requires rounding
6.1.2
JTAG Boundary Scan Interface
Figure 49 shows the timing and Table 58 the appropriate timing parameter values at the JTAG pins to perform a
boundary scan test of the QuadLIUTM, see Chapter 3.5.4.
Data Sheet
226
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
1
TRS
2
3
4
TCK
TMS, TDI
TDATI
5
6
8
7
9
TDO, TDATO
F0120
Figure 49 JTAG Boundary Scan Timing
Table 58
JTAG Boundary Scan Timing Parameter Values
Parameter
Symbol
Values
Unit
Note / Test
Condition
Min.
200
250
80
Typ.
–
Max.
TRS reset active low time
TCK period
1
2
3
4
5
6
7
8
9
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
TCK high time
–
–
TCK low time
80
–
–
TMS, TDI setup time
TMS, TDI hold time
TDATI setup time
TDATI hold time
40
–
–
40
–
–
40
–
–
40
–
–
TDO, TDATO output delay
–
–
100
6.1.3
Reset
Figure 50 shows the timing and Table 59 the appropriate timing parameter value at the pin RES to perform a reset
of the QuadLIUTM
.
1
RES
F0008
Figure 50 Reset Timing
Data Sheet
227
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 59
Reset Timing Parameter Value
Symbol
Parameter
Values
Typ.
Unit
Note / Test
Condition
Min.
Max.
RES pulse width low
1
101)
–
–
µs
–
1) While MCLK is running
6.1.4
Asynchronous Microprocessor Interface
6.1.4.1
Intel Bus Interface Mode
Figure 51 to Figure 54 show the timing of the SCI Interface and Table 60 the appropriate timing parameter
values.
Ax
BHE
CS
3
3A
1
2
RD
WR
ITT10975
Figure 51 Intel Non-Multiplexed Address Timing
Ax
BHE
5
4
6
ALE
7
7A
1
CS
3
3A
RD
WR
ITT10977
Figure 52 Intel Multiplexed Address Timing
Data Sheet
228
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
CS
RD
WR
8
9
9
8
11
Dx
32
33
30 31
READY
QLIU_F0121
Figure 53 Intel Read Cycle Timing
CS
8
9
WR
RD
9
8
16
31
15
Dx
34
30
READY
QLIU_intel_write_cycle
Figure 54 Intel Write Cycle Timing
Table 60
Intel Bus Interface Timing Parameter Values
Parameter
Symbol
Min.
Values
Typ.
Unit
Note/ Test
Condition
Max.
Address, BHE setup time
Address, BHE hold time
CS setup time
1
5
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
2
0
3
0
CS hold time
3A
0
Address, BHE stable before ALE inactive 4
25
10
Address, BHE hold after ALE inactive
5
Data Sheet
229
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 60
Intel Bus Interface Timing Parameter Values (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note/ Test
Condition
Min.
30
0
Max.
–
ALE pulse width
6
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
–
ALE setup time before RD or WR
ALE hold time after RD or WR
RD, WR pulse width
7
–
7A
8
301)
80
702)
10
30
10
–
–
–
RD, WR control interval
9
–
Data hold after RD inactive
Data stable before WR inactive
Data hold after WR inactive
RD or WR delay after READY
READY hold time after RD or WR
Data stable before READY
RD to READY delay
11
15
16
30
31
32
33
34
30
–
–
50
–
5
–
100
100
100
–
WR to READY delay
–
1) Not tested in production
2) Not tested in production
6.1.4.2
Motorola Bus Interface Mode
Figure 55 and Figure 56 show the timing of the SCI Interface and Table 61 the appropriate timing parameter
values.
Ax, BLE
17
18
CS
RW
DS
Dx
19
20
19A
21
22
23
24
25
41
44
43
DTACK
QLI U_F0122
Figure 55 Motorola Read Cycle Timing
Data Sheet
230
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Ax, BLE
CS
17
18
19
20
19A
RW
DS
21
22A
23
26
27
41
Dx
42
DTACK
QLIU_mot_write_cycle
Figure 56 Motorola Write Cycle Timing
Table 61
Motorola Bus Interface Timing Parameter Values
Parameter
Symbol
Min.
Values
Unit
Note/ Test
Condition
Typ.
Max.
–
Address, BLE setup time before DS active 17
15
0
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
Address, BLE hold after DS inactive
CS active before DS active
CS hold after DS inactive
18
–
19
0
–
19A
20
0
–
RW stable before DS active
RW hold after DS inactive
10
0
–
21
–
DS pulse width (read access)
DS pulse width (write access)
DS control interval
22
80
100
701)
–
–
22A
23
–
–
Data valid after DS active (read access)
24
752)
30
–
Data hold after DS inactive (read access) 25
–
Data stable before DS inactive (write
access)
26
30
Data hold after DS inactive (write access) 27
10
10
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
DTACK hold time after DS inactive
DS to DTACK delay for write
DS to DTACK delay for read
Data strobe before DTACK
41
42
43
44
–
100
100
–
–
0
1) Not tested in production
2) Not tested in production
Data Sheet
231
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
6.1.4.3
SCI Interface
Figure 57 shows the timing of the SCI Interface and Table 62 the appropriate timing parameter values.
1
3
2
SCI_CLK
4
5
SCI_RXD
SCI_TXD
6
QLIU_SCI_timing
Figure 57 SCI Interface Timing
Table 62
SCI Timing Parameter Values
Parameter
Symbol
Values
Unit
Note / Test
Condition
Min.
170
500
76.51)
76.52)
0
Typ.
Max.
SCI_CLK cycle time in full duplex mode
SCI_CLK cycle time in half duplex mode
SCI_CLK clock low time
1
1
2
3
4
5
6
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
SCI_CLK clock high time
–
SCI_RXD setup time before SCI_CLK
SCI_RXD hold time after SCI_CLK
SCI_TXD delay time after SCI_CLK
–
0
–
–
30
1) Not tested in production
2) Not tested in production
Data Sheet
232
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
6.1.4.4
SPI Interface
Figure 58 shows the timing of the SCI Interface and Table 63 the appropriate timing parameter values.
7
CS
6
2
8
1
SCLK
SDI
4
3
5
9
11
10
high impedance
SDO
QLIU_SPI_timing
Figure 58 SPI Interface Timing
Table 63
SPI Timing Parameter Values
Parameter
Symbol
Values
Typ.
Unit
Note / Test
Condition
Min.
–
Max.
100
–
SCLK frequency
–
1
2
3
4
5
6
7
8
9
10
–
–
–
–
–
–
–
–
–
–
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
CS setup time before SCLK
CS hold time after SCLK
SDI hold time after SCLK
SDI setup time before SCLK
SCLK low time
40
40
40
40
451)
452)
100
50
–
–
–
–
–
SCLK high time
–
CS high time
–
Clock disable time before SCLK
SDO output stable after SCLK
SDO output hold after CS disable
–
40
40
–
–
SDO output high impedance after SCLK 11
0
1) Not tested in production
2) Not tested in production
6.1.5
Digital Interface (Framer Interface)
Figure 59, Figure 60, Figure 61 and Figure 62 show the timing and Table 65, Table 66, Table 67 the
appropriate timing parameter values at the digital interface of the QuadLIUTM
.
Data Sheet
233
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
1
2
3
FCLKX (TPE=0)
FCLKX (TPE=1)
data change edge
4
5
XDI, XDIN
QLIU_F0055
Figure 59 FCLKX Output Timing
Table 64
FCLKX Timing Parameter Values
Parameter
Symbol
Values
Unit
Note / Test
Condition
Min.
–
Typ.
Max.
FCLKX clock period E1
FCLKX clock period T1/J1
FCLKX high
1
1
2
3
4
5
488
648
–
–
–
–
–
–
–
ns
ns
%
–
–
–
–
–
–
–
40
40
20
20
FCLKX low
–
%
XDI, XDIN setup time
XDI, XDIN hold time
–
ns
ns
–
1
2
3
FCLKR (RPE=1)
FCLKR (RPE=0)
data change edge
4
5
RDO, RDON
QLIU_F0054
Figure 60 FCLKR Output Timing
Data Sheet
234
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 65
FCLKR Timing Parameter Values
Symbol
Parameter
Values
Typ.
Unit
Note / Test
Condition
Min.
Max.
FCLKR clock period E1
FCLKR clock period T1/J1
FCLKR high
1
1
2
3
4
5
–
488
648
–
–
–
–
–
–
–
ns
ns
%
–
–
–
–
–
–
–
40
40
-10
200
FCLKR low
–
%
RDO, RDON setup time
RDO, RDON hold time
–
ns
ns
–
1
2
3
SYNC
Figure 61 SYNC Timing
F0056
Table 66
SYNC Timing Parameter Values
Symbol
Parameter
Values
Typ.
Unit
Note / Test
Condition
Min.
–
Max.
SYNC period 2.048 MHz
SYNC period 1.544 MHz
SYNC period 8 kHz
SYNC low time
1
1
1
2
3
488
648
125
–
–
–
–
–
–
ns
ns
ns
%
–
–
–
–
–
–
–
20
20
SYNC high time
–
%
1
2
FSC
3
RCLK
F0053
Figure 62 FSC Timing
Data Sheet
235
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 67
FSC Timing Parameter Values
Symbol
Parameter
Values
Typ.
Unit
Note / Test
Condition
Min.
Max.
–
FSC period
1
–
–
–
–
–
125
488
648
–
µs
ns
ns
ns
ns
–
–
–
–
–
FSC low time E1
2
2
3
3
–
FSC low time T1/J1
RCLK to FSC delay E1
RCLK to FSC delay T1/J1
–
370
280
–
6.1.6
Pulse Templates - Transmitter
The transmitter includes a programmable pulse shaper to generate transmit pulse masks according to:
•
For T1: FCC68; ANSI T1. 403 1999, figure 4; ITU-T G703 11/2001, figure 10 (for different cable lengths), see
Figure 64. For measurement configuration were Rload = 100 Ω see Figure 40.
•
For E1: ITU-T G703 11/2001, figure 15 (for 0 m cable length), see Figure 63; ITU-T G703 11/2001, figure 20
(for DCIM mode). For measurement configuration were Rload = 120 Ω or Rload = 75 Ω see Figure 39.
The transmit pulse form is programmed either
•
By the registers XMP(2:0) compatible to the QuadLIU®, see Table 29 and Table 30, if the register bit
XPM2.XPDIS is cleared
•
Or by the registers TXP(16:1), if the register bit XPM2.XPDIS is set, see Table 31 and Table 32.
6.1.6.1
Pulse Template E1
With the given values in Table 30 or Table 32, for transformer ratio: 1 : 2.4, cable type AWG24 and with Rload
120 Ω the pulse mask according to ITU-T G703 11/2001, see Figure 63, is fulfilled.
=
Data Sheet
236
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
269 ns
(244 + 25)
194 ns
(244 - 50)
V=100 %
Nominal Pulse
50 %
244 ns
219 ns
(244 - 25)
0 %
488 ns
(244 + 244)
ITD00573
Figure 63 E1 Pulse Shape at Transmitter Output
6.1.6.2
Pulse Template T1
With the given values in Table 29 or Table 31, for transformer ratio: 1 : 2.4, cable type AWG24 and with Rload
=
100 Ω the pulse mask according to ITU-T G703 11/2001, figure 10, see Figure 64, is fulfilled.
Normalized Amplitude
V=100%
50%
0
-50%
t
0
250
500
750
1000
ns
ITD00574
Figure 64 T1 Pulse Shape at the Cross Connect Point
Data Sheet
237
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 68
T1 Pulse Template at Cross Connect Point (T1.102 1))
Maximum Curve
Minimum Curve
Time [ns]
0
Level [%]2)
Time [ns]
0
Level [%]
-5
5
250
5
350
-5
325
80
115
115
105
105
-7
350
50
325
400
95
425
500
95
500
600
90
675
650
50
725
650
-45
-45
-20
-5
1100
1250
5
800
5
925
1100
1250
-5
1) Requirements of ITU-T G.703 are also fulfilled
2) 100 % value must be in the range of 2.4 V and 3.6 V;
tested at 0 and 200 m using PIC 22AWG cable characteristics.
Data Sheet
238
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
6.2
Capacitances
Values of capacitances of the input and of the output pins of the QuadLIUTM are listed in Table 69.
Table 69
Capacitances
Parameter
Symbol
Values
Typ.
Unit
Note / Test
Condition
Min.
Max.
10
Input capacitance1)
Output capacitance 1)
Output capacitance 1)
CIN
5
8
8
–
–
–
pF
pF
pF
–
COUT
COUT
15
All except XLx
XLx
20
1) Not tested in production
6.3
Package Characteristics
F0051
Figure 65 Thermal Behavior of Package
Table 70
Package Characteristic Values
Symbol
Parameter
Values
Unit
Note / Test
Condition
Min.
Typ.
47
9
Max.
1)
Thermal Resistance
Rthjam
–
–
–
–
–
–
K/W
K/W
K/W
Single layer PCB, no
convection
2)
Rthjc
1)
Thermal Resistance BGA
Junction Temperature
Rthjab
29
Single layer PCB,
natural convection
Rj
–
125
°C
–
1) Rthja = (Tjunction - Tambient)/Power: Not tested in production.
2) Rthjc = (Tjunction - Tcase)/Power: Not tested in production.
Data Sheet
239
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
6.4
Test Configuration
AC Tests
6.4.1
The values for AC characteristics of the chapters above are based on the following definitions of levels and load
capacitances:
Table 71
AC Test Conditions
Parameter
Symbol
CL
Test Values
Unit
pF
V
Notes
Load Capacitance
Input Voltage high
Input Voltage low
Test Voltage high
Test Voltage low
50
–
VIH
2.4
0.4
2.0
0.8
All except RLx
All except RLx
All except XLx
All except XLx
VIL
V
VTH
VTL
V
V
Test Levels
VTH
Device
under
Test
CL
VTL
Timing Test
Points
Drive Levels
VIH
VIL
F0067
Figure 66 Input/Output Waveforms for AC Testing
6.4.2
Power Supply Test
For power supply test all eight channels of the QuadLIUTM are active. Transmitter and receiver are configured as
for typical applications. The transmitted data are looped back to the receiver by a short line as shown in Figure 67.
On the system side the interfaces of all channels work independent from another (no multiplex mode is
configured).
Data Sheet
240
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
R1
R1
tt1 : t
t2
Digital Interface
QuadLIU
Z0
l
tr1 : t
r2
R2
4 x
QLIU_F0176
Figure 67 Device Configuration for Power Supply Testing
Table 72
Power Supply Test Conditions E1
Symbol
Parameter
Test Values
Unit
Ω
Notes
Load Resistance at transmitter
R1
7.5
1%; PC6.TSRE = ´0´
Termination Resistance at receiver R2
120
Ω
1%; integrated receive line
resistor RTERM is switched off
(LIM0.RTRS =´0´)
Line Impedance
RL
120
Ω
–
–
–
–
–
Line Length
l
< 0.2
2.4 : 1
1 : 1
m
Transformer Ratio Transmit
Transformer Ratio Receive
Framer interface Frequency
tt1 : tt2
tr1 : tr2
XCLK
RCLK
2.048
MHz
Test Signal
–
215-1
40H
03H
7BH
85
–
–
PRBS pattern
Pulse Mask Programming
(compatible to QuadLIU®)
XPM2
XPM1
XPM0
–
Pulse mask according to ITU-T
G703 11/2001, see Figure 63
Ambient Temperature
°C
–
Table 73
Power Supply Test Conditions T1/J1
Parameter
Symbol
R1
Test Values
Unit
Ω
Notes
Load Resistance
Termination Resistance
2
1%; PC6.TSRE = ´0´
R2
100
Ω
1%; integrated receive line
resistor RTERM is switched off
(LIM0.RTRS =´0´)
Line Impedance
RL
100
Ω
m
–
–
–
–
–
Line Length
l
< 0.2
2.4 : 1
1 : 1
Transformer Ratio Transmit
Transformer Ratio Receive
tt1 : tt2
tr1 : tr2
–
Data Sheet
241
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Electrical Characteristics
Table 73
Power Supply Test Conditions T1/J1 (cont’d)
Parameter
Symbol
Test Values
Unit
Notes
Framer interface Frequency
XCLK
RCLK
1.544
MHz
–
Test Signal
–
215-1
02H
27H
9FH
85
–
–
PRBS pattern
Pulse Mask Programming
(compatible to QuadLIU®)
XPM2
XPM1
XPM0
–
Pulse mask according to ITU-T
G703 11/2001, figure 10, see
Figure 64
Ambient Temperature
°C
–
Data Sheet
242
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Operational Description
7
Operational Description
7.1
Operational Overview
Each of the four channels of the QuadLIUTM can be operated in two clock modes, which are either E1 mode or
T1/J1 mode, selected by the register bit GCM2.VFREQ_EN, see Chapter 3.5.5:
•
In the so called “flexible master clocking mode” (GCM2.VFREQ_EN = ´1´) all four ports can work in E1 or in
T1 mode individually, independent from another.
•
In the so called “clocking fixed mode” (GCM2.VFREQ_EN = ´0´) all four ports must work together either in E1
or in T1 mode.
The device is programmable via one of the three integrated micro controller interfaces which are selected by
strapping of the pins IM(1:0):
•
The asynchronous interface has two modes: Intel (IM(1:0) = ´00b´) and Motorola (IM(1:0) = ´01b´). This
interface enables byte or word access to all control and status registers, see Chapter 3.5.1.
SPI interface (IM(1:0) = ´10b´), see Chapter 3.5.2.2.
•
•
SCI interface (IM(1:0) = ´11b´), see Chapter 3.5.2.1.
The QuadLIUTM has three different kinds of registers:
•
•
The control registers configure the whole device and have write and read access.
The status registers are read-only and are updated continuously. Normally, the processor reads the status
registers periodically to analyze the alarm status and signaling data.
•
The interrupt status registers are read-only and are cleared by reading (“rsc”). They are updated (set)
continuously. Normally, the processor reads the interrupt status registers after an interrupt occurs at pin INT.
Masking can be done with the appropriate interrupt mask registers. Mask registers are control registers.
All this registers can be separate into two groups:
•
•
Global registers are not belonging especially to one of the four channels. The higher address byte is ´00H´.
The other registers are belonging to one of the four channels. The higher address bytes - marked as ´xxH´ in
the register description - are identical to the numbers 0 up to 3 of the appropriate channels. So every of this
registers exist four time in the whole device.
7.2
Device Reset
After the device is powered up, the QuadLIUTM must be forced to the reset state first.
The QuadLIUTM is forced to the reset state if a low signal is input on pin RES for a minimum period of 10 µs, see
Figure 50. During reset the QuadLIUTM
•
•
•
•
Needs an active clock on pin MCLK and
The pin VSEL must be connect either to 3.3 V or to VSS to define if internal voltage regulator is used
The pins IM(1:0) must have defined values to select the micro controller interface.
Only if IM(1:0) = ´11b´ (SCI interface is selected) the pins A(5:0) must have defined values to select the SCI
source address of the device.
•
•
Only if IM1 = ´1´ (SCI or SPI interface is selected) the pins D(15:5) must have defined values to configure the
central PLL in the master clocking unit of the device.
Only if IM1 = ´0´ (asynchronous micro controller interface is selected) the pin READY_EN must have a defined
value to select if the signal READY/DTACK is used
During and after reset all internal flip-flops are reset and most of the control registers are initialized with default
values.
After reset the complete device is initialized, especially to E1 operation and “flexible master clocking mode”. The
complete initialization is listed in Table 74. Additionally all interrupt mask registers IMR1, IMR3, IMR4, IMR6 and
IMR7 are initialized to ´FFH´, so that not masking is performed.
After reset the QuadLIUTM must be configured first. General guidelines for configuration are described in
Chapter 7.4 for E1 mode and Chapter 7.5 for T1/J1 mode.
Data Sheet
243
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Operational Description
For reset see also Chapter 3.5.5.1.
7.3
Device Initialization
After reset, the QuadLIUTM is initialized for E1 with register values listed in the following table.
Table 74
Register
GPC1
Initial Values after Reset
Reset Value
Meaning
´00H´
Reserved mode. Must be set to ´10H´ for proper operation!
LIM0, LIM1,
PCD, PCR
´00H´, ´00H´,
´00H´, ´00H´
Slave Mode, local loop off
Analog interface selected; remote loop off; Pulse count for LOS detection
cleared; Pulse count for LOS recovery cleared
XPM(2:0)
´40H´, ´03H´, ´7BH´ E1 Transmit pulse template for 0 m but with unreduced amplitude (note that
transmitter is in tristate mode)
IMR(7:0)
GCR
´FFH´
´00H´
´00H´
´00H´
All interrupts are disabled
Internal second timer, power on
CMR1
CMR2
PC(3:1)
RCLK output: DPLL clock, DCO-X enabled, DCO-X internal reference clock
RCLK selected, XCLK selected
´00H´, ´F0H´
´00H´, ´00H´
Functions of ports RP(A to B) are reserved, function of port RPC is RCLK
output (but is only pulled up, because PC5.CRP = ´0´ after reset), functions
of ports XP(A to B) are reserved.
PC5
´00H´
FCLKR, FCLKX, RCLK configured to inputs,
“Flexible master clocking mode” selected
GCM(6:1)
GCM2 = ´10H´,
others ´00H´
GPC(4:3)
CMR(6:4)
GPC2
´43H´, ´21H´
´00H´
Sources for RCLK1 up to RCLK4 are the appropriate channels
Recovered line clock drives RCLK
´00H´
Source for SEC and RCLK1 is channel 1
TXP(16:1)
TXP(1:8) = ´38H´ This registers are not used after reset because XPM2.XPDIS = ´0´
TXP(9:16) = ´00H´
INBLDTR
ALS
´00H´
Minimum In-band loop detection time
No automatic loop switching is performed
No time slots are selected for PRBS pattern
´00H´
PRBSTS(4:1)
All ´00H´
7.4
Device Configuration in E1 Mode
E1 Configuration
For a correct start up of the primary access interface a set of parameters specific to the system and hardware
environment must be programmed after reset goes inactive. Both the basic and the operational parameters must
be programmed before the activation procedure of the PCM line starts. Such procedures are specified in ITU-T
and ETSI recommendations (e.g. fault conditions and consequent actions). Setting optional parameters primarily
makes sense when basic operation via the PCM line is guaranteed. Table 75 gives an overview of the most
important parameters in terms of signals and control bits which are to be programmed in one of the above steps.
The sequence is recommended but not mandatory. Accordingly, parameters for the basic and operational set up,
for example, can be programmed simultaneously. The bit MR1.PMOD should always be kept low (otherwise T1/J1
mode is selected).
Data Sheet
244
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Operational Description
Table 75
Configuration Parameters (E1)
Basic Set Up
Master clocking mode
GCM(6:1) according to external MCLK clock frequency
MR1.PMOD = ´0´
E1 mode select
Clock system configuration
Specification of line interface
Specification of transmit pulse mask
Line interface coding
CMR(3:1), GPC1; CMR(6:4) and GPC(6:2)
LIM0, LIM1, XPM(2:0)
XPM(2:0) or TXP(16:1)
MR0.XC(1:0), MR0.RC(1:0)
PCD, PCR, LIM1, LIM2
Loss-of-signal detection/recovery conditions
Multi Function Port selection
PC(3:1)
Features like alarm simulation etc. are activated later. Transmission of alarms (e.g. AIS, remote alarm) and control
of synchronization in connection with consequent actions to remote end and internal system depend on the
activation procedure selected.
Note:Read access to unused register addresses: value should be ignored. Write access to unused register
addresses: should be avoided, or set to “00” hex. All control registers (except XS(16:1), CMDR, DEC) are of
type Read/Write.
Specific E1 Register Settings
The following is a suggestion for a basic configuration to meet most of the E1 requirements. Depending on different
applications and requirement any other configuration can be used.
Table 76
Line Interface Configuration (E1)
GPC6.COMP_DIS = ´1´
MR2.DAIS = ´1´
Sets the QuadLIUTM into a defined mode (necessary for proper operation)
Disables AIS insertion into the data stream (necessary for proper operation)
MR2.RTM = ´1´
Sets the receive dual elastic store in a “free running” mode (necessary for proper
operation)
MR5.TT0 = ´1´
MR5.XTM = ´1´
Enables transmit transparent mode (necessary for proper operation)
Sets the transmitter in a “free running” mode (necessary for proper operation)
MR0.XC0/
MR0.RC0/
LIM1.DRS
MR3.CMI
The QuadLIUTM supports requirements for the analog line interface as well as the
digital line interface. For the analog line interface the codes AMI and HDB3 are
supported. For the digital line interface modes (dual- or single-rail) the QuadLIUTM
supports AMI, HDB3, CMI (with and without HDB3 precoding).
PCD = ´0AH´
LOS detection after 176 consecutive “zeros” (fulfills G.775).
LOS recovery after 22 “ones” in the PCD interval. (fulfills G.775).
LOS threshold of 0.6 V (fulfills G.775).
PCR = ´15H´
LIM1.RIL(2:0) = ´02H´
Attention: After the device configuration a software reset should be executed by setting of bits
CMDR.XRES/RRES.
7.5
Device Configuration in T1/J1 Mode
After reset, the QuadLIUTM is initialized for E1 doubleframe format. To configure T1/J1 mode, bit MR1.PMOD has
to be set high. After the internal clocking is settled to T1/J1mode (takes up to 20 µs), the following register values
are initialized:
T1/J1 Initialization
For a correct start up of the primary access interface a set of parameters specific to the system and hardware
environment must be programmed after RES goes inactive (high). Both the basic and the operational parameters
Data Sheet
245
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Operational Description
must be programmed before the activation procedure of the PCM line starts. Such procedures are specified in
ITU-T recommendations (e.g. fault conditions and consequent actions). Setting optional parameters primarily
makes sense when basic operation via the PCM line is guaranteed. Table 77 gives an overview of the most
important parameters in terms of signals and control bits which are to be programmed in one of the above steps.
The sequence is recommended but not mandatory. Accordingly, parameters for the basic and operational set up,
for example, can be programmed simultaneously. The bit MR1.PMOD must always be kept high (otherwise E1
mode is selected). J1 mode is selected by additionally setting RC0.SJR = ´1´.
Features like channel loop-back, idle channel activation, clear channel activation, extensions for signaling support,
alarm simulation, etc. are activated later. Transmission of alarms (e.g. AIS, remote alarm) and control of
synchronization in connection with consequent actions to remote end and internal system depend on the activation
procedure selected.
Table 77
Configuration Parameters (T1/J1)
Basic Set Up
T1
GCM(6:1) according to external MCLK clock frequency
MR1.PMOD = ´1´, MR1.PMOD = ´1´,
J1
Master clocking mode
T1/J1 mode select
Clock system configuration
Specification of line interface
CMR(3:1), GPC1; CMR(6:4) and GPC(6:2)
LIM0, LIM1,
Specification of transmit pulse mask XPM(2:0) or TXP(16:1)
Line interface coding
MR0.XC(1:0), MR0.RC(1:0)
PCD, PCR, LIM1, LIM2
Loss-of-signal detection/recovery
conditions
AIS to framer interface
MR2.XAIS
PC(3:1)
Multi Function Port selection
Note:Read access to unused register addresses: value should be ignored. Write access to unused register
addresses: should be avoided, or set to ´00H´. All control registers (except XS(12:1), CMDR, DEC) are of
type read/write
Specific T1/J1 Configuration
The following is a suggestion for a basic configuration to meet most of the T1/J1 requirements. Depending on
different applications and requirements any other configuration can be used.
Table 78
Register
Line Interface Configuration (T1/J1)
Function
GPC6.COMP_DIS = ´1´ Sets the QuadLIUTM into a defined mode (necessary for proper operation)
MR2.DAIS = ´1´
LOOP.RTM = ´1´
Disables AIS insertion into the data stream (necessary for proper operation)
Sets the receive dual elastic store in a “free running” mode (necessary for proper
operation)
MR4.TM = ´1´
Enables transparent mode (necessary for proper operation)
MR5.XTM = ´1´
CCB(3:1) = ´FFH‘
Sets the transmitter in a “free running” mode (necessary for proper operation)
“Clear Channel” mode is selected (necessary for proper operation only if AMI code is
selected)
MR0.XC0/1
MR0.RC0/1
LIM1.DRS
CCB(3:1)
The QuadLIUTM supports requirements for the analog line interface as well as the
digital line interface. For the analog line interface the codes AMI (with and without bit
7stuffing) and B8ZS are supported. For the digital line interface modes (dual- or
single-rail) the QuadLIUTM supports AMI (with and without bit 7 stuffing), B8ZS (with
and without B8ZS precoding).
DIC3.CMI
Data Sheet
246
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Operational Description
Table 78
Line Interface Configuration (T1/J1) (cont’d)
Register
Function
PCD = ´0AH´
PCR = ´15H´
LIM1.RIL(2:0) = ´02H´
GCR.SCI = ´1´
LOS detection after 176 consecutive “zeros” (fulfills G.775/Telcordia (Bellcore)/AT&T)
LOS recovery after 22 “ones” in the PCD interval (fulfills G.775, Bellcore/AT&T).
LOS threshold of 0.6 V (fulfills G.775).
Additional Recovery Interrupts. Help to meet alarm activation and deactivation
conditions in time.
LIM2.LOS1 = ´1´
Automatic pulse-density check on 15 consecutive zeros for LOS recovery condition
(Bellcore requirement)
Note:After the device configuration a software reset should be executed by setting of bits CMDR.XRES/RRES.
Data Sheet
247
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Operational Description
7.6
Device Configuration for Digital Clock Interface Mode (DCIM)
The following table shows the necessary configuration for the Digital Clock Interface Mode (DCIM), see ITU-T
G.703 11/2001, chapter 13. The receive clock at RL1/RL2 (2.048 MHz) is supported at multi function port RPC.
The transmit clock at FCLKX (2.048 MHz) is transmitted at XL1/XL2.
DCIM mode is standardized only for 2.048 MHz (E1 mode, MR1.PMOD = ´0´). The QuadLIUTM can handle also
1.544 MHz if MR1.PMOD = ´1´.
Table 79
Device Configuration for DCIM Mode
GPC6.COMP_DIS = ´1´
MR1.PMOD
Sets the QuadLIUTM into a defined mode (necessary for proper operation)
Selects 2.048 MHz or 1.544 MHz, see text above
Selects DCIM mode.
LIM0.DCIM = ´1´
LIM1.RL = ´0´
TX clock mode.
CMR1.DXSS = ´0´
CMR1.DXJA = ´0´
LIM1.DRS = ´0´
Line interface mode RX
MR0.RC(1:0) = ´10b´
MR0.XC(1:0) = ´10b´
PC1.RPC1(3:0) = ´1111b´
PC5.CRP = ´1´
Line interface mode TX
Select RCLK as output
CMR1.DRSS(1:0) or
RX clock mode
CMR5.DRSS(2:0) : select the
appropriate channel
CMR1.DCS = ´1´
LIM0.MAS = ´0´
CMR1.RS(1:0) = ´10b´ or
CMR4.RS(2:0) = ´010b´
GCM(1:8) see Chapter 3.5.5 and
Configure clock system
GCM6
LIM2.SCF, CMR6.SCFX,
Configure DCO-X and DCO-R
CMR2.ECFAX, CMR2.ECFAR,
CMR3:CFAX(3:0), CMR3.CFAR(3:0),
CMR4.IAR(4:0), CMR5.IAX(4:0): see
Chapter 3.7.8 and Table 23
DIC1.RBS(1:0) = ´10b´
DIC1.XBS(1:0) = ´11b´
Configure elastic buffers
Data Sheet
248
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Appendix
8
Appendix
8.1
Protection Circuitry
The design in Figure 68 shows an example of how to build up a generic E1/T1/J1 platform. The circuit shown has
been successfully checked against ITU-T K.20 and K.21 lightning surge tests (basic level). For values of R1 see
Table 28.
1:1
RL1
PTC
B
A
A
Fuse
1.25 A
VDD
VSS
RL2
PTC
Fuse
1.25 A
RJ45
QuadLIU
1:2.4
XL1
R1
R1
PTC
B
Fuse
A
A
1.25 A
VDD
VSS
XL2
PTC
Fuse
1.25 A
A
B
SMP 100LC-35 (~65 pF)
SMP P3500SC (~60 pF)
QLIU_F0262_2
Figure 68 Protection Circuitry Examples (shown for one channel)
8.2
Application Notes
Several application notes and technical documentation provide additional information. Online access to supporting
information is available on the internet page:
http://www.infineon.com/octalliu
On the same page you find as well the
•
Boundary Scan File for QuadLIUTM Version 2.1 (BSDL File)
8.3
Software Support
The following software package is provided together with the QuadLIUTM Reference System EASY 2256:
•
•
•
E1 and T1 driver functions supporting different ETSI, AT&T and Telcordia (former: Bellcore) requirements
IBIS model for QuadLIUTM Version 2.1 (according to ANSI/EIA-656)
“Flexible Master Clock Calculator”, which calculates the required settings for the registers GCM(1:8)
depending on the external master clock frequency (MCLK)
•
“External Line Front End Calculator”, which provides an easy method to optimize the external components
depending on the selected application type.r
The both calculators run under a Win9x/NT environment. Calculation results are traced an can be stored in a file
or printed out for documentation.
Screen shots of both programs are shown in Figure 69 and Figure 70 below.
Data Sheet
249
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Appendix
F0126
Figure 69 Screen Shot of the “Master Clock Frequency Calculator”
Data Sheet
250
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Appendix
F0198_2256
Figure 70 Screen Shot of the “External Line Frontend Calculator”
Data Sheet
251
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
Terminology
A
A/D
Analog to digital
ADC
AIS
Analog to Digital Converter
Alarm Indication Signal (blue alarm)
Automatic Gain Control
AGC
ALOS
AMI
Analog Loss Of Signal
Alternate Mark Inversion
American National Standards Institute
Asynchronous Transfer Mode
AUXiliary Pattern
ANSI
ATM
AUXP
B
B8ZS
Bellcore
BPV
BSN
C
Binary 8 Zero Supression (Line coding to avoid too long strings of consecutive "0")
Bell Communications Research
BiPolar Violation
Backward Sequence Number
CDR
CIS
Clock and Data Recovery
Channel Interrupt Status
CMI
D
Coded Mark Inversion code (also known as 1T2B code)
D/A
Digital to Analog
DAC
DCIM
DCO
DCO-R
DCO-X
DL
Digital to Analog Converter
Digital Clock Interface Mode
Digitally Controlled Oscillator
DCO of receiver
DCO of transmitter
Digital Loop
DPLL
DS1
E
Digitally controlled Phase Locked Loop
Digital Signal level 1
ESD
EASY
EQ
ElectroStatic Discharge
Evaluation system for FALC and LIU products
EQualizer
ETSI
F
European Telecommunication Standards Institute
FALC®
FCC
FCS
G
Framing And Line interface Component
US Federal Communication Commission
Frame Check Sequence (used in PPR)
Data Sheet
252
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
GIS
H
Global Interrupt Status
HBM
HDB3
I
Human body model for ESD classification
High density bipolar of order 3
IBIS
IBL
I/O buffer information specification (ANSI/EIA-656)
In Band Loop
ISDN
ITU
Integrated Services Digital Network
International Telecommunications Group
J
JATT
JTAG
L
Jitter ATTenuator
Joined Test Action Group
LBO
LCV
LIU
Line Build Out
Line Code Violation
Line Interface Unit
Local Loop
LL
LLB
LOS
LSB
M
Line Loop Back
Loss of Signal (red alarm)
Least Significant Bit
MFP
MSB
MUX
N
Multi Function Port
Most Significant Bit
MUltipleXer
NRZ
P
Non Return to Zero signal
PCM
PD
Pulse Code Modulation
Pull Down resistor
PDV
PLB
PLL
PMQFP
PRBS
PTQFP
PU
Pulse Density Violation
Payload Loop Back
Phase Locked Loop
Plastic Metric Quad Flat Pack (device package)
Pseudo Random Binary Sequence
Plastic Thin Metric Quad Flat Pack (device package)
Pull Up resistor
R
RAI
RAM
RDI
RL
Remote Alarm Indication (yellow alarm)
Random Access Memory
Remote Defect Indication
Remote Loop
RLM
ROM
Receive Line Monitoring
Read-Only Memory
Data Sheet
253
Rev. 1.3, 2006-01-25
QuadLIUTM
PEF 22504
RX
S
Receiver
SAPI
SCI
SPI
Sidactor
T
Service Access Point Identifier (special octet in PPR)
Serial ControlInterface
Serial Peripheral Interface
Overvoltage protection device for transmission lines
TAP
TEI
TX
Test Access Port
Terminal Endpoint Identifier (special octet in PPR)
Transmitter
U
UI
Unit Interval
Z
ZCS
Zero Code Suppression
Data Sheet
254
Rev. 1.3, 2006-01-25
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
PEF22554
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
INFINEON
PEF22554E
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
INFINEON
PEF22554HT
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
INFINEON
PEF2256E
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
INFINEON
©2020 ICPDF网 联系我们和版权申明