PIIPM50E06M004X [INFINEON]
Programmable Isolated IPM; 可编程隔离IPM
| 型号： | PIIPM50E06M004X |
| 厂家： | 
Infineon |
| 描述： | Programmable Isolated IPM |
| 文件： | 总28页 (文件大小：963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Bulletin I27146 01/03
PIIPM50P12B004
Programmable Isolated IPM
PI-IPM Features:
Package:
ꢀ
Power Module:
•
•
NPT IGBTs 50A, 1200V
10us Short Circuit capability
ꢀ
ꢀ
ꢀ
Square RBSOA
Low Vce(on) (2.15Vtyp @ 50A, 25°C)
Positive Vce(on) temperature coefficient
•
•
Gen III HexFred Technology
ꢀ
Low diode VF (1.78Vtyp @ 50A, 25°C)
Soft reverse recovery
ꢀ
2mΩ sensing resistors on all phase outputs and DCbus
PI-IPM – Inverter (EconoPack 2 outline compatible)
minus rail
ꢀ
T/C < 50ppm/°C
Power Module schematic:
ꢀ
Embedded driving board
•
•
•
Programmable 40 Mips DSP
Current sensing feedback from all phases
Full protection from ground and line
to line faults
•
•
UVLO, OVLO on DCbus voltage
Embedded flyback smps for floating
stages (single 15Vdc @ 300mA input required)
Asynchronous isolated 2.5Mbps serial port for
DSP communication and programming
IEEE standard 1149.1 (JTAG port interface)
for program downloading and debugging
Separated turn on / turn off outputs for
IGBTs di/dt control
•
•
•
•
Three phase inverter with current sensing
resistors on all output phases
Isolated serial port input with strobe signal for
quadrature encoders or SPI communication
PI-IPM System Block Schematic:
Description
The PIIPM50P12B004 is a fully integrated Intelligent Power
Module for high performances Servo Motor Driver applications.
The device core is
a
state of the art DSP, the
TMS320LF2406A* at 40 Mips, interfaced with a full set of
peripheral designed to handle all analog feedback and control
signals needed to correctly manage the power section of the
device.
The PI-IPM has been designed and tailored to implement
internally all functions needed to close the current loop of a
high performances servo motor driver, a basic software is
already installed in the DSP and the JTAG connector allows
the user to easily develop and download its own proprietary
algorithm.
The device comes in the EMPTM package, fully compatible in
length, width and height with the popular EconoPack 2 outline.
*Beta samples come with the TMS320LF2406 at 30Mips, please refer to TI datasheet
for further information about performances.
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1
PIIPM50P12B004
I27146 01/03
Detailed Block Diagram
m C o
n e - t o B o
t l u F a
- r k e c t T
P D
3 0 n i C D A
5 0 n i C D A
U 1 E M
U 0 E M
- T S T R
k T c
2 0 n i C D A
1 0 n i
A D C
0 0 n i C A D
t l u a L F
4 0 n i C D A
o
i
T D
T D
T M
S
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2
PIIPM50P12B004
I27146 01/03
Signal pins on RS422 serial port
Symbol
Lead Description
Pin number
Vin iso
GND iso
Tx+
Tx-
External 5V supply voltage for opto-couplers and line driver supply
Extenal 5V supply ground reference for opto-couplers and line driver supply
RS422 Trasmitter Non inverting Driver Output
6
7
1
2
RS422 Trasmitter Inverting Driver Output
4
3
5
9
10
Rx+
Rx-
RS422 Receiver Non inverting Driver Input,
RS422 Receiver Inverting Driver Input
Incremental Encoder 1 / Hall effect sensor input 1/ SpiCK input (GND iso referenced)
RS422
serial
port
Enc1 – Hall1 / SpiCK
Enc2 – Hall2 / SpiSTE Incremental Encoder 2 / Hall effect sensor input 2 / SpiSTE input (GND iso referenced)
Strb – Hall3 / SpiRx
SpiTx
Vin
COM
Incremental Encoder Strobe / Hall effect sensor input 3 / SpiRx input (GND iso ref.)
SpiTx output (GND iso referenced)
External 15V supply voltage. Internally referred to DC bus minus pin (DC -)
External 15V supply ground reference. This pin is directly connected to DC -
8
17-18
19-20
Signal pins on IEEE1149.1 JTAG connector
Symbol
TMS
TMS2
TDI
Lead Description
State
Pin number
JTAG test mode select
JTAG test mode select 2
JTAG test data input
JTAG test data output
Input
Input
Input
12
5-6
14
13
15
TDO
Output
JTAG test clock. TCK is a 10MHz clock source from the emulation pod. This
signal can be used to drive the system test clock.
JTAG test reset
TCK
TRST~
EMU0
Input
Input
I/O
11
9-10
7-8
1
Emulation pin 0
Emulation pin 1
Presence detect.
IEEE1149.1
JTAG
EMU1/OFF~
I/O
Indicates that the emulation cable is connected and that the PI-IPM logic is
powered up. PD is tied to the DSP 3.3V supply through a 1k resistor.
JTAG test clock return. Test clock input to the emulator.
Internally short circuited to TCK.
Boot ROM enable. This pin is sampled during DSP reset, pulling it low
enables DSP boot ROM (Flash versions only). 47k internal pull up.
PD
Output
Output
16
TCK_RET
17
20
Boot-En
COM
Input
N/A
External 15V supply ground reference. This pin is directly connected to DC -
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3
PIIPM50P12B004
I27146 01/03
Following pins are intended for signal communication between driving board and
power module only, though here described for completeness, they are on purpose
not available to the user.
Symbol
DC +
Lead Description
Pin number
DC Bus plus input signal
DC -
Th +
DC Bus minus input signal (internally connected to COM)
Thermal sensor positive input
Th -
Sh +
Sh -
G1/2/3
E1/2/3
R1/2/3 +
R1/2/3 -
G4/5/6
E4/5/6
Thermal sensor negative input (internally connected to COM)
DC Bus minus series shunt positive input (Kelvin point)
DC Bus minus series shunt negative input (Kelvin point)
Gate connections for high side IGBTs
Emitter connections for high side IGBTs (Kelvin points)
Output current sensing resistor positive input (IGBTs emitters 1/2/3 side, Kelvin points)
Output current sensing resistor negative input (Motor side, Kelvin points)
Gate connections for low side IGBTs
Lateral connectors
on embedded
driving board
Emitter connections for low side IGBTs (Kelvin points)
Power Module Frame Pins Mapping
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4
PIIPM50P12B004
I27146 01/03
Absolute Maximum Ratings (TC=25ºC)
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur.
All voltage parameters are absolute voltages referenced to VDC-, all currents are defined positive into any lead.
Thermal Resistance and Power Dissipation ratings are measured at still air conditions.
Symbol
Parameter Definition
Min.
Max.
1000
1200
50
Units
VDC
DC Bus Voltage
0
0
V
VCES
Collector Emitter Voltage
º
IC @ 100C
IC @ 25C
ICM
IGBTs continuous collector current (TC = 100 C)
º
100
200
50
IGBTs continuous collector current (TC = 25 C)
Pulsed Collector Current (Fig. 3, Fig. CT.5)
A
º
Inverter
IF @ 100C
IF @ 25C
IFM
Diode Continuous Forward Current (TC = 100 C)
º
100
200
+20
330
130
20
Diode Continuous Forward Current (TC = 25 C)
Diode Maximum Forward Current
Gate to Emitter Voltage
VGE
-20
V
PD @ 25°C
PD @ 100°C
Vin
Power Dissipation (One transistor)
W
º
Power Dissipation (One transistor, TC = 100 C)
Non isolated supply voltage (DC- referenced)
Isolated supply voltage (GND iso referenced)
RS422 Receiver input voltage (GND iso referenced)
Operating Ambient Temperature Range
Board Storage Temperature Range
-20
-5
V
Vin-iso
5.5
Rx
-7
12
Embedded
Driving
Board
TA—EDB
TSTG-EDB
-20
-40
+60
+125
ºC
AC
DC
800
1000
V
V
VISO-CONT RS232
Input-Output Continuous Withstand Voltage (RH ≤ 50%, -40°C ≤ TA ≤ 85°C )
VISO-TEMP RS232
RMS
2500
V
Input-Output Momentary Withstand Voltage (RH ≤ 50%, t = 1 min, TA = 25°C)
Mounting Torque
MT
3.5
Nm
T J
Operating Junction Temperature
-40
-40
+150
+125
+2500
Power
Module
ºC
V
TSTG
Vc-iso
Storage Temperature Range
Isolation Voltage to Base Copper Plate
-2500
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5
PIIPM50P12B004
I27146 01/03
Electrical Characteristics: Inverter
For proper operation the device should be used within the recommended conditions.
TJ = 25°C (unless otherwise specified)
Symbol
Parameter Definition
Min.
Typ.
Max.
Units
Test Conditions
GE = 0V, IC = 250µA
GE = 0V, IC = 1mA (25 - 125 C)
Fig.
V(BR)CES
Collector To Emitter Breakdown Voltage
Temperature Coeff. of Breakdown Voltage
1200
V
V
V
º
º
+1.2
2.15
2.70
2.45
4.7
∆V(BR)CES /
V/ C
T
∆
2.50
3.78
3.22
5.5
IC = 50A, VGE = 15V
IC = 100A, VGE = 15V
5, 6
7, 9
VCE(on)
Collector To Emitter Saturation Voltage
V
V
º
10, 11
IC = 50A, VGE = 15V, TJ = 125 C
VGE(th)
Gate Threshold Voltage
4.4
29
V
V
CE = VGE, IC = 250µA
CE = VGE, IC = 1mA (25 - 125 C)
12
º
º
Temp. Coeff. of Threshold Voltage
Forward Trasconductance
-1.2
33
∆VGE(th) /
mV/ C
Tj
∆
gfe
38
500
S
VCE = 50V, IC = 50A, PW = 80µs
VGE = 0V, VCE = 1200V
ICES
Zero Gate Voltage Collector Current
µA
º
GE = 0V, VCE = 1200V, TJ = 125 C
650
1350
4000
2.1
V
º
VGE = 0V, VCE = 1200V, TJ = 150 C
IC = 50A
1.78
1.90
8
8
VFM
Diode Forward Voltage Drop
V
º
2.22
20
IC = 50A, TJ = 125 C
º
IRM
Diode Reverse Leakage Current
Gate To Emitter Leakage Current
Sensing Resistors
µA
VR = 1200V, TJ = 25 C
IGES
±200
2.02
2.02
nA
VGE = 20V
R1/2/3
Rsh
1.98
1.98
2
2
mΩ
DC bus minus series shunt resistor
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6
PIIPM50P12B004
I27146 01/03
Switching Characteristics: Inverter
For proper operation the device should be used within the recommended conditions.
TJ = 25°C (unless otherwise specified)
Symbol
Qg
Parameter Definition
Total Gate Charge (turn off)
Min
Typ
400
Max Units
Test Conditions
Fig.
IC = 50A
411
23
nC
µJ
µJ
VCC = 600V
VGE = 15V
Qge
Gate – Emitter Charge (turn off)
Gate – Collector Charge (turn off)
Turn on Switching Loss
46
55
CT1
Qgc
181
200
º
Eon
2814
5293
8107
3220
5825
9145
CT4
WF1
WF2
IC = 50A, VCC = 600V, TJ = 25 C
Eoff
Turn off Switching Loss
V
GE = 15V, RG =10Ω, L = 250µH
Etot
Total Switching Loss
Tail and Diode Rev. Recovery included
º
IC = 50A, VCC = 600V, TJ = 125 C
13,
15
CT4
WF1
WF2
Eon
Eoff
Etot
Turn on Switching Loss
Turn off Switching Loss
Total Switching Loss
3963
7810
4415
8965
VGE = 15V, RG =10Ω, L = 250µH
11773
13380
Tail and Diode Rev. Recovery included
td (on)
Tr
Turn on delay time
Rise time
66
72
72
83
14,16
CT4
º
IC = 50A, VCC = 600V, TJ = 125 C
ns
td (off)
Tf
Turn off delay time
Fall time
593
95
641
117
WF1
WF2
VGE = 15V, RG =10Ω, L = 250µH
Cies
Coes
Cres
Input Capacitance
5884
950
6052
968
VCC = 30V
VGE = 0V
f = 1MHz
pF
22
Output Capacitance
Reverse Transfer Capacitance
167
193
º
TJ = 150 C, I C =250A, VGE = 15V to 0V
4
RBSOA
SCSOA
Reverse Bias Safe Operating Area
Short Circuit Safe Operating Area
FULL SQUARE
CT2
VCC = 1000V, Vp = 1200V, RG = 5Ω
º
CT3
TJ = 150 C, VGE = 15V to 0V
10
µs
WF4
VCC = 900V, Vp= 1200V, RG = 5Ω
17,18
19,20
21
CT4
WF3
º
EREC
trr
Diode reverse recovery energy
Diode reverse recovery time
Peak reverse recovery current
693
156
35
1114
260
42
1535
363
43
µJ
ns
A
TJ = 125 C
IF = 50A, VCC = 600V,
Irr
VGE = 15V, RG =10Ω, L = 250µH
º
º
RthJC_T
RthJC_D
Each IGBT to copper plate thermal resistance
Each Diode to copper plate thermal resistance
0.38
0.76
C/W
C/W
24
Module copper plate to heat sink thermal
resistance. Silicon grease applied = 0.1mm
º
RthC-H
0.03
C/W
º
100
150
250
200
IC = 7A, VDC = 530V, fsw = 8kHz, TC = 55 C
PD1
PD2
PD3
º
IC = 10A, VDC = 530V, fsw = 8kHz, TC = 55 C
Pdiss
Total Dissipated Power
W
º
IC = 10A, VDC = 530V, fsw = 16kHz TC = 55 C,
º
IC = 20A, VDC = 530V, fsw = 4kHz, TC = 40 C
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7
PIIPM50P12B004
I27146 01/03
Electrical Characteristics: Embedded Driving Board (EDB) communication ports
For proper operation the device should be used within the recommended conditions.
Vin = 15V, Vin-iso = 5V, TA = 0 to 55C, TC = 75C (unless otherwise specified)
Symbol
Vin
Parameter Definition
EDB Input supply Voltage
Min.
12
Typ.
15
Max.
18
Units
V
Test Conditions
Conn.
Isupp
Isupp
Isupp
Vin iso
Iq. iso
EDB input Supply Current with EEprom not programmed
EDB Input Supply Current
90
100
149
152
5
110
166
170
5.5
mA
mA
mA
V
131
132
4.5
VDC = 0V, fPWM = 8kHz (*)
Vdc=600V, fPWM = 8kHz (*)
EDB Input Supply Current
RS422
port
EDB isolated supply voltage
Rx+ = +5V, Rx- = 0V
Hall1/2/3 = open
EDB isolated quiescent supply current
9
20
mA
Hall1/2/3 low
Rx+ = 0V, Rx- = +5V
Tx+ and Tx- open
Hall1/2/3 low
24
29
48
34
59
mA
mA
Isupp. iso
EDB isolated supply current
Rx+ = 0V, Rx- = +5V
Tx+ and Tx- on 120Ω
37
2
VDO-TX
VCO-TX
VDI-RX
RIN-RX
fMAX
Differential Driver Output Voltage
Driver Common mode output voltage
Receiver Input Differential Threshold Voltage
Receiver Input Resistance
V
V
Rload = 120 Ω
3
RS422
port
- 0.2
0.2
V
≤
≤ +12V
VCM
- 7V
120
Ω
RS422 maximum data rate
2.5
2
Mbps
Venc-high /
Vhall-high
Logic High Input Voltage
3.6
V
Enc1 / Hall1
Enc2 / Hall2
Strb / Hall3
input pins
RS422
port
Venc-low /
Vhall-low
Ienc-low /
Ihall-low
Logic Low Input Voltage
Logic Low Input Current
V
- 5.2
mA
TMS
TMS2
TDI
Please see
Directly connected from
DSP to connector pins.
EMU0 and EMU1 with 4.7k
internal pull up.
TDO
TMS320LF2406A
datasheet from
Texas Instruments
TCK
JTAG interface pins
JTAG
TRST-
EMU0
EMU1/OFF~
PD
and VPD specifications
VPD
Presence detect voltage
3.2
3.3
3.4
V
V
JTAG
JTAG
IPD = -100µA
VBoot En
IBoot-En
Boot ROM enable input voltage
Boot ROM enable input current
0.5
Active low
- 100
µA
* these values are obtained with internal DSP clock, EVA, EVB, SCI peripherals enabled at 40MHz, A/D peripheral at 20MHz and 50% PWM duty cycle on
all legs.
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8
PIIPM50P12B004
I27146 01/03
AC Electrical Characteristics: Embedded Driving Board (EDB)
DSP pins mapping
For proper operation the device should be used within the recommended conditions.
Vin = 15V, Vin-iso = 5V, TA = 0 to 55C, TC = 75C (unless otherwise specified)
Test
Symbol
Parameter Definition
Min.
Typ.
Max.
Units
DSP name ; pin N
Conditions
VDCgain
VDC-MAX
VDCpole
VDC-OVth
VTH25C
VTH100C
Vin-gain
Vin-pole
Iph-GAIN
Iph-pole
Iph-MAX
Iph-MIN
Iph-LAT
Iph-Zero
ISC
DC bus voltage feedback partition coefficient
Maximun DC bus voltage read
2.39
1309
950
870
2.65
1.04
125
1600
16.6
5.0
2.44
2.49
mV/V
V
ADCin03;72
DC bus voltage feedback filter pole
DC bus voltage over-voltage threshold
1000
920
1050
970
Hz
V
PDPINTA;6
ADCin04;70
º
2.75
1.09
128
2.85
1.14
131
V
Thermal sensor voltage feedback at 25 C (Fig. TF1)
º
Thermal sensor voltage feedback at 100 C (Fig.
V
Input voltage feedback partition coefficient
mV/V
Hz
mV/A
kHz
Α
ADCin05;69
Input voltage feedback filter pole
Current feedback gain
1700
16.9
5.5
1800
17.2
6.0
Current feedback filter pole
ADCin00: 79
ADCin01: 77
ADCin02: 74
Maximun Current feedback read
Minimun Current feedback read
Current feedback signal delay
Zero current input voltage level
Short Circuit Threshold Current
Short Circuit detection delay time
DC bus minus over-current level
DC bus minus over-current filter pole
External watchdog timeout (see also RS~ signal)
95
all phases
-95
12
Α
µs
V
1.64
110
1.67
128
3
1.70
146
6
A
all phases
all phases
PDPINTA;6
ISC-DEL
DCOC
µs
A
130
14
140
15
150
16
DC bus minus
DC bus minus
PDPINTA;6
WD;85
DCOC-pole
WD
kHz
Sec
0.9
1.6
2.5
2, 3, 5, 7, 11, 12, 13, 14, 15, 16, 19, 26, 27, 29, 32, 34, 38, 41, 43, 45, 46, 48, 53, 56, 58, 60, 63, 65,
66, 67, 68, 71, 73, 75, 76, 78, 80, 81, 84, 90, 97
COM
DSP Ground
3.3V
DSP 3.3V supply
4, 10, 20, 30, 35, 47, 54, 59, 64, 91, 98
42,44,51,88
floating
Ref3.3V
The following pins are left unconnected
3.3V reference voltage
3.33
V
VCCA,VREFHI; 83,82
~ indicates active low signals
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9
PIIPM50P12B004
I27146 01/03
Other DSP pins mapping
Symbol
PWM1
Signal Definition
DSP pin name ;pin N
Comments
DSP Event Manager A output
OUT 1 high side IGBT gate drive signal
OUT 1 low side IGBT gate drive signal
OUT 2 high side IGBT gate drive signal
OUT 2 low side IGBT gate drive signal
OUT 3 high side IGBT gate drive signal
OUT 3 low side IGBT gate drive signal
PWM1;39
PWM2;37
PWM3;36
PWM4;33
PWM5;31
PWM6;28
PWM2
PWM3
PWM4
PWM5
PWM6
DSP Event Manager A output
DSP Event Manager A output
DSP Event Manager A output
DSP Event Manager A output
DSP Event Manager A output
Enc1–Hall1 /
SpiCK
Incremental Encoder 1 / Hall effect sensor
input 1/ SpiCK input (GND iso referenced)
SPICK;24
QEP1;57
Optically isolated input
Enc2 – Hall2 /
SpiSTE
SPISTE~;23
QEP2; 55
Incremental Encoder 2 / Hall effect sensor
input 2 / SpiSTE input
Incremental Encoder Strobe / Hall effect
sensor input 3 / SpiSIMO input (GND iso ref.)
Optically isolated input
Optically isolated input
Strb – Hall3 /
SpiRx
SPISIMO;21
CAP3; 52
SPISOMI;22
Optically isolated input
SpiTx
SpiSOMI output (GND iso referenced)
3.3V reference voltage
Vrefhi;82
Vcca; 83
Ref3.3V
3.33V reference voltage for ADC converter
Supplied by the embedded flyback regulator
See also EDB electrical characteristics
5V supp.
Boot En~
Tx
Flash programming voltage pin
Boot ROM enable signal
SCI transmit data
Vccp;40
BOOT_EN~;86
SCITXD;17
CANTX ; 50
SCIRX ; 18
CANRX ; 49
Drives Tx+ and Tx- through an opto-isolator and a line driver
Rx
SCI receive data
Driven by Rx+ and Rx- through an opto-isolator and a line driver
Activated by short circuits on output phases and DC bus minus and by
DC bus over-voltage comparator
LFAULT
System general fault input (latched)
IOPF6;92
IOPF5;89
PDPINTA~;6
RS~;93
LFAULT Reset signal, to be activated via software after a fault or
LFAULT reset System general fault output reset signal
system boot
Activated by short circuits on output phases and DC bus minus and by
DC bus over-voltage comparator
FAULT~
RS~
System general fault input (not latched)
DSP reset input signal (see also WD signal)
PLL oscillator input pin
Forces a DSP reset if WD signal holds too long (see also EDB
electrical char.)
Xtal1
XTAL1;87
PLLF;9
A 10Mhz oscillator at 100ppm frequency stability feeds this pin.
PLL filter for 40Mhz DSP clock frequency
PLL filter for 40Mhz DSP clock frequency
Not used pull up 4.7K to 3.3V
PLLF1
PLLF2
PDPINTB
PLL filter input 1
PLL filter input 2
PLLF2;8
External protection interrupt for EVB
PDPINTB~;95
~ indicates active low signals
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10
PIIPM50P12B004
I27146 01/03
THE “EMPTM” POWER MODULE
General Description
The PI-IPM is a new generation of Intelligent
Power Module designed specifically to
implement itself a complete motor driver system.
The device contains all peripherals needed to
control a six IGBTs inverter, including voltage,
temperature and current output sensing,
completely interfaced with a 40Mips DSP, the
TMS320LF2406A from Texas Instruments. All
communication between the DSP and the local
host, including DSP software installing and
debugging, is realized through an asynchronous
isolated serial port (SCI), an isolated port for
incremental encoder inputs or synchronous serial
port communication (SPI) is also provided
This module contains six IGBTs + HexFreds
Diodes in a standard inverter configuration.
IGBTs used are the new NPT 1200V-50A
(current rating measured @ 100C), generation V
from International Rectifier; the HexFred diodes
have been designed specifically as pair elements
for these power transistors. Thanks to the new
design and technologic realization, this gen V
devices do not need any negative gate voltage for
their complete turn off and the tail effect is also
substantially reduced compared to competitive
devices of the same family. This feature
simplifies the gate driving stage that will be
described in a dedicated chapter. Another not
standard feature in this type of power modules is
the presence of sensing resistors in the three
output phases, for precise motor current sensing
and short circuit protections, as well as another
resistor of the same value in the DC bus minus
line, needed only for device protections purposes.
A complete schematic of the EMP module is
shown on page 1 where sensing resistors have
been clearly evidenced, a thermal sensor is also
embedded and directly coupled with the DSP
inputs.
making this module
a
complete user
programmable solution connected to the system
only through a serial link cable.
System Description
The PI-IPM is realized in two distinct parts: the
Power Module “EMP” and the Embedded
Driving Board “EDB,” these two elements
assembled together constitute the complete
device with all performances described in the
following.
The complete block schematic showing all
functions implemented in the product is
represented on the System Block Schematic on
page 1. The new module concept includes
everything depicted within the dotted line, the
EMP power module includes IGBTs, Diodes and
Sensing Resistors while all remaining electronics
is assembled on the EDB that is fitted on the top
of it as a cover with also mechanical protective
functions.
The package chosen is mechanically compatible
with the well known EconoPack outline, also the
height of the plastic cylindrical nuts for the
external PCB positioned on its top is the same, so
that, with the only re-layout of the main
motherboard, this module can fit into the same
mechanical fixings of the standard Econo II
package thus speeding up the device evaluation
in an already existing driver.
An important feature of this new device is the
presence of Kelvin points for all feedback and
command signals between the board and the
module with the advantage of having all emitter
and resistor sensing independent from the power
path. The final benefit is that all low power
signal from/to the controlling board are
unaffected by parasitic inductances or resistances
inevitably present in the module power layout.
Connections between the two parts are realized
through a single-in-line connector and the EDB
only, without disassembling the power module
from the system mechanic, can be easily
substituted “at the factory” for an upgrade, a
system configuration change (different control
architecture) or a board replacement. Also
software upgrades are possible but this does not
even require any hardware changes thanks to the
DSP programmability through the serial or JTAG
ports.
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The new package outline is show on page 4, all
signal and power pins are clearly listed, note that
because of high current spikes on those inputs the
DC bus power pins are doubled in size
comparing to the other power pins. Module
technology uses the standard and well know
DBC: over a thick Copper base an allumina
(Al2O3) substrate with a 300µm copper foil on
both side is placed and IGBTs and Diodes dies
are directly soldered, through screen printing
process. These dies are then bonded with a 15
mils aluminum wire for power and signal
connections. All components are then completely
covered by a silicone gel with mechanical
protection and electrical isolation purposes.
1. DSP and opto isolated serial and JTAG
ports.
The DSP used in this application is the new
TMS320LF2406A from TI, it is a improvement
of the well known in the motor driver market
“F240” used in many motor driver applications.
If we compare this new device with the
predecessor, the new DSP has some added
features that let the software designer
significantly improve the system control
performances, the following table shows a list of
relevant data, for all other information please
refer to the related device datasheet. To be noted
is the increased number of instruction per second,
(40MIPS) and of I/O pins, the availability of a
boot ROM and a CAN, a much faster ADC and
the reduced supply voltage from 5V down to
3.3V, to follow the global trend for this type of
products. The choice of the DSP has been done
looking at the high number of applications
already existing in the market using devices of
this family, however it is clear that the same kind
of approach could be followed using products
from different suppliers to let the customer work
on its preferred and well known platform.
THE “EDB” EMBEDDED DRIVING BOARD
This is the core of the device intelligence, all
control and driving functions are implemented at
this level, the board finds its natural placement as
a cover of the module itself and has a double
function of mechanical cover and intelligent
interface. DSP and all other electronics are here
assembled; figure on page 2 shows the board
schematic and all connection pins.
Looking at the schematic, all diamond shaped
pins are signal connections, some belonging to
the RS422 port interface and some to the IEEE
1149.1 (JTAG) connector. All other pins are used
for communication between the board and the
module, they are positioned laterally in the board
and the module doesn’t have any pins in the
middle of its body.
TMS320LF2406A vs TMS320F240
‘F2406
‘F240
20
MIPS
40
544w
16Kw
—
RAM
2.5Kw
32Kw
—
Flash
ROM
—
Boot ROM
Ext. Memory I/F
Event manager
• GP timers
• CMP/PWM
• CAP/QEP
Watchdog timer
10-bit ADC
• Channels
• Conv. time (min)
SPI
256w
—
Yes
Yes
3
Yes
4
From the top left, in anti-clockwise direction we
identify the following blocks that will be then
described in details:
9/12
4/2
10/16
6/4
Yes
Yes
16
Yes
Yes
16
1. DSP and opto isolated serial and JTAG
ports
500ns
Yes
Yes
Yes
37
6.6µs
Yes
Yes
—
2. Flyback Power Supply
SCI
3. Current Sensing interfaces, over-current
protections and signal conditioning
CAN
Digital I/O pins
Voltage range
28
3.3V
5 V
4. Gate drivers
5. DC bus and Input voltage feedback
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The “2406A” has three different serial interfaces
available: SCI, SPI, and CAN bus. In the PI-
IPM50P12B004 communication is made through
the asynchronous port (SCI) while four other
opto-isolated lines can be used for the SPI or for
the hall effect sensor interface. Maximum bit rate
for this asynchronous serial port is 2.5Mbps
while the SPI (synchronous) could reach
10Mbps. The choice of the SCI has been taken
for easy interfacing with a standard computer
serial port, the only component needed is a line
driver to adapt the RS232 voltage standard with
the RS422 at 3.3V used on this application.
floating stages, isolated from each other at 1.5kV
minimum, and a single 5V and 3.3V output.
The 5V supplies all low voltage electronics and a
3.3V linear regulator is used to feed the DSP and
some analog and logic interfaces to it. This 5V
and 3.3V are directly referred to the DC bus
minus, so that all control circuitry is alternately at
one of the input lines potential, isolation is
provided at the DSP serial link level, then
avoiding all delays due to opto couplers insertion
between DSP and control logic. Note that also
the required 15V input voltage is referred to the
same DC bus minus and directly supplies the low
side gate drivers stages, the user should pay some
attention on how this supply line is realized in his
application. Just for completeness, the following
figure gives a possible solution to that that
doesn’t impact heavily on the user application.
In a standard Brushless motor application usually
1Mbps are far enough to transmit all information
needed for the torque reference updates and other
fault and feedback signals at a maximum frame
rate of 10kHz (100bits/frame), in this way the on-
board line driver let the application use long
connecting wires between the host and the
module, leaving the user the possibility of having
the PI-IPM displaced near the motor, e.g. in its
connecting box, thus avoiding long ad noisy three
phase cables between driver and load.
The JTAG port is the standard one, neither
isolation nor signal conditioning are provided
here and all signal, except the Tck-ret, are
directly connected from the related DSP pins to
the connector; however, due to the limited board
space, the connector used in not the standard 14
pins at two rows header, then an adaptor has to
be realized to connect it to the JTAG adapter
interface provided by Texas Instruments.
Examples of power supply for PI-IPM
15V and 5V iso inputs
Normally a 5V power supply is already present,
for displays, electronics and micro processor, the
same 5V could be used for the 5V iso supply of
opto-couplers and line driver, the 15V could be
realized as an added winding in the secondary
side of the flyback transformer, the only care that
should be taken is in keeping its isolation from
the above mentioned 5V at the required level (at
least 1.5kV).
Last but not least is the ADC speed and load
characteristic: as the table shows the conversion
time is 500ns, in fact the 2406A DSP has a single
ADC handling, in time sharing, all 16 inputs,
then, using 6 inputs, the total conversion time,
which is a fixed delay to wait for before having
all data updated, is around 3.0µs.
To avoid noise problems in the measuring lines
due to the commutating electronics during
normal functioning of the system, references are
kept separated. A 5V linear regulator, directly
supplied from the 15V input, is used to provide
the reference voltage to the current sensing
amplifying and conditioning components while a
precise op-amp, configured as a voltage follower,
2. Flyback Power Supply
A flyback power supply for the floating stages is
provided in the EDB. As the block schematic on
page 2 shows, we have three 15V outputs for the
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acts as a buffer of the partition at 3.30V created
down the 5V reference. This 3.30V is used also
as reference for the DSP A/D converter. It has to
be noted that in the schematic we are using the
same linear regulator as a starting point for all
reference voltages. In fact if the 5V linear
regulator drifts in temperature or time, then all
references (even the 3.30V being this a simple
partitioning) follow in track and still keep the
overall chain precision. The trimming is then
done only once, in a single point of the
measuring chain, that is the conditioning op-amp
collecting the current sensing ICs signal as will
then be described in the following chapter.
so that the offset and gain is easily trimmed by
three on board resistors. The filter implemented
is a second order Bessel with 5.5kHz pole
frequency, the reason for this is that this type of
polynomials are calculated with the aim of
having a constant group delay within the pass-
band frequencies, thus giving the minimum
waveform distortion to the output signal up to
almost twice the filter pole. In other words we
could also say that the group delay of the signal
chain from the sensing resistor up to the ADC
input of the DSP is constant from 0 to 5.5kHz.
Signal outputted from the overall chain has a 0 to
+3.30V dynamic, with a sensing resistor of
2mohms the input measured current range is +/-
100A then we have a situation as follows:
3. Current sensing interfaces, over-current
protections and signal conditioning.
−100A = 0.0V
0.00A =1.65V
+100A = 3.30V
This block is the real critical point of the system.
Current measuring performances directly impact
on motor control performances in a servo
application: errors in current evaluation, delay in
its measuring chain or poor overall precision of
the system, such as scarce references or lower
number of significant A/D bits, inevitably results
in unwanted trembling and unnatural noise
coming from the motor while running at lower
speed or at blocked shaft conditions.
Summing up our current measurements
performances are shown in the following table:
PI-IPM Current sensing chain typical
performances
Value
Units
current range
+/- 100
A
In the PI-IPM50P12B004 the current sensing
function is done through three sensing resistors
dropout measurement, one on each output phase,
with the benefit of a lower area and somewhat a
lower cost compared to the well-known Hall
effect devices. This solution has the added value
of having the shunts element embedded in the
power module with all Kelvin connections
available, avoiding any noise due to long routing
of power paths.
Gain and Offset
precision
+/- 1.8
%
Bandwidth
5.5
10
kHz
latency time
µs
The “2406A” DSP has
a
10bit ADC,
consequently the PI-IPM50P12B004 has a
minimum
appreciable
current
step
of
approximately:
As the block schematic on page 2 shows, the
voltage across each sensing resistor is applied,
through an anti-aliasing 400kHz filter, at the
input of a current sense IC and then to a signal
conditioning circuit.
2*100
210
LSB =
= 0.1953Α
that is:
1LSB ≅195mA
Though the block schematic here shows an Op-
Amp plus an external passive filter this is simply
realized implementing a VCVS cell (i.e. a
Constant Gain or Sallen – Key cell) configured
The over current protection is provided also
through the current sensing ICs, the related fault
signal is activated when a 250mV voltage across
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PIIPM50P12B004
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sensing pins is detected, this means an over-
current detection level of approximately 25%.
The delay of this line is around 3µs, fast enough
to let the DSP react within the 10µs IGBTs short
circuit rating, thus providing full device
protection for any phase-to-ground and phase-to-
phase short circuits. The only failure not covered
in this way is the shoot-through, where high
current levels cannot be detected from outside the
module rather internally between two IGBTs of
the same leg. In this case the protection is
implemented by means of the fourth sensing
element, with the same resistive value of the
other shunts present in the power module,
inserted in series to the DC bus minus. The
related dropout voltage is then filtered by a
15kHz passive filter to avoid false fault
detections due to unwanted induced voltage
spikes and finally applied to an operational
amplifier configured as a comparator. All data
referred to the OC protection are listed on page 9
of this datasheet.
turn on only. Observed rise and fall times are
around 250ns – 300ns depending on the output
current level, this values are considered as pretty
adequate for a 25A application at 16kHz
symmetric PWM carrier, space vector
modulation.
These gate drivers do provide levels shifting
without any galvanic isolation, that is no opto-
couplers are built inside. This turns out to be a
major benefit in this stage where the usual 1µs
delay of optos impacts on the system control as a
systematic and fastidious delay.
5. DC bus and Input voltage feedback
The purpose of this block is to continuously
check the voltage of the two supply lines of the
system: Vin and DC bus. Vin is the only external
power supply needed for all electronics in the
EDB. The internal flyback regulator has its own
under-voltage lockout to prevent all electronics
from start working when an insufficient supply
voltage is present; minimum recommended
supply voltage is 12V. Low side gate drivers are
directly fed from the Vin line and there is no
further control to this voltage than their own
under-voltage lockout. This is typically set at
8.5V and this level could be not sufficient to
properly drive the IGBT gates, then it is
advisable to check with the DSP the input voltage
and impose that the system could start switching
only when the Vin voltage is between 10V and
18V thus providing also an over-voltage control.
4. Gate Drivers
Devices used to perform this task are the well-
known IR2213, capable of 2A sink and 2A
source maximum gate driving current, in a
SO16W package; on page 2 is shown also the
block schematic of the gate driving section of the
module.
The IGBTs used in the PI-IPM (genV NPT
1200V - 50A from IR) do not need any negative
gate drive voltage for their complete turn off, this
simplifies the flyback power supply design
avoiding the need of center tapped transformer
outputs or the use of zener diodes to create the
central common reference for the gate drivers
floating ground. Though the IR2213 do have +/-
2A of gate current capability, in the PI-
IPM50P12B004 we use different gate resistor
values for turn on and turn off as follows:
The DC bus voltage is also important for the
system functioning and needs to be continuously
kept under control. A resistor divider provides a
partition coefficient of 2.44mV/V and
maximum mapped voltage of around 1100V
a
As the block schematic shows, it has to be taken
into account that, to avoid false detections due to
voltage spikes inevitably present on the
partitioned voltage, a 1kHz passive filter has
been inserted between the divider and the voltage
follower buffer whose output is connected to one
of the ADC inputs.
turn − on = 33ohm
turn − off = 7.6ohm
Commonly realized through a diode-resistor
series in parallel with a single resistor used in
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PIIPM50P12B004
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Fig. 1 – Maximum DC collector
Current vs. case temperature
Fig. 2 – Power Dissipation vs.
Case Temperature
TC = (ºC)
TC = (ºC)
Fig. 3 – Forward SOA
Fig. 4 – Reverse Bias SOA
Tj = 150ºC, VGE = 15V
TC = 25ºC; Tj ≤ 150ºC
VCE = (V)
VCE = (V)
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Fig. 5 – Typical IGBT Output Characteristics
Fig. 6 – Typical IGBT Output Characteristics
Tj = - 40ºC; tp = 300µs
Tj = 25ºC; tp = 300µs
VCE = (V)
VCE = (V)
Fig. 7 – Typical IGBT Output Characteristics
Fig. 8 – Typical Diode Forward Characteristics
Tj = 125ºC; tp = 300µs
tp = 300µs
VCE = (V)
VF = (V)
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Fig. 9 – Typical VCE vs. VGE
Tj = - 40ºC
Fig. 10 – Typical VCE vs. VGE
Tj = 25ºC
VGE = (V)
VGE = (V)
Fig. 11 – Typical VCE vs. VGE
Tj = 125ºC
Fig. 12 – Typical Transfer Characteristics
VCE = 20V; tp = 20µs
VGE = (V)
VGE = (V)
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Fig. 13 – Typical Energy Loss vs. IC
Tj = 125ºC; L = 250µH; VCE = 600V;
Rg = 10Ω; VGE = 15V
Fig. 14 – Typical Switching Time vs. IC
Tj = 125ºC; L = 250µH; VCE = 600V;
Rg = 10Ω; VGE = 15V
IC = (A)
IC = (A)
Fig. 16 – Typical Switching Time vs. Rg
Tj = 125ºC; L = 250µH; VCE = 600V;
ICE = 50A; VGE = 15V
Fig. 15 – Typical Energy Loss vs. Rg
Tj = 125ºC; L = 250µH; VCE = 600V;
ICE = 50A; VGE = 15V
Rg = (Ω)
Rg = (Ω)
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Fig. 17 – Typical Diode IRR vs. IF
Tj = 125ºC
Fig. 18 – Typical Diode IRR vs. Rg
IF = 50A; Tj = 125ºC
IF = (A)
Rg = (Ω)
Fig. 19 – Typical Diode IRR vs. dIF/dt
Fig. 20 – Typical Diode QRR
VDC = 600V; VGE = 15V; IF = 50A; Tj = 125ºC
VDC = 600V; VGE = 15V; Tj = 125ºC
dIF/dt (A/µs)
dIF/dt (A/µs)
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Fig. 21 – Typical Diode EREC vs. IF
Tj = 125ºC
Fig. 22 – Typical Capacitance vs. VCE
VGE = 0V; f = 1MHz
IF = (A)
VCE = (V)
Fig. 23 – Typical Gate Charge vs. VGE
IC = 50A; L = 600µH; VCC = 600V
QG = (nC)
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Fig. 24 – Normalized Transient Impedance, Junction-to-copper plate
t1, Rectangular Pulse Duration (sec)
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Fig. PD1 – Total Dissipated Power vs. fSW
IoutRMS = 7A, VDC = 530V, TC = 55ºC
Fig. PD2 – Total Dissipated Power vs. fSW
IoutRMS = 10A, VDC = 530V, TC = 55ºC
fSW = (kHz)
fSW = (kHz)
Fig. TF1 – Thermal Sensor Voltage
Feedback vs. Base-plate Temperature
Fig. PD3 – Total Dissipated Power vs. fSW
IoutRMS = 20A, VDC = 530V, TC = 40ºC
TC (ºC)
fSW = (kHz)
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PIIPM family part number identification
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Top board suggested footprint
(top view)
RS422 and JTAG Connectors top view
These connectors do not have any orientation tag; please check their Pin 1 position on Power Module Frame
Pins Mapping before inserting mate part.
Molex 53916-0204
mates with 54167-0208 or 52991-0208
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PIIPM50P12B004 case outline and dimensions
Data and specifications subject to change without notice
This product has been designed and qualified for Industrial Level.
Qualification Standards can be found on IR’s Web Site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 3252 7105
TAC Fax: (310) 252 7309
Visit us at www.irf.com for sales contact information 01/03
Data and specifications subject to change without notice.
Sales Offices, Agents and Distributors in Major Cities Throughout the World.
© 2003 International Rectifier - Printed in Italy 01-13 - Rev. 2.9
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