PMB2304R [INFINEON]
PLL-FREQUENCY SYNTHESIZER; PLL频率合成器
| 型号： | PMB2304R |
| 厂家： | 
Infineon |
| 描述： | PLL-FREQUENCY SYNTHESIZER |
| 文件： | 总33页 (文件大小：1335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wireless Components
PLL-Frequency Synthesizer
PMB 2304R Version 2.1
Specification June 2002
preliminary
Revision History: Current Version: 06.02
Previous Version:Data Sheet
Page
Page
Subjects (major changes since last revision)
(in previous
Version)
(in current
Version)
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®,
IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-
2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG.
Edition 03.02
Published by Infineon Technologies AG
SC,
Balanstraße 73,
81541 München
© Infineon Technologies AG 13.06.02.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits im-
plemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest
Infineon Technologies Office.
Infineon Technologies AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing
material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the
Infineon Technologies AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-
support device or system, or to affect its safety or effectiveness of that device or system.
1. 2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they
fail, it is reasonable to assume that the health of the user may be endangered.
PMB 2304R
preliminary
Productinfo
Productinfo
Package:
General Description The PMB 2304R PLL is a high speed
CMOS IC, especially designed for use
in battery powered radio equipment
and mobile telephones and serves as a
functional replacement of the PMB
2307R. The primary applications are in
digital cellular and cordless systems
e.g. GSM 900/1800/1900 and DECT
systems. The wide range of dividing
ratios also allows application in analog
systems.
Features
Low operating current consumption
(typically 3.5 mA)
Large dividing ratios for small
channel spacing
A counter 0 to 127
N counter 3 to 16.383
R counter 3 to 65.535
High input sensitivity, high input
frequencies (220 MHz)
Extremely fast phase detector
without dead zone
Serial control (3-wire bus: data,
clock, enable) for fast programming
(fmax ~ 10 MHz)
Linearization of the phase detector
output by current sources
Switchable polarity and phase
detector current programmable
Synchronous programming of the
counters (N-, N/A-, R-counters)
and system parameters
2 Multifunction outputs
frn, fvn outputs of the R- and
N/A- counters for test
Fast modulus switchover for
65-MHz operation
Output port
Switchable modulus trigger edge
(e.g. for standby of the prescaler)
Serial control (3-wire bus: data,
clock, enable) for fast programming
(fmax ~ 10 MHz)
External current setting for PD
output
Lock detect output with quasidigital
lock detect
Application
GSM 900 / 1800 / 1900
DECT
Analog systems
Ordering Information
Type
PMB 2304R
Ordering Code
Q67106-H9100
Package
P-TSSOP-16
Wireless Components
Product Info
Specification, June 2002
1
Table of Contents
1
2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.6 Data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
5
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.3 Typical Supply Current IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.1.4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2 Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3 Serial Control Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4 Programming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.5 Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6 Serial Control Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.7 Diagram Input Sensitivity FI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
2
Product Description
Contents of this Chapter
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PMB 2304R
preliminary
Product Description
2.1 Overview
The PMB 2304R PLL is a high speed CMOS IC, especially designed for use in
battery powered radio equipment and mobile telephones and serves as a func-
tional replacement of the PMB 2307R. The primary applications are in digital
cellular and cordless systems e.g. GSM 900/1800/1900 and DECT systems.
The wide range of dividing ratios also allows application in analog systems.
2.2 Features
Low operating current consumption (typically 3.5 mA)
High input sensitivity, high input frequencies (220 MHz)
Extremely fast phase detector without dead zone
Linearization of the phase detector output by current sources
Synchronous programming of the counters (N-, N/A-, R-counters) and
system parameters
Fast modulus switchover for 65-MHz operation
Switchable modulus trigger edge
Serial control (3-wire bus: data, clock, enable) for fast programming
(fmax ~ 10 MHz)
Large dividing ratios for small channel spacing
A counter 0 to 127
N counter 3 to 16.383
R counter 3 to 65.535
Serial control (3-wire bus: data, clock, enable) for fast programming
(fmax ~ 10 MHz)
Switchable polarity and phase detector current programmable
2 Multifunction outputs frn, fvn outputs of the R- and N/A- counters for test
Output port (e.g. for standby of the prescaler)
External current setting for PD output
Lock detect output with quasidigital lock detect
Wireless Components
2 - 2
Specification, June 2002
PMB 2304R
preliminary
Product Description
2.3 Application
GSM 900 / 1800 / 1900
DECT
Analog systems
2.4 Package Outlines
P-TSSOP-16
Wireless Components
2 - 3
Specification, June 2002
3
Functional Description
Contents of this Chapter
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.6 Data acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
PMB 2304R
preliminary
Functional Description
3.1 Pin Configuration
RI
VSS
EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LD
M FO 2
M FO 1
VDD1
PD
DA
PMB 2304R
CLK
VDD
M O D
NC
VSS1
FI
NC
Pin_config.wmf
Figure 3-1
Pin Configuration
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin Symbol
No.
Equivalent I/O-Schematic
Function
1
RI
Reference Frequency
Input with highly sensitive
STD BY
preamplifier for 16-bit R-counter. With
small input signals AC
coupling must be set up, where DC cou-
pling can be used for large input signals.
500K
Ω
Pin1
R I
560
Ω
2pF
ESD
STDBY
VSS
2
Ground for serial control logic.
Wireless Components
3 - 2
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3
4
5
EN
3-Line Bus: Enable
Enable line of the serial control with inter-
nal pull-up resistor. When EN = H the
input signals CLK and DA are disabled
internally. When EN = L the serial control
is activated. The received data are trans-
ferred into the latches with the positive
edge of the EN-signal.
Pin 3
EN
560
560
560
Ω
Ω
Ω
ESD
ESD
ESD
DA
3-Line Bus: Data
Serial data input with internal pull-up
resistor. The last two bits before the EN-
signal define the destination address. In a
byte-oriented data structure the transmit-
ted data have to end with the EN-signal,
i.e. bits to be filled in (don’t care) are
transmitted first.
Pin 4
DA
CLK
3-Line Bus: Clock
Clock line with internal pull-up resistor.
The serial data are read into the internal
shift register with the positive edge (see
pulse diagram for serial data control).
Pin 5
CLK
6
7
VDD
Positive supply voltage for serial control
logic.
MOD
Modulus Control Output for external
dual modulus prescaler. The modulus
output is low at the beginning of the cycle.
When the A-counter has reached its set
value, MOD switches to high. When the
N-counter has reached its set value,
MOD switches to low again, and the cycle
starts from the top. When the prescaler
has the counter factor P or P + 1 (P for
MOD = H, P +1 for MOD = L), the overall
divider factor is NP + A. The value of the
A-counter must be smaller than that of
the N-counter. The trigger edge of the
modulus signal to the input signal can be
selected (see programming tables and
MODA, B) according to the needs of the
prescaler. In single modulus operation
and for standby operation in dual modu-
lus operation, the output is low.
pin 7
M O D
2pF
ESD
Wireless Components
3 - 3
Specification, June 2002
PMB 2304R
preliminary
Functional Description
8
NC
NC
FI
not connected
not connected
9
10
VCO-Frequency
Input with highly sensitive preamplifier for
14-bit N-counter and 7-bit A-counter. With
small input signals AC coupling must be
set up, where DC coupling can be used
for large input signals.
STD BY
500K
Ω
Pin10
FI
560
Ω
2pF
ESD
STDBY
11
12
VSS1
Ground for the preamplifiers, counters,
phase detector and charge pump.
(Note: The pins VDD and VDD respec-
1
tively VSS and VSS have to have the
1
same supply voltage.)
PD
Phase Detector
Tristate charge pump output. The inte-
grated, positive and negative current
sources can be programmed with respect
to their current density by means of the
serial control. Activation and deactivation
depend on the phase relationship of the
scaled-down input signals FI:N, RI:R.
(See phase detector output waveforms.)
frequencyfV < fR or fV lagging:p-channel
current source active
pin 12
*2pF
PD
ESD
frequencyfV > fR or fR leading:n-channel
current source active
* O nly this pin has lim ited build-in ESD
protection
frequencyfV = fR and PLL locked:current
sources are switched off,
PD-output is tristate
In standby mode the PD-output is set to
tristate. The assignment of the current
sources to the output signals of the phase
detector can be swapped in it’s polarity,
i.e. the sign of the phase detector con-
stant can be controlled.
13
VDD1
Positive supply voltage for the preamplifi-
ers, counters, phase detector and charge
pump.
Wireless Components
3 - 4
Specification, June 2002
PMB 2304R
preliminary
Functional Description
14
MFO1
Multifunction Output for the signals fRN
ΦV,, ΦVN , and port1.
,
–The signal fRN is the divided signal of the
reference frequency.
The L-time corresponds to 1/fRI respec-
tively
–In the port function the port 1 output sig-
nal is assigned to the information of the
programmed status. The output switches
with the rising edge of the EN-signal
The standby mode does not affect the
port function.
pin 14
M FO 1
2pF
ESD
15
MFO2
Multifunction I/O-Pin for the external ref-
erence current setting IREF and the signals
560
Ω
Φ
and fVN ( in testmode).
RN
IREF
–The signal fVN is the divided signal of FI-
input. The L-time corresponds to 1/fFI
respectively.
Output levels are not specified, the signal
should only be used for test purpose.
–In the internal charge pump mode the
reference current IREF at MFO2 deter-
mines the value of the PD-output current.
M F02
Pin15
VREF
2pF
Internal Charge
Pum p M ode
& standby
VREF
ESD
16
LD
Lock Detector Output (open drain). Uni-
polar output of the phase detector in the
form of a pulse-width modulated signal.
The LD-pulse width corresponds to the
phase difference. In the locked state the
LD-signal is at H-level. For standby mode
see Standby Table.
pin 16
LD
2pF
Only for ABL status 11 no gating of ABL
impulse is performed.
ESD
Wireless Components
3 - 5
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3.3 Functional Block Diagram
ƒR
Phase-
R
16-Bit R-Counter
RI
Lock-
LD
Detector
Detector
Data Register
and
Shadow Register
PD
ƒV
Charge
Pum p
Shift Register
V
M FO 1
IREF
M FO 2
M O D
M odulus Control
14-Bit
N-Counter
7-Bit
A-Counter
FI
Data Register
Shadow Register
Shift Register
Data Register
Shadow Register
Shift Register
VDD1
VSS1
CLK
DA
EN
VDD
VSS
Serial Control Logic
Funct_block.wmf
Figure 3-2
Functional Block Diagram
Wireless Components
3 - 6
Specification, June 2002
PMB 2304R
preliminary
Functional Description
3.4 General Description
The circuit consists of a reference-, A- and N-counter, a dual modulus control
logic, a phase detector with charge pump output and a serial control logic. The
setting of the operating mode and the selection of the counter ratios is done
serially at the ports CLK, DA and EN.
The operating modes allow the selection of single or dual operation, asynchro-
nous or synchronous data acquisition, 4 different antibacklash-impulse times, 8
different PD-output current modes, polarity setting of the PD-output signal,
adjustment of the trigger-edge of the MOD-output signal, 2 standby modes and
the control of the multifunction outputs MFO1 and MFO2.
The reference frequency is applied at the RI-input and divided by the R-counter.
It’s maximum value is 100 MHz. The VCO-frequency is applied at the FI-input
and divided by the N- or N/A-counter according to single or dual mode opera-
tion. The maximum value at FI is 220 MHz at single-, and 65 MHz at dual mode
operation.
The phase and frequency sensitive phase detector produces an output signal
with adjustable anti-backlash impulses in order to prevent a dead zone for very
small phase deviations. Phase differences of less than 100 ps can be resolved.
In general the shortest anti-backlash pulse gives the best system performance.
3.5 Programming
Programming of the IC is done by a serial data control. The contents of the mes-
sage are assigned to the functional units according to the address. Single or
dual mode operation as well as asynchronous or synchronous data acquisition
is set by status 2 and should therefore precede the programming of the
counters.
3.6 Data acquisition
The PMB 2304R offers the possibility of synchronous data acquisition to avoid
error signals at the phase detector due to non-corresponding dividing factors in
the counters produced by asynchronous loading.
Synchronous programming guarantees control during changes of frequency or
channel. That means that the state of the phase detector or the phase
difference is kept maintained, and in case of “lock in”, the control process starts
with the phase difference “zero”.
Wireless Components
3 - 7
Specification, June 2002
PMB 2304R
preliminary
Functional Description
This is done as follows:
1. Setting of synchronous data acquisition by status 2.
2. Programming of the R-counter, status 1 (optional)-data is being loaded into
shadow registers.
3. Programming of the N- or N/A-counter-data is being loaded into shadow reg-
isters, the EN-signal starts the synchronous loading procedure.
4. Synchronous programming – which means data transfer of all data from the
shadow registers to the data registers – takes place at that point in time
when the respective counter reaches “zero + 1”, the maximum repetition rate
for channel change is therefore fFI:N.
5. Transfer of status 1 information into the corresponding data register is tied
to the N-counter loading, but follows the loading of the N-data register in the
distance of one N-counter dividing ratio, this guarantees that for example a
new PD-current value becomes valid at the same time when the counters
are loaded with the new data.
Synchronous avoids additional phase error caused by programming. Synchro-
nous data acquisition is of especial advantage, when large steps in frequency
are to be made in a short time. For this purpose a high reference frequency can
be programmed in order to achieve rapid – “rough” – transient response. This
method increases the fundamental frequency nearly by the square route of the
reference frequency relation. When rough lock is achieved, another synchro-
nous data transfer is needed to switch back to the original channel spacing. A
“fine” lock in will finish the total step response. It may not be necessary to
change reference frequency, but it make sense to perform synchronous data
acquisition in any case. Especially for GSM, PCN, PCS, DECT, DAMPS, PHP
systems the synchronous mode should be used to get best performance of the
PMB 2304R.
Standby Condition:
The PMB 2304R has two standby modes (standby 1, 2) to reduce the current
consumption.
Standby 1 switches off the whole circuit, the current consumption is reduced
below 1 µA.
Standby 2 switches off the counters, the charge pump and the outputs, only the
preamplifiers stay active.
For the influence on the output signals see standby table (5-10).
fRN, fVN, ΦRN, ΦVN are the inverted signals of fR, fV,ΦR, ΦV.
Wireless Components
3 - 8
Specification, June 2002
4
Applications
Contents of this Chapter
4.1 PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Application Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
PMB 2304R
preliminary
Applications
4.1 PCB Layout
oben.wmf
Figure 4-1
Top Side
unten.wmf
Figure 4-2
Bottom Side
Wireless Components
4 - 2
Specification, July 1999
PMB 2304R
preliminary
Applications
4.2 Application Board
stromlauf.wmf
Figure 4-3
Application board
Wireless Components
4 - 3
Specification, July 1999
PMB 2304R
preliminary
Applications
4.3 Bill of material
Table 4-1
Nr
1
Reference
C1
Symbol name
CAP
Technology
10p
2
C2
CAPELK
CAP
4µ7
3
C3
10p
4
C4
CAP
10p
5
C5
CAP
10p
6
C6
CAP
220pF
7
C7
CAP
CAP
330pF
8
C8
30pF
9
C9
CAP
100p
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C10
C11
C12
C13
C14
C15
C16
C17
C18
IC1
IC2
J1
CAP
100n
CAP
100p
CAP
100n
CAPELK
CAP
4µ7
5.6nF
CAP
150p
CAP
10nF
CAP
1nF
CAPELK
PMB2314T
PMB2305
CON-5
JUMP-2SMD0603
JUMP-2SMD0603
VCO2
4µ7
PMB2314T
PMB2304R
5 Pin
J2
JUMPER_2SMD06031
J3
JUMPER_2SMD06031
N2
1500MHz
10k
R1
RES
R2
RES
10k
R3
R4
R5
R6
R7
R8
RES
10k
RES
4k7
RES
4k7
RES
4k7
RES
27k
RES
124k
Wireless Components
4 - 4
Specification, July 1999
PMB 2304R
preliminary
Applications
33
34
35
36
37
38
39
40
41
42
43
44
45
R9
RES
RES
RES
RES
RES
RES
RES
RES
RES
SMA
SMA
SMA
SMA
8.2k
18
R10
R11
R12
R13
R14
R15
R16
R17
56
18
18
47
10
10
22k
SMA_stehend
-
SMA_stehend
SMA_stehend
SMA_stehend
X1
X2
Wireless Components
4 - 5
Specification, July 1999
5
Reference
Contents of this Chapter
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3 Serial Control Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4 Programming Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.5 Pulse Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.6 Serial Control Data Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.7 Diagram Input Sensitivity FI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
PMB 2304R
preliminary
Reference
5.1 Electrical Data
5.1.1 Absolute Maximum Range
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Range
Parameter
Symbol
Limit Values
Unit
Remarks
min
max
Supply Voltage
VDD
V1
-0.3
-0.3
6
VDD + 0.3
VDD
V
Input Voltage
V
Output Voltage
VQ
PQ
Ptot
TA
GND
V
Power dissipation per output
Total power dissipation
Ambient temperature
Storage temperature
Thermal Resistance
10
mW
mW
°C
°C
K/W
300
-40
-50
85
in operation
Tstg
125
R
180
thJA
ESD Integrity except @Pin 12
(PD) (according to MIL833
Method 3015.7)
V
1
KV
ESD
ESD
ESD Integrity except @Pin 12
(PD) (according to MIL833
Method 3015.7)
V
400
V
Wireless Components
5 - 2
Specification, June 2002
PMB 2304R
preliminary
Reference
5.1.2 Operating Ratings
Within the operating ratings the IC operates as described in the circuit descrip-
tion. The AC/DC characteristic limits are not guaranteed.
Table 5-2 Operating Ratings, Supply Voltage V
= 2.7 V .. 4.5 V, Ambient temp. T
= -30°C ... + 85°C
AMB
VCC
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
2.7
max
5.5
Supply Voltage
VDD
V
Input frequency dual
ƒFI
0.1
0.1
0.1
65
220
90
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
VDD = 4.5...5.5V
VDD = 4.5...5.5V
VDD = 4.5...5.5V
VDD = 4.5...5.5V
VDD = 2.7V
Input frequency single HF-mode
Input frequency single LF-mode
Input reference frequency
Input frequency dual mode
Input frequency single HF-mode
Input frequency single LF-mode
Input reference frequency
ƒF
I
ƒFI
ƒRI
ƒFI
ƒFI
ƒFI
ƒRI
100
30
0.1
0.1
0.1
90
VDD = 2.7V
35
VDD = 2.7V
20
VDD = 2.7V
PD-output current
PD-output voltage
/ IPD
4
mA
V
VPD
0.5
0.5
-40
VDD - 0.5
VDD = 4.5- 5.5V
VDD = 2.7V
VPD
PD-output voltage
VDD - 0.5
c
Ambient temperature
TA
85
°C
5.1.3 Typical Supply Current IDD
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either VDD or VSS
.
Table 5-3 Typical Supply Current I
DD
Parameter
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
2.7
max
5.5
Supply voltage
Supply current:
VDD
5
V
ƒFI = 50MHz
VF = 150mVrms
single mode HF
IDD
IDD
IDD
IDD
1.63
1.76
0.11
2.6
2.94
3.17
0.75
1
mA
mA
mA
µA
I
ƒRI = 10MHz
dual mode
standby 2
standby 1
2.80
0.62
VRI = 150mVrms
I
PD = 0.25mA
Iref = 100 µA
Wireless Components
5 - 3
Specification, June 2002
PMB 2304R
preliminary
Reference
5.1.4 AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified sup-
ply voltage and ambient temperature range. Typical characteristics are the median of the
production.
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 °C, Supply Voltage VVCC = 2.7 .. 4.5V
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Input Signals DA, CLK, EN (with internal pull-up resistors)
0.7- VDD
1.1
1.2
H-input voltage
L-input voltage
Input capacity
H-input current
L-input current
VIH
VIL
CI
VDD
V
0.3- VDD
V
5
pF
µA
µA
1.3
1.4
IH
10
VI = VDD = 5.5V
VI = GND
IL
-60
Input Signal RI
Input voltage
Input voltage
Slew rate
mVrms
mVrms
ƒ = 4...100MHz, VDD = 4.5V
ƒ = 4...30MHz, VDD = 2.7V
2.1
2.2
2.3
VI
VI
100
100
4
V/µs
pF
VDD = 2.7...5.5V
Input capacity
H-input current
L-input current
CI
IH
IL
3
2.4
2.5
30
µA
VI = VDD = 5.5V
VI = GND
-30
µA
Input Signal FI (dual mode)
Input voltage
mVrms
mVrms
ƒ = 4...65MHz, VDD = 4.5V
ƒ = 10...25MHz, VDD = 2.7V
3.1
3.2
3.3
VI
VI
180
50
4
Input voltage
Slew rate
V/µs
pF
VDD = 2.7...5.5V
Input capacity
CI
IH
IL
3
3.4
3.5
H-input current
L-input current
30
µA
VI = VDD = 5.5V
VI = GND
-30
µA
Input Signal FI (single HF-mode)
mVrms
mVrms
mVrms
ƒ = 4...200MHz, VDD = 4.5V
ƒ = 4...90MHz, VDD = 2.7V
ƒ = 10...40MHz, VDD = 4.5V
4.1
4.2
4.3
4.4
Input voltage
Input voltage
Input voltage
Slew rate
VI
VI
VI
200
200
50
4
V/µs
pF
VDD = 2.7...5.5V
Input capacity
H-input current
L-input current
CI
IH
IL
3
4.5
4.6
30
µA
VI = VDD = 5.5V
VI = GND
-30
µA
Wireless Components
5 - 4
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 °C, Supply Voltage VVCC = 2.7 .. 4.5V
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
Input Signal FI (single LF-mode)
mVrms
mVrms
ƒ = 4...90MHz, VDD = 4.5V
ƒ = 4...35MHz, VDD = 2.7V
5.1
5.2
5.3
Input voltage
Input voltage
Slew rate
VI
VI
100
100
4
V/µs
pF
VDD = 2.7...5.5V
Input capacity
H-input current
L-input current
CI
IH
IL
3
5.4
5.5
30
µA
VI = VDD = 5.5V
VI = GND
-30
µA
Output Current /IPD/
Current mode:
"0.175 mA"
"0.25 mA"
"0.35 mA"
"0.5 mA"
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
IPROG
IPROG
IPROG
IPROG
IPROG
IPROG
IPROG
IPROG
-20%
-20%
-20%
-20%
-20%
-15%
-15%
-10%
0.175
0.25
0.35
0.5
+20%
+20%
+20%
+20%
+20%
+15%
+15%
+10%
1
mA
mA
mA
mA
mA
mA
mA
mA
nA
VDD = 4.5...5.5V
VPD = VDD/2
IREF = 100µΑ
"0.7 mA"
0.7
"1.0 mA"
1.0
"1.4 mA"
1.0
VDD = 4.5V
"2.0 mA"
2.0
Standby"
/IPD
/
0.1
Output Tolerance IPD
∆IPD / IPROG
VPD = VDD/2, VDD = 2.7V
7.1
7.2
-10%
-5%
+0%
1.3
VPD = 0.5...2.2V, VDD = 2.7V
∆IPD / IPROG
±2.5%
Input Voltage MFO2 (Internal charge pump mode)
VDD = 2.7...5.5V
IREF = 100µA
8.1
VREF
Reference voltage
0.9
1.1
V
Output Signal MFO1 (push pull)
VDD = 4.5...5.5V,IQH= -2mA
VDD = 4.5...5.5V,IQL= 2mA
VDD = 2.7V,IQH=-1.2mA
VDD = 2.7V,IQL=1.2mA
VDD = 4.5...5.5V,CI= 10pF
VDD = 4.5...5.5V,CI= 10p
VDD = 2.7V,CI=10pF
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
H-output voltage
L-output voltage
H-output voltage
L-output voltage
Rise time
VQH
VQL
VQH
VQL
tR
VDD - 1
VDD - 1
V
1
V
V
1
V
2.5
2.0
5
10
10
12
12
ns
ns
ns
ns
Fall time
tF
Rise time
tR
VDD = 2.7V,CI=10pF
Fall time
tF
4
Wireless Components
5 - 5
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-4 AC/DC Characteristics with Ambient temp. Tamb= -20 .. 85 °C, Supply Voltage VVCC = 2.7 .. 4.5V
Symbol
Limit Values
Unit
Test Conditions
L
Item
min
typ
max
1
Output Signal MFO2 (push pull)
VDD = 4.5...5.5V,IQH= 2mA
VDD = 4.5...5.5V,IQL= 2mA
VDD = 2.7V,IQH= 1.2mA
VDD = 2.7V,IQL= 1.2mA
VDD = 4.5...5.5V,CI= 10pF
VDD = 4.5...5.5V,CI= 10p
VDD = 2.7V,CI=10pF
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
H-output voltage
L-output voltage
H-output voltage
L-output voltage
Rise time
VQH
VQL
VQH
VQL
tR
VDD - 1
VDD - 1
V
V
V
1
V
2
2
3
3
10
10
10
10
ns
ns
ns
ns
Fall time
tF
Rise time
tR
VDD = 2.7V,CI=10pF
Fall time
tF
Output Signal LD (n-channel open drain)
VDD = 2.7...5.5V,
IQL = 0.3mA
11.1
L-output voltage
VQL
0.4
V
11.2
11.3
11.4
VDD = 2.7...5.5V
H-output current
Fall time
IQH
tF
5
µA
ns
ns
VDD = 4.5...5.5V,CI=10pF
3
5
10
12
VDD = 2.7V,C =10pF
Fall time
tF
I
Output Signal MOD (push pull)
VDD-0.4
VDD = 4.5...5.5V,
IQH = -0.5mA
12.1
12.2
H-output voltage
VQH
V
V
VDD = 4.5...5.5V
IQL = 0.5mA
L-output voltage
VQL
0.4
VDD-0.4
VDD = 2.7V, IQH = - 0.3mA
VDD = 2.7V, IQL= 0.3mA
VDD = 4.5...5.5V, CI = 5pF
VDD = 4.5...5.5V, CI = 5pF
VDD = 4.5...5.5V, CI = 5pF
12.3
12.4
12.5
12.6
12.7
H-output voltage
L-output voltage
Rise time
VQH
VQL
tR
V
0.4
3
V
1.5
1.3
8
ns
ns
ns
Fall time
tF
3
Propagation delay
time H-L to FI
tDQHL
12
VDD = 4.5...5.5V, CI = 5pF
12.8
Propagation delay
time L-H to FI
tDQHL
8
12
ns
12.9
Rise time
Fall time
tR
3.2
2
5
5
ns
ns
ns
VDD = 2.7V, C = 5pF
I
12.10
12.11
tF
VDD = 2.7V, C = 5pF
I
Propagation delay
time H-L to FI
tDQHL
15
VDD = 2.7V, C = 5pF
I
12.12
Propagation delay
time L-H to FI
tDQHL
15
ns
VDD = 2.7V, C = 5pF
I
This value is only guaranteed in lab.
Wireless Components
5 - 6
Specification, June 2002
PMB 2304R
preliminary
Reference
5.2 Phase detector outputs
RI
fR
(RI:R)
MOD A
FI
MOD B
fV
(FI:N)
P-Channel
Tri-State.
PD
Polarity
pos.
N-Channel
P-Channel
Tri-State.
PD
Polarity
neg.
N-Channel
LD
ΦR
Polarity pos.
(internal Signal)
ΦV
Polarity pos.
(internal Signal)
Frequency f = f
Frequency f < f
Frequency f > f
V R
V
R
V
R
or f lagging
or f leading
V
V
Figure 5-1
Phase detector output signals
Wireless Components
5 - 7
Specification, June 2002
PMB 2304R
preliminary
Reference
5.3 Serial Control Data Format
Table 5-5 Serial Control Data Format (status 1,2)
Status 1
Status 2
0
1
Data acquisition mode
Mode 1
1
2
asynchronous
synchronous
see table
Mode 2
3
see table
PD-polarity
4
negative
standby
standby
positive
active
active
Standby 1
5
Standby 2
6
Anti-backlash pulse width 1
Anti-backlash pulse width 2
Preamplifier select
Single / dual mode
7
see table
see table
see table
8
9
10
single
low
dual
high
1
2
3
4
5
6
Port 1
11
12
13
14
15
16
PD-current 1
PD-current 2
PD-current 3
see table
see table
see table
0
0
Address
0
1
EN
EN
Wireless Components
5 - 8
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-6 Serial Control Data Format
(N-, N/A-counter)
Table 5-7 Serial Control Data Format
(R-counter)
Dual
Mode
Single
Mode
1
2
3
4
5
6
7
MSB
1
2
3
4
5
6
7
MSB
A-
Counter
LSB
8
MSB
MSB
1
2
8
R-
Counter
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
EN
3
10
11
12
13
14
15
16
17
18
EN
4
5
6
N-
Counter
7
8
LSB
1
9
10
11
12
13
14
15
16
EN
Address
1
LSB
LSB
1
0
1
0
Address
Wireless Components
5 - 9
Specification, June 2002
PMB 2304R
preliminary
Reference
5.4 Programming Tables
Table 5-8
Status Bits
Anti-
Backlash
Pulse Width 2 Pulse Width 1
Anti-
Backlash
tW (typ.)
[ns]
0
0
1.3
VDD = 5V
0
1
1
1
0
1
5
10
13*
not recommended
any application where
continuous lock detect is required
* No ABL gating performed
* In general the shortest anti-backlash pulse gives the best system performance
.
Table 5-9
Status Bits
Preamplifier Function Mode
Single/Dual Mode
Preamplifier Select
0
0
1
0
1
0
FI-input frequency,single HF-mode
FI-input frequency,single LF-mode
FI-input frequency, dual-mode, FI-
trigger edge LH, MOD A
1
1
FI-input frequency, dual-mode, FI-
trigger edge HL, MOD B
Table 5-10Standby Table
Output Pins
Status
MFO1
MFO2
LD
PD
MOD
Φ
Φ
VN
V
Standby 1
Standby 2
low
low
high
high
high
high
resistive
resistive
tristate
tristate
low
low
Wireless Components
5 - 10
Specification, June 2002
PMB 2304R
preliminary
Reference
Table 5-11
Status Bits
PD-Current Mode
PD-Current 3
PD-Current 2
PD-Current 1
Ipd/mA
0.175
0.25
0.35
0.5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.7
1
1.4
2
Table 5-12
Status Bits
Multifunction Output
Mode 2
Mode 1
MFO 1
MFO 2
Remarks
0
0
1
0
1
fRN
fVN
test mode
0
1
1
Φ
Φ
external charge pump mode 1
external charge pump mode 2
internal charge pump mode
V
RN
Φ
Φ
VN
RN
Port 1
Iref
5.5 Pulse Diagram
50%
50%
FI
tDQLH
tDQLH
tDQLH
tDQLH
VQH
VQL
MOD A
50%
50%
tF
tR
VQH
VQL
MOD B
50%
50%
tF
tR
Figure 5-2
Pulse diagram
Wireless Components
5 - 11
Specification, June 2002
PMB 2304R
preliminary
Reference
5.6 Serial Control Data Input Timing
tR
tF
tWHCL
VIH
CLK
VIL
tDS
VIH
VIL
DA
EN
tCLE
tECL
VIH
VIL
tWHEN
VIH
VIL
MFO1
MFO3
tDEP
Figure 5-3
Serial Control Data Input Timing
Table 5-13
Parameter
Symbol
Limit Values
Unit
min
max
ƒCL
Clock frequency
12
MHz
ns
tWHCL
tDS
H-pulsewidth (CL)
40
20
20
20
40
Data setup
ns
tCLE
Setup time-clock enable
Setup time enable-clock
H-pulsewidth (enable)
Rise, fall time
ns
tECL
ns
tWHEN
tR, tF
tDEP
ns
10
1
µs
Propagation delay time EN-PORT
µs
Wireless Components
5 - 12
Specification, June 2002
PMB 2304R
preliminary
Reference
5.7 Diagram Input Sensitivity FI
Figure 5-4
Input sensitivity FI (single HF-mode)
Wireless Components
5 - 13
Specification, June 2002
相关型号：
©2020 ICPDF网 联系我们和版权申明