PSB4600 [INFINEON]
PCI Bus Controller, CMOS, PQFP100, TQFP-100;
| 型号： | PSB4600 |
| 厂家： | 
Infineon |
| 描述： | PCI Bus Controller, CMOS, PQFP100, TQFP-100 时钟 PC 外围集成电路 |
| 文件： | 总17页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICs for Communications
PCI Interface for Telephony/Data Applications
PITA
PSB 4600 Version 1.0
Product Overview 03.98
DS 1
PSB 4600
Revision History:
Current Version: 03.98
None
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Group Offices in Germany or the Siemens Companies and Representatives worldwide:
see our webpage at http://www.siemens.de/Semiconductor/address/address.htm.
Edition 03.98
Published by Siemens AG,
HL SP,
Balanstraße 73,
81541 München
© Siemens AG 1998.
All Rights Reserved.
Attention please!
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applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
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question please contact your nearest Siemens Office, Semiconductor Group.
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Packing
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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-
dangered.
PSB 4600
Overview
1
Overview
The PITA is a cost-effective PCI bus interface chip for a serial or parallel microcontroller
interface. Because of its different interface modes, it can be used to provide a seamless
interface with existing ICs, including the SIEMENS Communications IC portfolio. This
results in complete chipsets for PCI ISDN cards, PCI hardware modems and PCI
software modems.
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PCI Interface for Telephony/Data Applications
PITA
PSB 4600
CMOS
Version 1.0
1.1
Features
• 32-bit 33 MHz PCI 2.1-compliant Master/Target
interface supporting a serial or parallel
microcontroller interface
• Compliant with PC 98
• Compliant with PCI Bus Power Management
Interface, Rel. 1.0. Supports all Power Management
states: D0, D1, D2, D3hot and D3cold
• Uses 5 and 3.3 Vdc power
P-TQFP-100
• Supports PCI IDs: Device, Vendor, Subsystem and Subsystem Vendor
• Serial controller interface supports IOM-2 and serial interface to the ALIS chipset
family
• Parallel Microcontroller interface with chip select logic to support up to three external
components
• DMA controller for serial communication
• 4 general purpose I/Os, with interrupt capability
• 16-word FIFOs for each direction
• SPITM interface for optional EEPROM, which can be used to load customized PCI
configuration data
• Glueless interface to all SIEMENS HL Communications ICs, e.g. IPAC, 3PAC,
ISAR34, ISAC-S, INTC-Q, SCOUT, IEC-Q, and the ALIS-D/ALIS-A chipset
Type
Package
PSB 4600
P-TQFP-100
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PSB 4600
Overview
1.2
Logic Symbol
Parallel Microcontroller Interface
CS#(2:0)
PAD(7:0) PA(7:0)
VDD5
VDD3
VSS
+5 V
+3.3 V
0 V
GP3
General
Purpose
Interface
GP2 / EEPROM SCK
GP1 / EEPROM SI
GP0 / EEPROM SO
ECS#
SRST#
FSC
DCL
RXD
TXD
Serial
Interface
EEPROM
Interface
ELD
AD(31:0) C/BE#(3:0)
PCI
Interface
Figure 1 Logic Symbol of the PITA ("#" Indicates Active Low)
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PSB 4600
Overview
1.3
Typical Applications
The PITA provides a PCI interface supporting a serial or parallel microcontroller
interface, including communications applications such as analog software modems and
hardware ISDN modems.
PSB 2115
IPAC
S-Interface
Microcontroller
Interface
PSB 4600
PITA
SPI
EEPROM
PCI Bus
Figure 2 ISDN S-Interface Application with the IPAC (the EEPROM is Optional)
PSB 2113
3PAC
PSB 21911
IEC-Q TE
U-Interface
Microcontroller
Interface
PSB 4600
PITA
SPI
EEPROM
PCI Bus
Figure 3 ISDN U-Interface Application with the 3PAC and IEC-Q TE
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PSB 4600
Overview
PSB 4596
ALIS-D
PSB 4595
ALIS-A
a/b
Data/Control
Interface
PSB 4600
PITA
SPI
EEPROM
PCI Bus
Figure 4 Software Modem Using the ALIS-A and ALIS-D with PCI Interface
The ALIS chipset provides a transformer-less and adaptable analog front-end for a host-
based software modem. In the ALIS application, a codec or a second ALIS chipset can
be multiplexed onto the Data/Control Interface.
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PSB 4600
Overview
PSB 7115
ISAR34
PEB 2081
SBCX
IOM-2
S-Interface
PSB 21911
IEC-Q TE
U-Interface
PSB 4600
PITA
SPI
EEPROM
PCI Bus
Figure 5 ISDN Hardware Modem Using the ISAR34: Two Interfaces Shown
The ISAR34 provides the datapump for an ISDN modem. In the figure above, both S-
and U-Interfaces are shown, but either can be omitted.
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PSB 4600
Pin Description
2
Pin Description
TEST#
GP3
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PA0
PA1
2
GP2
3
PA2
GP1
4
PA3
GP0
5
PA4
CLKRUN#
PME#
RST#
CLK
6
PA5
7
PA6
8
PA7
9
CS#1
CS#2
INTA#
VDD3
VSS
VDD5
VDD3
AD0
GNT#
REQ#
VDD3
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PITA
M0008
P-TQFP-100-1
VDD5
VDD3
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
C/BE#3
IDSEL
AD1
AD2
AD3
AD4
AD5
AD6
AD7
C/BE#0
AD8
Figure 6 Pin-out for the PITA ("#" Indicates Active Low)
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PSB 4600
Pin Description
Pin Symbol
No.
Input (I)
Function
Output (O)
Open Drain
(OD)
Tri-State
Output (OTS)
9
8
CLK
I
PCI Clock: operates up to 33 MHz
PCI Reset (active Low)
RST
I
AD(31:0)
C/BE(3:0)
I/O
I/O
I/O
O, OD
I
PCI Address/Data Bus
PCI Bus Command/Byte Enable (active Low)
PCI Parity
42 PAR
65 INTA
25 IDSEL
35 FRAME
36 IRDY
37 TRDY
38 DEVSEL
39 STOP
11 REQ
PCI Interrupt A (active Low)
PCI Initialization Device Select
PCI Cycle Frame (active Low)
PCI Initiator Ready (active Low)
PCI Target Ready (active Low)
PCI Device Select (active Low)
PCI Stop (active Low)
I/O
I/O
I/O
I/O
I/O
O, OTS
I
PCI Request (active Low)
10 GNT
PCI Grant (active Low)
40 PERR
41 SERR
I/O
O, OD
O, OD
I
PCI Parity Error
PCI System Error (active Low)
PCI Power Management Event (active Low)
PCI Mobile clock control (active Low)
Parallel Interface Reset.
7
6
PME
CLKRUN
76 PRST
CS(2:0)
O
O
Parallel Interface Chip Select for
microcontrollers (active Low)
PAD(7:0)
PA(7:0)
I/O
Parallel Interface Address/Data signal
Parallel Interface Address signal
O, OTS
91 ALE
86 WR
85 RD
O
O
O
Parallel Interface Address Latch Enable
Parallel Interface Write (active Low)
Parallel Interface Read (active Low)
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PSB 4600
Pin Description
Pin Symbol
No.
Input (I)
Function
Output (O)
Open Drain
(OD)
Tri-State
Output (OTS)
92 INT0
98 INT1
I
Parallel Interface standard active Low
Interrupt for applications (active Low)
I
Parallel Interface standard active High
Interrupt for applications.
93 SRST
97 FSC
O
I
Serial Interface Reset (active Low)
Serial Interface Frame Synchronization
signal.
94 DCL
95 RXD
96 TXD
I/O (note 1)
Serial Data Clock
I
Serial Interface Input for Serial data.
Serial Interface Output for Serial data.
General Purpose I/O Pin 3 (note 2)
O, OD
I/O (note 2)
I/O
2
3
GP3
GP2
General Purpose I/O Pin 2. Also used as
Serial EEPROM Interface pin SCK.
4
5
GP1
GP0
I/O
I/O
I
General Purpose I/O Pin 1. Also used as
Serial EEPROM Interface pin SI.
General Purpose I/O Pin 0. Also used as
Serial EEPROM Interface pin SO.
99 ELD
100 ECS
’1’: EEPROM configuration is enabled.
’0’: EEPROM configuration is disabled.
O
I
EEPROM Chip Select (SPITM) signal (active
Low).
1
TEST
This must be pinned to ’1’.
Notes:
1) The direction of DCL is controlled by programming.
2) GP3 is driven High during automatic EEPROM configuration if ELD is ’1’.
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PSB 4600
Functional Description
3
Functional Description
Functional Overview
3.1
The PITA provides a Peripheral Component Interconnect (PCI) bus interface for all
current SIEMENS communication ICs. The Parallel Interface Control supports up to
three external devices. The Serial Interface is controlled by the internal DMA Controller;
serial communications use Transmit and Receive FIFOs.
3.2
Block Diagram
EEPROM
Control
SPITM Interface
Parallel
Interface
Control
Parallel
Microcontroller
Interfaces
PCI Bus
DMA
Controller
Serial
Interface
Control
Serial
Microcontroller
Interface
Tx FIFO
Rx FIFO
General
Purpose
Interface
Figure 7 Block Diagram of the PITA
3.3
Functional Blocks
PCI Bus Control
3.3.1
The PCI Bus Control provides a 32-bit interface at speeds up to 33 MHz. It provides Bus
Master DMA capability for data passing through the Serial Interface, and Target
capability for data passing through the Parallel Interface. It supports the D0, D1, and D3
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PSB 4600
Functional Description
Power Management states by default, and can be configured to support the D2 state as
well.
3.3.2
Parallel Interface Control
The Parallel Microcontroller Interface can support chips with a SIEMENS/Intel standard
parallel interface, including ISDN interfaces and ISDN hardware modems.
3.3.3
Serial Interface Control
The Serial Interface can support chips with a serial interface, including analog modem
and IOM-2 applications. In ALIS mode, it can support up to two multiplexed devices (e.g.,
two ALIS chips or an ALIS plus a second codec). Transmit and receive data are held in
separate 16-word FIFOs.
3.3.4
EEPROM Control
The EEPROM is an optional feature that can be used to customize the PITA
configuration at start-up. It can provide additional information, such as the Subsystem ID
and Subsystem Vendor ID; and the enabling of the D2 Power Management state.
3.3.5
General Purpose Interface
The General Purpose I/O pins can be configured to act as input, output, or interrupt input
pins. At start-up, they are used for the EEPROM interface.
3.4
Operating Modes
The PITA can provide the PCI interface for both a Serial Interface application, such as
an analog modem, and an ISDN interface; but these two cannot both be in operation at
the same instant.
The Serial Interface can operate in six different modes, to support various configurations
of the ALIS chipset and the IOM-2 applications. These are described more fully in the
section on the Serial Interface, Section 5.3.
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PSB 4600
Operational Description
4
Operational Description
The function of the PITA is to pass communications from the PCI bus to the
communications ICs and vice versa. For communications through the Serial Interface,
the DMA capability and FIFOs are provided to protect against stalls on the PCI bus
affecting the modem communications protocols. Communications using the Parallel
Interface do not require this, because the ISDN chips using this have their own FIFOs.
An EEPROM interface is provided to allow the optional use of an EEPROM to customize
the PCI configuration space beyond the defaults provided.
4.1
Operating States
4.1.1
Power Management States
The PITA supports by default the following Power Management states: D0, D1, and D3.
The possibility of the D2 state can also be configured by the EEPROM.
The D0 state is the active state. After a system reset, the PITA will be in D0, and will
respond only to configuration accesses by the host, the PCI Master function being
disabled.
The D1 state is a "light sleep" state, in which the PITA responds only to PCI configuration
accesses, but access to the memory-mapped locations defined by the Base Address
Registers is disabled. The only PCI bus operation the PITA can initiate in D1 is assertion
of the PME signal. It can be put into D1 by the host.
The D2 state is an optional "sleep" state, in which the PITA responds only to PCI
configuration accesses, but access to the memory-mapped locations defined by the
Base Address Registers is disabled. The only PCI bus operation the PITA can initiate in
D2 is assertion of the PME signal. It can be put into D2 by the host.
The D3hot state is a "powered down" state, in which it responds only to PCI configuration
accesses. In this state, power and clock are still available to the PITA, but it can initiate
no PCI bus operation. The only legal transition from D3hot is to D0, via a system reset or
a software reset. This will result in a full re-configuration of the PCI system.
The D3cold state is a "power off" state, when the PCI bus power Vcc has been
disconnected.
5
Interface Description
PCI Bus Interface
5.1
This interface includes all mandatory pins for 32-bit 33 MHz PCI Bus Master and Target
functionality. In addition, it includes three optional pins: the interrupt INTA; the Power
Management pin PME; and the Mobile Clock Control pin CLKRUN.
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PSB 4600
Interface Description
The PITA provides Bus Master DMA capability for data passing through the Serial
Interface; and Target capability for data passing through the Parallel Interface.
Specific aspects of the PCI interface are controlled by the PCI Configuration Space,
which is accessed at start-up. The Subsystem ID and Subsystem Vendor ID can be set
by pin-strapping; additionally, the optional EEPROM will be accessed after a system
reset, and can reset the Subsystem ID and Subsystem Vendor ID. The EEPROM re-
configuration can also over-ride the default to enable the D2 power management state.
The PITA uses Base Address Register 0 for the Application-Specific Registers.
5.2
Parallel Microcontroller Interface
This is an 8-bit SIEMENS/Intel standard microcontroller interface, which can operate in
either multiplexed or demultiplexed mode. It includes two interrupts for applications: the
active Low INT0 and the active High INT1. It can be connected to the IPAC, 3PAC,
ISAR34, ISAC-S, INTC-Q, HSCX, or SCOUT, and supports up to three devices,
including the glue logic.
The PITA uses memory mapping to Base Address Register 1 to address devices
attached through the Parallel Interface.
5.3
Serial Microcontroller Interface
This interface can be connected to any device with an IOM-2 interface, such as the
ISAC-S, IEC-Q, etc. It can also be connected to an ALIS-D.
The Serial Interface can operate in several modes:
- ALIS modes for a software modem application.
- ALIS mode with an additional codec or a second ALIS chipset can be supported.
- IOM-2 modes for ISDN applications in which the HDLC controller is provided by the
host. These modes can provide: the B1 and B2 channels of IOM-2 channel 0; the
complete IOM-2 channel 0; the B1 and B2 channels of IOM-2 channel 0 plus the IC1 and
IC2 channels of IOM-2 channel 1.
5.4
EEPROM Interface
Three pins are used to provide a SPITM-compatible serial interface to a 256 x 8 bit
EEPROM; these also do double-duty as part of the General Purpose Interface. Two
other pins are also used to select the EEPROM chip and to enable/disable the automatic
re-configuration of the Configuration Space by the EEPROM. (See Table 1.) This would
occur after a system reset.
The contents of the EEPROM can be programmed by writing a command to the
EEPROM Control Register and initiating a read/write transaction to the EEPROM.
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PSB 4600
Interface Description
5.5
General Purpose Interface
There are four General Purpose I/O pins that can be configured to act independently as
inputs, outputs, or interrupts. Three of these pins also do double-duty as the EEPROM
interface.
Pin
General
PurposeI/O
Function
EEPROM
SPITM
Function
GP0
GP1
GP2
GP3
ELD
I/O/Int.
I/O/Int.
I/O/Int.
I/O/Int.
-
SO
SI
SCK
-
Enables auto-configuration from
EEPROM after System Reset
ECS
-
Chip select
Table 1
Multiple Use of General Purpose I/O Pins
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PSB 4600
Package Outlines
6
Package Outlines
P-TQFP-100
(Plastic Thin Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
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