Q-67106-H6514 [INFINEON]
PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2; PLL频率合成器PMB2306R / PMB2306T 2.2版
| 型号： | Q-67106-H6514 |
| 厂家： | 
Infineon |
| 描述： | PLL-Frequency Synthesizer PMB2306R/PMB2306T Version 2.2 |
| 文件： | 总35页 (文件大小：760K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICs for Communications
PLL-Frequency Synthesizer
PMB2306R/PMB2306T Version 2.2
Data Sheet 02.97
T2306-0V22-D1-7600
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Previous Version: 01.94
Page
Page
Subjects (major changes since last revision)
(in previous (in new
Version)
14-15
Version)
19-20
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H-input current ,H: is changed from 10µA to 30µA and
L-input current ,L: is changed from -10µA to -30µA
26
26
&ORFNꢀIUHTXHQF\ ICL max. is changed from 10MHz to 12MHz;
+ꢉSXOVHZLGWKꢀꢎ&/ꢏ WWHCL min. is changed from 60ns to 40ns;
+ꢉSXOVHZLGWKꢀꢎHQDEOHꢏ WWHENmin. is changed from 60ns to 40ns;
18
19
18
19
Input reference frequency ICRIꢍ is changed from 20MHz to 22MHz
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Input voltage 9I: is changed from 20MHz to 22MHz
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This edition was realized using the software system FrameMaker .
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As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
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Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2 with the express written approval of the Semiconductor Group of Siemens AG.
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.1
1.2
1.3
1.4
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Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Typical Supply Current ,DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.1
3.2
3.3
ꢐ
4.1
4.2
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Plastic-Package, P-TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Plastic-Package, P-DSO-14-1(SMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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• Low operating current consumption
(typically 3.5 mA)
• High input sensitivity, high input frequencies
(220 MHz)
• Extremely fast phase detector without dead zone
• Linearization of the phase detector output by current
sources
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• Synchronous programming of the counters
(n-, n/a-, r-counters) and system parameters
• Fast modulus switchover for 65-MHz operation
• Switchable modulus trigger edge
• Large dividing ratios for small channel spacing
A scaler 0 to 127
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N scaler 3 to 16.380
R scaler 3 to 65.535
• Serial control (3-wire bus: data, clock, enable) for fast programming (Imax ~ 10 MHz)
• Switchable polarity and phase detector current programmable
• 2 Multifunction outputs
• Digital phase detector output signals (e.g. for external charge pump)
• Irn, Ivn outputs of the R and N scalers
• Port 1 output (e.g. for standby of the prescaler)
• External current setting for PD output
• Lock detect output with gated anti-backlash pulse (quasi digital lock detect)
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PMB 2306T
PMB 2306T
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V2.2
Q67106-H6423
P-DSO-14 (SMD, Tape & Reel)
P-TSSOP-16 (SMD, T&R)
V2.2
Q-67106-H6514 (T&R)
The PMB 2306T PLL is a high speed CMOS IC, especially designed for use in battery powered
radio equipment and mobile telephones. The primary applications will be in digital systems e.g.
GSM, PCN, ADC, JDC and DECT systems. The wide range of dividing ratios also allows application
in modern analog systems
Semiconductor Group
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DA
V
DD1
CLK
PD
V
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MOD
NC
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9DD
9SS
9DD
Positive supply voltage for serial control logic.
6
6
Ground for serial control logic.
2
2
Positive supply voltage for the preamplifiers, counters, phase
detector and charge pump.
11
13
1
9SS
Ground for the preamplifiers, counters, phase detector and
charge pump.
9
3
11
3
1
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ꢀ
EN
DA
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Enable line of the serial control with internal pull-up resistor.
When EN = H the input signals CLK and DA are disabled
internally. When EN = L the serial control is activated. The
received data are transferred into the latches with the positive
edge of the EN-signal.
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4
Serial data input with internal pull-up resistor. The last two bits
before the EN-signal define the destination address. In a byte-
oriented data structure the transmitted data have to end with
the EN-signal, i.e. bits to be filled in (don’t care) are transmitted
first.
CLK
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7
5
7
Clock line with internal pull-up resistor. The serial data are read
into the internal shift register with the positive edge (see pulse
diagram for serial data control).
MOD
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The modulus output is low at the beginning of the cycle. When
the a-counter has reached its set value, MOD switches to high.
When the n-counter has reached its set value, MOD switches to
low again, and the cycle starts from the top. When the prescaler
has the counter factor P or P+1 (P for MOD = H, P +1 for MOD
= L), the overall scaling factor is NP + A. The value of the a-
counter must be smaller than that of the n-counter. The trigger
edge of the modulus signal to the input signal can be selected
(see programming tables and MOD
A, B) according to the needs of the prescaler. In single modulus
operation and for standby operation in dual modulus operation,
the output is low.
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Input with highly sensitive preamplifier for 14-bit n-counter and
7-bit a-counter. With small input signals AC coupling must be
set up, where DC coupling can be used for large input signals.
RI
PD
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Input with highly sensitive preamplifier for 16-bit r-counter. With
small input signals AC coupling must be set up, where DC
coupling can be used for large input signals.
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10
12
Tristate charge pump output. The integrated, positive and
negative current sources can be programmed with respect to
their current density by means of the serial control. Activation
and deactivation depend on the phase relationship of the
scaled-down input signals FI:N, RI:R. (See phase detector
output waveforms.)
frequency IV <ꢀIR orꢀIV lagging:
p-channel current source
active
frequency IV > IR orꢀIR leading:
n-channel current source
active
frequency IV = IR and PLL locked: current sources are
switched off, PD-output is tristate
In standby mode the PD-output is set to tristate. The
assignment of the current sources to the output signals of the
phase detector can be swapped in it’s polarity, i.e. the sign of
the phase detector constant can be controlled.
LD
/RFNꢀ'HWHFWRUꢀ2XWSXW (open drain). Unipolar output of the
phase detector in the form of a pulse-width modulated signal.
The L-pulse width corresponds to the phase difference. Phase
differences < 20 ns are not indicated due to gating of the
antibacklash impuls. In the locked state the LD-signal is at
H-level. In standby mode the output is resistive.
14
16
Only for ABL status 11 no gating of ABL impulse is performed.
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0XOWLIXQFWLRQꢀ,ꢌ2ꢉ3LQ for the output signals IVN, ΦRN and the
input signal ,REF
.
– The signals ΦR and ΦV are the digital output signals of the
phase and frequency detector for use in external active
current sources (see phase detector output wave forms).
– The signals IRN and IVN are the scaled down signals of the
reference frequency and VCO-frequency. The L-time
corresponds to 1/IRI and 1/IFI respectively.
– In the port function the port 1 output signal is assigned to the
information of the status program. The output switches with
the rising edge of the
EN-signal. The standby mode does not affect the port
function.
– In the internal charge pump mode the input signal ,REF
determines the value of the PD-output current.
Reference current for charge pump:
,REF = (9DD – 9REF)/R1
= 100µA (tolerance of ±20% or less is recommended)
R1:see application circuit
ꢀꢀꢀꢀ9REF:see AC/DC characteristics
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The circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a
phase detector with charge pump output and a serial control logic. The setting of the
operating mode and the selection of the counter ratios is done serially at the ports CLK,
DA and EN.
The operating modes allow the selection of single or dual operation, asynchronous or
synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PD-
output current modes, polarity setting of the PD-output signal, adjustment of the trigger-
edge of the MOD-output signal, 2 standby modes and the control of the multifunction
outputs MFO1 and MFO2.
The reference frequency is applied at the RI-input and scaled down by the r-counter. It’s
maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and scaled
down by the n- or n/a-counter according to single or dual mode operation. The maximum
value at FI is 220 MHz at single-, and 65 MHz at dual mode operation.
The phase and frequency sensitive phase detector produces an output signal with
adjustable anti-backlash impulses in order to prevent a dead zone for very small phase
deviations. Phase differences of less than 100 ps can be resolved. In general the
shortest anti-backlash pulse gives the best system performance.
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Programming of the IC is done by a serial data control. The contents of the message are
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The PMB 2306T offers the possibility of synchronous data acquisition to avoid error
signals at the phase detector due to non-corresponding dividing factors in the counters
produced by asynchronous loading.
Synchronous programming guarantees control during changes of frequency or channel.
That means that the state of the phase detector or the phase difference is kept
maintained, and in case of “lock in”, the control process starts with the phase difference
“zero”.
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This is done as follows:
1.Setting of synchronous data acquisition by status 2.
2.Programming of the r-counter, status 1 (optional)-data is being loaded into shadow
registers.
3.Programming of the n- or n/a-counter-data is being loaded into shadow registers, the
EN-signal starts the synchronous loading procedure.
4.Synchronous programming – which means data transfer of all data from the shadow
registers to the data registers – takes place at that point in time when the respective
counter reaches “zero + 1”, the maximum repetition rate for channel change is
therefore IFI:N.
5.Transfer of status 1 information into the corresponding data register is tied to the n-
counter loading, but follows the loading of the n-data register in the distance of one n-
counter dividing ratio, this guarantees that for example a new PD-current value
becomes valid at the same time when the counters are loaded with the new data.
Synchronous avoids additional phase error caused by programming. Synchronous data
acquisition is of especial advantage, when large steps in frequency are to be made in a
short time. For this purpose a high reference frequency can be programmed in order to
achieve rapid – “rough” – transient response. This method increases the fundamental
frequency nearly by the square route of the reference frequency relation. When rough
lock is achieved, another synchronous data transfer is needed to switch back to the
original channel spacing. A “fine” lock in will finish the total step response. It may not be
necessary to change reference frequency, but it make sense to perform synchronous
data acquisition in any case. Especially for GSM, PCN, DECT, DAMPS, JDC, PHP
systems the synchronous mode should be used to get best performance of the PMB
2306T.
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The PMB 2306T has two standby modes (standby 1, 2) to reduce the current
consumption.
Standby 1 switches off the whole circuit, the current consumption is reduced below 1 µA.
Standby 2 switches off the counters, the charge pump and the outputs, only the
preamplifiers stay active.
The standby modes do not affect the port output signal. For the influence on the other
output signals VHHꢀVWDQGE\ꢀWDEOHꢃ
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test mode
ΦV
ΦRN
external charge pump mode 1
external charge pump mode 2
internal charge pump mode
ΦVN
ΦRN
Port 1
,
REF
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not recommended
13**
any application where
continuous lock detect required
*
In general the shortest anti-backlash pulse gives the best system performance.
** No ABL (Anti-Backlash-Pulse) gating performed. This means, that at the LD output the anti-backlash pulse
will appear. In the other cases the anti-backlash pulse will be surpressed at the LD output.
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FI-input frequency, single HF-mode
FI-input frequency, single LF-mode
FI-input frequency, dual mode, FI-trigger edge LH, MOD A
FI-input frequency, dual mode, FI-trigger edge HL, MOD B
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Standby 1
Standby 2
low
high
high
high
high
resistive
resistive
tristate
tristate
low
low
low
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0
1
Data acquisition mode
Mode 1
1
2
asynchronous synchronous
see table
Mode 2
3
see table
PD-polarity
4
negative
standby
standby
positive
active
active
Standby 1
5
Standby 2
6
Anti-backlash pulse width 1
Anti-backlash pulse width 2
Preamplifier select
Single / dual mode
7
see table
8
see table
see table
9
10
11
12
13
14
15
16
EN
single
low
dual
high
1
2
Port 1
PD-current 1
PD-current 2
PD-current 3
see table
see table
see table
3
4
5
0
0
Address
0
1
6
EN
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14
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1
2
MSB
3
a-Counter
4
5
6
7
LSB
8
MSB
MSB
1
2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
EN
3
4
5
6
7
n-Counter
8
9
10
11
12
13
14
15
16
EN
LSB
LSB
1
0
1
0
Address
Semiconductor Group
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1
2
MSB
3
4
5
6
7
8
r-Counter
9
10
11
12
13
14
15
16
17
18
LSB
1
1
Address
EN
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16
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ꢊꢃꢇ
7A = – 40 to 85 °C
3DUDPHWHU
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PLQꢃ
PD[ꢃ
6
Supply voltage
9DD
9I
– 0.3
– 0.3
GND
V
Input voltage
9DD + 0.3
V
Output voltage
9Q
3Q
3tot
7A
9DD
10
V
Power dissipation per output
Total power dissipation
Ambient temperature
Storage temperature
mW
mW
°C
300
85
– 40
– 50
in operation
7stg
125
°C
2SHUDWLQJꢀ5DQJH
Supply voltage
9DD
IFI
3.0
5.5
V
Input frequency dual mode
Input frequency single HF-mode IFI
Input frequency single LF-mode IFI
Input reference frequency
Input frequency dual mode
Input frequency single HF-mode IFI
Input frequency single LF-mode IFI
Input reference frequency
0.1
0.1
0.1
65
220
90
100
30
120
35
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
9
9
9
9
9
9
9
9
DD = 4.5 … 5.5 V
DD = 4.5 … 5.5 V
DD = 4.5 … 5.5 V
DD = 4.5 … 5.5 V
DD = 3.3 V
DD = 3.3 V
DD = 3.3 V
DD = 3.3 V
IRI
IFI
0.1
0.1
0.1
IRI
22
PD-output current
PD-output voltage
PD-output voltage
/ ,PD
9PD
9PD
/
4
9
9
mA
V
V
0.5
0.5
DD – 0.5
DD – 0.5
9
9
DD = 4.5 – 5.5 V
DD = 3.3 V
Ambient temperature
7A
– 40
85
°C
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either 9DD or 9SS
.
ꢊꢃꢂ
7\SLFDOꢀ6XSSO\ꢀ&XUUHQWꢀ, ꢀ
Supply voltage 9DD
3.3
5
5.5
V
Test conditions:
Supply current
I
I
,
= 50 MHz, 9 = 150 mVrms
FI
FI
singlemode HF
dual mode
standby 2
,
DD
,
DD
,
DD
,
DD
1.63
1.76
0.11
2.6
2.80
0.62
2.94
3.17
0.75
1
mA
mA
mA
µA
= 10 MHz, 9 = 150 mVrms
RI
RI
= 0.25 mA, , = 100 µA
PD
ref
standby 1
Semiconductor Group
18
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H-input voltage
L-input voltage
Input capacity
H-input current
L-input current
9IH
9IL
0.7 9D
0
9DD
0.3 9DD
5
V
V
pF
µA
µA
D
&
I
,
H
10
9I = 9DD = 5.5 V
9I = GND
,
L
– 300
Further information about timing see at page 25 and 26
,QSXWꢀ6LJQDOꢀ5,
Input voltage
9I
9I
&
100
mVrms I = 4 … 100 MHz,
DD =4.5 V
mVrms I = 4 … 22 MHz, 9DD = 3.3 V
9
Input voltage
Slew rate
Input capacity
H-input current
L-input current
100
2.5
V/µs
9DD = 3.3 … 5.5 V
3
30
pF
I
,
H
µA
µA
9I = 9DD = 5.5 V
9I = GND
,
L
– 30
,QSXWꢀ6LJQDOꢀ),ꢀꢎGXDOꢀPRGHꢏ
Input voltage
Input voltage
Input voltage
Slew rate
9I
9I
9I
180
180
50
mVrms I = 4 … 65 MHz, 9DD = 4.5 V
mVrms I = 4 … 30 MHz, 9DD = 3.3 V
mVrms I = 10 … 30 MHz, 9DD = 3.3 V
4
V/µs
9DD = 3.3 … 5.5 V
Input capacity
H-input current
L-input current
&
3
30
pF
µA
µA
I
,
,
9I = 9DD = 5.5 V
9I = GND
H
– 30
L
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Input voltage
Input voltage
Input voltage
Slew rate
9I
9I
9I
200
20
50
mVrms I = 4 … 220 MHz, 9DD = 4.5 V
mVrms I = 4 … 120 MHz, 9DD = 3.3 V
mVrms I = 10 … 50 MHz, 9DD = 4.5 V
2.5
V/µs
9DD = 3.3 … 5.5 V
Input capacity
H-input current
L-input current
&
3
30
pF
µA
µA
I
,
H
9I = 9DD = 5.5 V
9I = GND
,
L
– 30
Semiconductor Group
19
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Input voltage
Input voltage
Slew rate
9I
9I
100
100
2.5
mVrms I = 4 … 90 MHz, 9DD = 4.5 V
mVrms I = 4 … 35 MHz, 9DD = 3.3 V
V/µs
9DD = 3.3 … 5.5 V
Input capacity
H-input current
L-input current
&
3
30
pF
µA
µA
I
,
H
9I = 9DD = 5.5 V
9I = GND
,
L
– 30
2XWSXWꢀ&XUUHQWꢀ,
Current mode
“0.175 mA”
“0.25 mA”
“0.35 mA”
“0.5 mA”
,
,
,
,
,
,
,
,
– 20 %
– 20 %
– 20 %
– 20 %
– 20 %
– 10 %
– 10 %
– 10 %
+ 20 % mA
PROG
PROG
PROG
PROG
PROG
PROG
PROG
PROG
+ 20 % mA
+ 20 % mA
+ 20 % mA
+ 20 % mA
+ 10 % mA
+ 10 % mA
+ 10 % mA
9
DD = 4.5 … 5.5 V
9PD = 9DD/2
“0.7 mA”
“1.0 mA”
“1.4 mA”
“2.0 mA”
,REF = 100 µA
“Standby”
* guaranteed by
design
/ ,PD
/
0.1* 50
nA
9DD = 5.5 V
2XWSXWꢀ7ROHUDQFHVꢀ,
∆ ,PD / ,PROG
– 20 %
+ 3 %
9
PD = 9DD/2, 9DD = 3.3 V
PD = 1 … 4 V, 9DD = 5 V
∆ ,PD / ,PROG
±4%
9
,QSXWꢀ9ROWDJHꢀ0)2ꢂꢀꢎLQWHUQDOꢀFKDUJHꢀSXPSꢀPRGHꢏ
Reference voltage 9REF
0.9
1.1 1.3
V
9
DD = 4.5 … 5.5 V,
,REF = 100 µA
Semiconductor Group
20
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H-output voltage
9QH
9DD – 1
V
9DD = 4.5 … 5.5 V,
,
QH = 2 mA
L-output voltage
H-output voltage
L-output voltage
Rise time
Fall time
Rise time
9QL
9QH
9QL
WR
WF
WR
1
V
V
V
ns
ns
ns
ns
9
9
9
9
9
9
9
DD = 4.5 … 5.5 V, ,QL = 2 mA
DD = 3.3 V, ,QH = 1.2 mA
DD = 3.3 V, ,QL = 1.2 mA
DD = 4.5 … 5.5 V, &I = 10 pF
DD = 4.5 … 5.5 V, &I = 10 pF
DD = 3.3 V, &I = 10 pF
DD = 3.3 V, &I = 10 pF
9DD – 1
1
2.5 10
2.0 10
4.0 10
2.5 10
Fall time
WF
2XWSXWꢀ6LJQDOꢀ0)2ꢂꢀꢎSXVKꢀSXOOꢏ
H-output voltage
9QH
9DD – 1
V
9DD = 4.5 … 5.5 V,
,
QH = 2 mA
L-output voltage
H-output voltage
L-output voltage
Rise time
Fall time
Rise time
9QL
9QH
9QL
WR
WF
WR
1
1
10
10
10
10
V
V
V
ns
ns
ns
ns
9
9
9
9
9
9
9
DD = 4.5 … 5.5 V, ,QL = 2 mA
DD = 3.3 V, ,QH = 1.2 mA
DD = 3.3 V, ,QL = 1.2 mA
DD = 4.5 … 5.5 V, &I = 10 pF
DD = 4.5 … 5.5 V, &I = 10 pF
DD = 3.3 V, &I = 10 pF
9DD – 1
2
2
3
3
Fall time
WF
DD = 3.3 V, &I = 10 pF
2XWSXWꢀ6LJQDOꢀ/'ꢀꢎQꢉFKDQQHOꢀRSHQꢀGUDLQꢏ
L-output voltage
9QL
0.4
V
9DD = 4.5 … 5.5 V,
,
QL = 0.5 mA
L-output voltage
Fall time
Fall time
9QL
WF
WF
0.4
10
4.5 10
V
ns
ns
9
9
9
DD = 3.3 V, ,QL = 0.5 mA
DD = 4.5 … 5.5 V, &I = 10 pF
DD = 3.3 V, &I = 10 pF
3
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21
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H-output voltage
L-output voltage
H-output voltage
9QH
9QL
9QH
9DD
– 0.4
V
V
V
9
,
9
DD = 4.5 … 5.5 V,
QH = 0.5 mA
DD = 4.5 … 5.5 V,
QL = 0.5 mA
0.4
0.4
3
3
12
,
9
9DD
– 0.4
DD = 3.3 V, ,QH = 0.3 mA
L-output voltage
Rise time
Fall time
9QL
WR
WF
V
9
9
9
9
DD = 3.3 V, ,QL = 0.3 mA
1.5
1.3
8
ns
ns
ns
DD = 4.5 … 5.5 V, &I = 5 pF
DD = 4.5 … 5.5 V, &I = 5 pF
DD = 4.5 … 5.5 V, &I = 5 pF
Propagation delay WDQHL
time H-L to FI
Propagation delay WDQLH
time L-H to FI
8
12
ns
9DD = 4.5 … 5.5 V, &I = 5 pF
Rise time
Fall time
Propagation delay WDQHL
WR
WF
2.8
1.6
12
4
4
ns
ns
ns
9DD = 3.3 V, &I = 5 pF
9DD = 3.3 V, &I = 5 pF
9DD = 3.3 V, &I = 5 pF
time H-L to FI
Propagation delay WDQLH
time L-H to FI
12
ns
9DD = 3.3 V, &I = 5 pF
Semiconductor Group
22
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23
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500kΩ
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Clock frequency
ICL
12
MHz
ns
9DD=3.3V
H-pulsewidth (CL)
WWHCL
WDS
40
20
20
20
40
Data setup
ns
Setup time clock-enable
Setup time enable-clock
H-pulsewidth (enable)
Rise, fall time
WCLE
WECL
WWHEN
WRꢁꢀWF
WDEP
ns
ns
ns
10
1
µs
Propagation delay time EN-PORT
µs
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4 59, 53, 55, 511
1 54
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100 Ω
150 Ω
220 Ω
330 Ω
3.3 kΩ
6.8 kΩ
8.2 kΩ
18 kΩ
22 kΩ
39 kΩ
SMD/0805 B54102-A1101-K60
SMD/0805 B54102-A1151-J60
SMD/0805 B54102-A1221-J60
SMD/0805 B54102-A1331-J60
SMD/0805 B54102-A1332-J60
SMD/0805 B54102-A1682-J60
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SMD/0805 B54102-A1223-J60
SMD/0805 B54102-A1393-J60
S+M
S+M
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S+M
S+M
S+M
S+M
S+M
S+M
9
10
1 52
11
1 /1
22 nH
SIMID 01 B82412-A3220-M
S+M
12
13
14
15
1 &11
1 &13
1 &8
6 &20, &10, &12,
ꢀꢀꢀꢀ&14, &15, &16
3 &17, &1, &2
1 &9
1 &3
1 &5
1.2 pF
2.2 pF
10 pF
COG/0805 B37940-K5010-C262
COG/0805 B37940-K5020-C262
COG/0805 B37940-K5100-J62
S+M
S+M
S+M
22 pF
33 pF
COG/0805 B37940-K5220-J62
COG/0805 B37940-K5330-J62
COG/0805 B37940-K5101-J62
COG/0805 B37940-K5331-J62
COG/0805 B37940-K5561-J62
COG/1210 B37949-K5562-J62
X7R/1210 B37950-K5104-K62
B45196-E3226-+409
S+M
S+M
S+M
S+M
S+M
S+M
S+M
S+M
16
17
18
19
20
21
22
100 pF
330 pF
560 pF
5.6 nF
100 nF
22 µF
1 &7
1 &6
1 &19
23
24
25
1 D1
2 T3, T2
1 T1
BBY 51
BFR 280
BFT 92
Q62702-B631
Q62702-F1298
Q62702-F1062
SIEMENS
SIEMENS
SIEMENS
26
27
28
29
1 &
2 X2, X1
1 RX
1,0 nF
SMA
1.3 GHz
PMB 2306T P-DSO-14
PMB 2306T P-DSO-14
PMB 2314 P-DSO-8
PMB 2314 P-DSO-8
COG/1210 B37949-K5102-J62
Connector
S+M
4
B69610-G1307-A412
Q67100-H6423
Q67106-H6423(T+R)
Q67000-A6121
Q67006-A6121(T+R)
S+M
1 IC1
SIEMENS
SIEMENS
SIEMENS
SIEMENS
30
1 IC2
Semiconductor Group
29
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34
02.97
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3DFNDJHꢀ2XWOLQHV
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Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
35
02.97
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