Q67000-A9243-A802 [INFINEON]
5-V Low-Drop Fixed Voltage Regulator; 5 -V低压降固定电压稳压器
| 型号： | Q67000-A9243-A802 |
| 厂家： | 
Infineon |
| 描述： | 5-V Low-Drop Fixed Voltage Regulator |
| 文件： | 总19页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5-V Low-Drop Fixed Voltage Regulator
TLE 4270
Features
• Output voltage tolerance ≤ ± 2 %
• Low-drop voltage
• Integrated overtemperature protection
• Reverse polarity protection
• Input voltage up to 42 V
• Overvoltage protection up to 65 V (≤ 400 ms)
• Short-circuit proof
P-TO220-5-11
(P-TO220-5-1)
• Suitable for use in automotive electronics
• Wide temperature range
• Adjustable reset time
• ESD protection > 4000 V
Type
Ordering Code
Package
P-TO220-5-12
(P-TO220-5-2)
TLE 4270
Q67000-A9209-A903 P-TO220-5-11
Q67000-A9243-A904 P-TO220-5-12
Q67006-A9201-A901 P-TO263-5-1
Q67000-A9209-A801 P-TO220-5-1
Q67000-A9243-A802 P-TO220-5-2
Q67006-A9201-A802 P-TO220-5-8
TLE 4270 S
TLE 4270 G
▼ TLE 4270
▼ TLE 4270 S
▼ TLE 4270 G
● TLE 4270 D
P-TO263-5-1
(P-TO220-5-8)
Q67006-A9360
P-TO252-5-1
▼ Not for new design
● New type
Functional Description
This device is a 5-V low-drop fixed-voltage regulator.
The maximum input voltage is 42 V (65 V, ≤ 400 ms).
Up to an input voltage of 26 V and for an output current
up to 550 mA it regulates the output voltage within a
2 % accuracy. The short circuit protection limits the
P-TO252-5-1 (D-PAK)
output current of more than 650 mA. The device incorporates overvoltage protection
and temperature protection that disables the circuit at unpermissibly high temperatures.
Semiconductor Group
1
1998-11-01
TLE 4270
Pin Configuration
(top view)
P-TO220-5-11
(P-TO220-5-1)
P-TO220-5-12
(P-TO220-5-2)
P-TO263-5-1
(P-TO220-5-8)
1
5
RO
GND
D
1
5
1
5
Ι
Q
AEP01922
P-TO252-5-1 (D-PAK)
GND
Ι
GND
RO
Q
RO
GND
D
D
Ι
Q
AEP02172
AEP01923
1
5
Ι RO D Q
AEP02580
Figure 1
Pin Definitions and Functions
Pin Symbol Function
1
2
I
Input; block to ground directly on the IC with ceramic capacitor
RO
Reset Output; the open collector output is connected to the 5 V output
via an integrated resistor of 30 kΩ.
3
4
5
GND
D
Ground; internally connected to heatsink.
Reset Delay; connect a capacitor to ground for delay time adjustment.
5-V Output; block to ground with 22 µF capacitor, ESR < 3 Ω.
Q
Semiconductor Group
2
1998-11-01
TLE 4270
Application Description
The IC regulates an input voltage in the range of 5.5 V < VI < 36 V to VQnom = 5.0 V. Up
to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the
save-operating-area protection allows operation up to 36 V with a regulated output
current of more than 300 mA. Overvoltage protection limits operation at 42 V. The
overvoltage protection hysteresis restores operation if the input voltage has dropped
below 36 V. A reset signal is generated for an output voltage of VQ < 4.5 V. The delay for
power-on reset can be set externally with a capacitor.
Design Notes for External Components
An input capacitor CI is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1 Ω in series with CI. An output capacitor CQ is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of CQ ≥ 22 µF and an ESR of
< 3 Ω.
Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of a series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element.
If the output voltage decreases below 4.5 V, an external capacitor CD on pin 4 (D) will be
discharged by the reset generator. If the voltage on this capacitor drops below VDRL, a
reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage
rises above 4.5 V, CD will be charged with constant current. After the power-on-reset time
the voltage on the capacitor reaches VDU and the reset output will be set high again. The
value of the power-on-reset time can be set within a wide range depending of the
capacitance of CD.
The IC also incorporates a number of internal circuits for protection against:
• Overload
• Overvoltage
• Overtemperature
• Reverse polarity
Semiconductor Group
3
1998-11-01
TLE 4270
Saturation
Control and
Protection
Circuit
Temperature
Sensor
5
1
Input
Output
Control
Amplifier
2
4
Buffer
Reset
Output
Bandgap
Reference
Reset
Generator
Adjustment
+
-
Reset
Delay
3
GND
AEB01924
Figure 2
Block Diagram
Semiconductor Group
4
1998-11-01
TLE 4270
Absolute Maximum Ratings
Tj = – 40 to 150 °C
Parameter
Symbol
Limit Values
max.
Unit
Notes
min.
Input
Voltage
Voltage
Current
VI
VI
II
– 42
42
65
V
V
t ≤ 400 ms
internally limited
Reset Output
Voltage
Current
VR
IR
– 0.3
– 0.3
– 1.0
– 0.5
– 50
7
V
V
V
A
Internally limited
Internally limited
Reset Delay
Voltage
Current
VD
ID
7
Output
Voltage
Current
VQ
IQ
16
–
Internally limited
Ground
Current
IGND
–
–
Temperatures
Junction temperature Tj
Storage temperature
150
150
°C
°C
Tstg
Optimum reliability and life time are guaranteed if the junction temperature does not
exceed 125 °C in operating mode. Operation at up to the maximum junction temperature
of 150 °C is possible in principle. Note, however, that operation at the maximum
permitted ratings could affect the reliability of the device.
Semiconductor Group
5
1998-11-01
TLE 4270
Operating Range
Parameter
Symbol
Limit Values
Unit Notes
min.
max.
42
Input voltage
VI
Tj
6
V
–
–
Junction temperature
– 40
150
°C
Thermal Resistance
Junction ambient
Rthja
–
–
65
70
K/W
K/W TO263, TO2521)
Junction case
Rthjc
Zthjc
3
2
K/W t < 1 ms
K/W (TO-220/263
Packages)
1)
Soldered in, min. footprint
Characteristics
VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
Output voltage
Output voltage
VQ
VQ
IQmax
Iq
4.90
5.00
5.10
5.10
–
V
5 mA ≤ IQ ≤ 550 mA;
6 V ≤ VI ≤ 26 V
4.90
650
–
5.00
850
1
V
26 V ≤ VI ≤ 36 V;
IQ ≤ 300 mA
Output current
limiting
mA
mA
VQ = 0 V
Current
1.5
IQ = 5 mA
consumption
Iq = II − IQ
Current
consumption
Iq = II – IQ
Iq
–
–
–
55
70
350
6
75
mA
mA
mV
IQ = 550 mA
Current
consumption
Iq = II – IQ
Iq
90
IQ = 550 mA; VI = 5 V
IQ = 550 mA1)
1998-11-01
Drop voltage
Vdr
700
Semiconductor Group
TLE 4270
Characteristics (cont’d)
VI = 13.5 V; – 40 °C ≤ Tj = ≤ 125 °C (unless otherwise specified)
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ.
max.
Load regulation
∆VQ
–
25
50
25
–
mV
mV
dB
IQ = 5 to 550 mA;
VI = 6 V
Supply voltage
regulation
∆VQ
–
–
12
54
VI = 6 to 26 V
IQ = 5 mA
Power supply
Ripple rejection
PSRR
fr = 100 Hz;
Vr = 0.5 VSS
Reset Generator
Switching threshold VRT
Reset High voltage VROH
4.5
4.5
–
4.65
–
4.8
–
V
–
–
V
Reset low voltage
VROL
60
–
mV
R
intern = 30 kΩ2);
1.0 V ≤ VQ ≤ 4.5 V
Reset low voltage
Reset pull-up
VROL
R
–
200
30
400
46
mV
IR = 3 mA, VQ = 4.4 V
18
kΩ
internally connected
to Q
Lower reset timing
threshold
VDRL
0.2
0.45
0.8
V
VQ < VRT
Charge current
Id
8
14
25
µA
VD = 1.0 V
Upper timing
threshold
VDU
1.4
1.8
2.3
V
–
Delay time
td
–
–
13
–
–
3
ms
CD = 100 nF
CD = 100 nF
Reset reaction time tRR
µs
Overvoltage Protection
Turn-Off voltage
VI, ov
42
44
46
V
–
1)
Drop voltage = VI – VQ (measured when the output voltage has dropped 100 mV from the nominal value
obtained at 13.5 V input)
2)
Reset peak is always lower than 1.0 V.
Semiconductor Group
7
1998-11-01
TLE 4270
Ι
Ι
Q
Ι
1
5
2
µ
22 µF
1000
F
470 nF
TLE 4270G
Ι
R
V
V
Q
Ι
4
Ι
3
D
V
R
V
C
Ι
D
D
GND
AES01925
Figure 3
Test Circuit
5
4
1
5 V-Output
Input
470 nF
TLE 4270
22 µF
2
Reset
to MC
100 nF
3
AES01926
Figure 4
Application Circuit
Semiconductor Group
8
1998-11-01
TLE 4270
V
V
V
V
Ι
< t
RR
Q
D
R
V
RT
d
d
Ι
C
V
t
d
d
=
V
V
DU
DRL
t
t
RR
d
Power-on-Reset
Thermal
Shutdown
Voltage Drop Undervoltage
at Input
Secondary
Spike
Load
Bounce
AES01927
Figure 5
Time Response
Semiconductor Group
9
1998-11-01
TLE 4270
Output Voltage VQ versus
Temperature Tj
Output Voltage VQ versus
Input Voltage VI
AED01929
AED01928
12
5.20
V
V
Q
V
V
Q
10
5.10
V = 13.5 V
Ι
8
6
4
2
0
5.00
4.90
4.80
4.70
4.60
R
= 25
Ω
L
0
2
4
6
8
10
V
-40
0
40
80
120
160
C
V
T
Ι
j
Output Current IQ versus
Temperature Tj
Output Current IQ versus
Input Voltage VI
AED01931
AED01930
1.2
A
1200
mA
Ι
Ι
Q
Q
1.0
0.8
0.6
0.4
0.2
0
1000
800
600
400
200
0
T = 25 C
j
T = 125 C
j
0
10
20
30
40
V
50
V
-40
0
40
80
120
160
C
T
Ι
Semiconductor Group
10
1998-11-01
TLE 4270
Current Consumption Iq
versus Output Current IQ
Current Consumption Iq
versus Output Current IQ
AED01932
AED01933
6
80
mA
mA
Ι
Ι
q
q
70
60
50
40
30
20
10
0
5
4
3
V = 13.5 V
Ι
V = 13.5 V
Ι
2
1
0
0
20
40
60
80
120
0
100 200 300 400
600
mA
mA
Ι
Ι
Q
Q
Current Consumption Iq
versus Input Voltage VI
Drop Voltage Vdr versus
Output Current IQ
AED01934
AED01935
120
mA
800
mV
V
Ι
Dr
700
600
500
400
300
200
100
0
q
100
80
T = 125 C
j
60
R = 10
Ω
L
40
20
0
T
=25 C
j
R = 20
Ω
R = 50
Ω
L
L
0
200
400
600
1000
mA
0
10
20
30
40
50
V
Ι
V
Q
Ι
Semiconductor Group
11
1998-11-01
TLE 4270
Charge Current Id
Delay Switching threshold VDU
versus Temperature Tj
versus Temperature Tj
AED01936
AED01937
8
A
7
4.0
V
µ
Ι
V
d
dT
3.5
Ι
d
6
5
4
3
2
1
3.0
V
V
= 13.5 V
= 1 V
Ι
V = 13.5 V
2.5
2.0
1.5
1.0
0.5
0
Ι
D
V
DU
0
-40
0
40
80
120
160
C
-40
0
40
80
120
160
C
T
T
j
j
Semiconductor Group
12
1998-11-01
TLE 4270
Package Outlines
P-TO220-5-1
(Plastic Transistor Single Outline)
10+0.4
4.6-0.2
10.2-0.2
3.75+0.1
1x45˚
1.27+0.1
2.6
1
5
0.4+0.1
1.7
0.8+0.1
1)
±0.4
4.5
8.4
M
0.6
±0.4
5x
1) 1-0.15 at dam bar (max 1.8 from body)
1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Semiconductor Group
13
1998-11-01
TLE 4270
P-TO220-5-2
(Plastic Transistor Single Outline)
10+0.4
4.6-0.2
10.2 -0.2
3.75+0.1
1x45˚
1.27+0.1
1
5
0.4+0.1
1.7
0.8+0.1
1)
±0.15
2.6
M
0.6
5x
1) 1-0.15 at dam bar (max 1.8 from body)
1) 1-0.15 im Dichtstegbereich (max 1.8 vom Körper)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Semiconductor Group
14
1998-11-01
TLE 4270
P-TO220-5-11
(Plastic Transistor Single Outline)
±0.2
10
A
±0.15
9.8
8.51)
4.4
3.7-0.15
1.27±0.1
0.05
C
0.5±0.1
3.9±0.4
0...0.15
2.4
0.8±0.1
1.7
M
0.25
A C
8.4±0.4
1)
Typical
All metal surfaces tin plated, except area of cut.
GPT09064
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Semiconductor Group
15
1998-11-01
TLE 4270
P-TO220-5-12
(Plastic Transistor Single Outline)
±0.2
10
A
±0.15
9.8
B
8.51)
4.4
3.7-0.15
1.27±0.1
0.05
C
±0.1
0.5
0...0.15
1.7
6x
2.4
0.8±0.1
M
0.25
A B C
Typical
1)
All metal surfaces tin plated, except area of cut.
GPT09065
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Semiconductor Group
16
1998-11-01
TLE 4270
P-TO263-5-1
(Plastic Transistor Single Outline)
±0.2
10
4.4
±0.15
9.8
±0.1
1.27
B
A
8.5 1)
0.1
0.05
2.4
0...0.15
4x1.7
5x0.8±0.1
8˚ max.
M
0.25
A B
0.1
1)
Typical
All metal surfaces tin plated, except area of cut.
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
17
1998-11-01
TLE 4270
P-TO220-5-8
(Plastic Transistor Single Outline)
4.6
1.27
0.2
10.2
8.0
2.6
1)
0.8
1.7
4 x 1.7 = 6.8
GPT05873
1) shear and punch direction burr free surface
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
18
1998-11-01
TLE 4270
P-TO252-5-1
(Plastic Transistor Single Outline)
+0.05
-0.10
+0.15
2.3
6.5
-0.10
+0.08
0.9
-0.04
B
±0.1
5.4
A
±0.1
1
0...0.15
0.15 max
per side
+0.08
-0.04
0.5
±0.1
5x0.6
1.14
0.1
4.56
M
0.25
A B
GPT09161
All metal surfaces tin plated, except area of cut.
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
19
1998-11-01
相关型号：
©2020 ICPDF网 联系我们和版权申明