Q67000-A9407 [INFINEON]
5-V Low-Drop Voltage Regulator; 5 -V低压差稳压器
| 型号： | Q67000-A9407 |
| 厂家： | 
Infineon |
| 描述： | 5-V Low-Drop Voltage Regulator |
| 文件： | 总18页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5-V Low-Drop Voltage Regulator
TLE 4290
Features
• Output voltage 5 V 2%
• Very low current consumption
• 450 mA current capability
• Power Good Feature
• Very low-drop voltage
P-TO252-5-1
• Short-circuit-proof
• Reverse polarity proof
• Suitable for use in automotive electronics
Type
Ordering Code Package
•
•
•
TLE 4290 D Q67006-A9408 P-TO252-5-1 (SMD)
TLE 4290 G Q67006-A9405 P-TO263-5-1 (SMD)
TLE 4290
Q67000-A9407 P-TO220-5-11
• New type
P-TO263-5-1
Functional Description
The TLE 4290 is a monolithic integrated low-drop
voltage regulator which can supply loads up to 450 mA
with power good feature. An input voltage up to 42 V is
regulated to VQ,nom = 5.0 V. The device is designed to
supply µ-controllers in the severe environment of
automotive applications. Therefore it is protected
against overload, short circuit and over temperature
conditions. Of course the TLE 4290 can been used also
in all other applications, where a stabilized 5 V voltage is
required.
P-TO220-5-11
Data Sheet Rev. 1.4
1
2001-10-18
TLE 4290
Power Good
The Power Good PG pin informs e.g. the microcontroller in case the output voltage has
fallen below the lower threshold VQ,pgt-d of typ. 3.65 V. Connecting the regulator to a
battery voltage at first the power good signal remains LOW. When the output voltage has
reached the higher threshold VQ,pgt-i the power good output remains still LOW for the
power good delay time trd. Afterwards the power good output turns HIGH. The delay time
can be set by the user with an external capacitor at pin D according to the requirements
of the application.
The Power Good circuitry supervises the output voltage. In case VQ falls below the lower
Power Good switching threshold VQ,pgt-d the PG output is set LOW after the Power Good
reaction time. The Power Good LOW signal is generated down to an output voltage VQ
to 1 V. A LOW signal at the Power Good pin informs that the battery was lost and
memory is no longer valid.
The feature should be used in combination with a microcontroller with internal reset.
TLE 4290
1
5
I
Q
Band-
Gap-
Reference
Current
and
Saturation
Control
2
PG
Power
Good
Control
4
AEB02823
GND
D
Figure 1
Block Diagram
Data Sheet Rev. 1.4
2
2001-10-18
TLE 4290
P-TO252-5-1 (D-PAK)
P-TO263-5-1 (SMD)
P-TO220-5-11
GND
I
PG
D Q
AEP02825
I
PG GND
D
Q
AEP02827
I
GND
Q
PG
D
AEP02826
Figure 2
Pin Configuration (top view)
Pin Definitions and Functions
Pin No. Symbol Function
1
2
I
Input; block to ground directly at the IC with a ceramic capacitor.
PG
Power Good; open collector output. Add a pull up resistor of > 5 kΩ
to pin Q.
3
4
GND
D
Ground; Pin 3 internally connected to heatsink.
Delay; connect a capacitor to GND for setting power good delay
time.
5
Q
Output; block to ground with a capacitor, C ≥ 22 µF
ESR < 5 Ω at 10 kHz.
Data Sheet Rev. 1.4
3
2001-10-18
TLE 4290
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Input I
Voltage
Current
VI
II
– 42
45
–
V
–
–
–
Internally limited
Output Q
Voltage
Current
VQ
IQ
– 1.0
16
V
–
–
–
–
Internally limited
Power Good Output PG
Voltage
Current
VPG
IPG
– 0.3
– 5
25
5
V
–
–
mA
Delay D
Voltage
Current
VD
ID
– 0.3
– 2
7
2
V
–
–
mA
Temperature
Junction temperature
Storage temperature
Tj
– 40
– 50
150
150
°C
°C
–
–
Tstg
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Data Sheet Rev. 1.4
4
2001-10-18
TLE 4290
Operating Range
Parameter
Symbol
Limit Values
Unit Remarks
min.
max.
42
Input voltage
VI
Tj
5.5
–
–
V
Junction temperature
– 40
150
°C
Thermal Resistance
Junction case
Rthj-c
Rthj-a
Rthj-a
Rthj-a
–
–
–
–
4
K/W –
Junction ambient
Junction ambient
53
78
65
K/W TO2631)
K/W TO2521)
K/W TO220
Junction ambient
1)
Worst case, regarding peak temperature; zero airflow; mounted on a PCB FR4, 80 × 80 × 1.5 mm3, heat sink
area 300 mm2
Note: In the operating range, the functions given in the circuit description are fulfilled.
Data Sheet Rev. 1.4
5
2001-10-18
TLE 4290
Characteristics
VI = 13.5 V; – 40 °C < Tj < 150 °C (unless otherwise specified)
Parameter
Symbol
Limit Values
Unit Measuring
Condition
min. typ. max.
Output
Output voltage
VQ
VQ
4.9
4.9
5.0
5.0
5.1
5.1
–
5 mA < IQ < 400 mA;
6 V < VI < 28 V
V
Output voltage
5 mA < IQ < 200 mA;
6 V < VI < 40 V
V
1)
Output current limitation
IQ
Iq
450 700
mA
Current consumption;
Iq = II – IQ
–
–
–
–
–
200 230 µA
IQ = 1 mA;
Tj = 25 °C
Current consumption;
Iq = II – IQ
Iq
200 255 µA
IQ = 1 mA;
Tj ≤ 85 °C
Current consumption;
Iq = II – IQ
Iq
5
12
25
mA
mA
IQ = 250 mA
IQ = 400 mA
IQ = 300 mA
Current consumption;
Iq = II – IQ
Iq
12
Drop voltage
Vdr
250 500 mV
1)
Vdr = VI – VQ
Load regulation
Line regulation
– 30 15
– 15 5
30
15
–
mV
mV
dB
VI = 6 V;
IQ = 5 mA to 400 mA
∆VQ, lo
∆VQ, li
PSRR
Vl = 8 V to 32 V;
IQ = 5 mA
Power supply ripple
rejection
–
60
0.5
–
fr = 100 Hz;
Vr = 0.5 Vpp
dVQ
----------
dT
Temperature output
voltage drift
–
–
mV/K –
Output Capacitor
CQ
22
–
µF
ESR < 5 Ω in the
operation range
Power Good Output PG and Delay Timing D
Power Good switching
threshold
VQ,pgt-i
4.45 4.65 4.80 V
VQ increasing
Data Sheet Rev. 1.4
6
2001-10-18
TLE 4290
Characteristics (cont’d)
VI = 13.5 V; – 40 °C < Tj < 150 °C (unless otherwise specified)
Parameter
Symbol
Limit Values
Unit Measuring
Condition
min. typ. max.
Power Good switching
threshold
VQ,pgt-d 3.50 3.65 3.80 V
VQ decreasing
Power Good output low
voltage
VPGL
IPGH
ID,c
–
0.2
0
0.4
2
V
RPG ≥ 5 kΩ;
VQ > 1 V
Power Good output
leakage current
–
µA
µA
V
VPG > 4.5 V
Power Good charging
current
3
6
9
VD = 1 V
Upper timing threshold
Lower timing threshold
Power Good delay time
VDU
VDL
trd
1.5
1.8
2.2
–
0.60 0.85 1.10 V
–
10
16
22
ms
CD = 47 nF
CD = 47 nF
Power Good reaction time trr
0.2
0.5
2.0
µs
1)
Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V.
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at Ta = 25 °C and
the given supply voltage.
II
IQ
I
Q
VI
1
4
5
2
CI1
CI2
100 nF
CQ
22 µF
1000 µF
RPG
5 k
TLE 4290
VQ
ID
D
PG
ID,C
VPG
CD
47 nF
GND
IGND
AES02824
Figure 3
Test Circuit
Data Sheet Rev. 1.4
7
2001-10-18
TLE 4290
Application Information
CQ2
CQ1
TLE 4290
µ-Controller
22 100
VBAT
µF
nF
1
5 Q
I
VCC
CI1
CI2
Band-
Gap-
Current
and
Reference
Saturation
Control
Internal
Reset
RPG
5 k
2
NMI /
PORT
Power
Good
PG
Control
4
GND
D
CD
47 nF
AES02822
Figure 4
Application Diagram
Input, Output
An input capacitor is necessary for damping line influences. A resistor of approx. 1 Ω in
series with CI, can damp the LC of the input inductivity and the input capacitor.
The TLE 4290 requires an output capacitor of at least 22 µF with an ESR below 5 Ω for
stability.
Power Good
The Power Good pin informs e.g. the micro-controller in case the output voltage has
fallen below a threshold of typ. 3.65 V. When the battery voltage is supplied the Power
Good signal indicates a loss of memory due to missing power. After the Memory Good
switching threshold is reached the Power Good output remains low for the Power Good
delay time. This time can be set by the user with an external capacitor at pin D according
to the requirements of the application, e.g. the time until the microcontroller is initialized
and ready to receive any information.
Data Sheet Rev. 1.4
8
2001-10-18
TLE 4290
The power good circuit supervises the output voltage. In case VQ falls below the Power
Good switching threshold the Power Good output PG is set LOW after the power good
reaction time. The power good LOW signal is generated down to an output voltage VQ
to 1 V. A LOW signal at the power good pin informs that the battery was lost and memory
is no longer valid.
The feature should only be used in combination to a microcontroller with internal reset.
For the power good delay time after the output voltage of the regulator is above the reset
threshold, the reset signal is set High again. The reset delay time is defined by the reset
delay capacitor CD at pin D.
The Power Good delay time is defined by the charging time of an external delay
capacitor CD.
CD= (trd × ID,c) / ∆V
With
CD
trd
∆V
Power Good delay capacitor
Power Good delay time
= VDU, typical 1.8 V
ID,c Charge current typical 6 µA
VΙ
< trr
VQ
VQ,pgt_i
VQ,pgt_d
dV
ΙD, c
CD
=
dt
VD
VDU
VDL
trd
trr
VPG
Power-on
Power Good
Signal
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Overload
at Output
AED03074
Figure 5
Power Good Timing
Data Sheet Rev. 1.4
9
2001-10-18
TLE 4290
The power good reaction time trr is the time it takes the voltage regulator to set power
good output PG LOW after the output voltage has dropped below the power good
switching threshold. It is typically 0.5 µs for delay capacitor of 47 nF. For other values for
CD the reaction time can be estimated using the following equation:
trr = 10 ns/nF × CD
The Power Good output is an open collector output. It requires externally a pull up
resistor of at least 5 kΩ to Q.
Typical Performance Characteristics
Output Voltage VQ versus
Temperature Tj
Output Voltage VQ versus
Input Voltage VI
AED01929
AED03033
12
V
5.2
V
VQ
V
Q
10
5.1
VI = 13.5 V
8
5.0
4.9
4.8
4.7
4.6
6
R
= 25
Ω
L
4
2
0
-40
0
40
80
120 ˚C 160
0
2
4
6
8
10
V
Tj
V
Ι
Data Sheet Rev. 1.4
10
2001-10-18
TLE 4290
Output Current IQ versus
Temperature Tj
Output Current IQ versus
Input Voltage VI
AED03046
AED03034
1.2
1200
mA
IQ
A
IQ
1.0
1000
800
600
400
200
0
0.8
0.6
0.4
0.2
0
T
j = 125 ˚C
25 ˚C
-40
0
40
80
120 ˚C 160
0
10
20
30
40 V 50
Tj
VI
Current Consumption Iq
versus Output Current IQ; Tj = 25 °C
Current Consumption Iq
versus Output Current IQ
AED03112
AED03035
2.4
80
mA
mA
Ι q
Ι q
70
60
50
40
2.0
1.6
1.2
VΙ = 13.5 V
30
0.8
VΙ = 13.5 V
20
10
0
0.4
0
0
20
40
60
80
120
mA
0
100
200
300
400
600
mA
Ι Q
Ι Q
Data Sheet Rev. 1.4
11
2001-10-18
TLE 4290
Drop Voltage Vdr versus
Output Current IQ
Charge Current ID,c
versus Temperature Tj
AED01935
AED03036
800
8
mV
µA
Vdr
ID, c
700
600
500
7
6
5
T
j = 125 ˚C
25 ˚C
VI = 13.5 V
D = 1 V
400
300
200
100
0
4
3
2
1
0
V
mA
0
200
400
600
1000
-40
0
40
80
120 ˚C 160
IQ
Tj
Upper Timing Threshold VDU
versus Temperature Tj
AED03037
4.0
mA
VDU
3.5
3.0
2.5
VΙ = 13.5 V
2.0
1.5
1.0
0.5
0
-40
0
40
80
120
160
˚C
Tj
Data Sheet Rev. 1.4
12
2001-10-18
TLE 4290
Package Outlines
P-TO252-5-1 (D-PAK)
(Plastic Transistor Single Outline)
+0.05
-0.10
+0.15
2.3
6.5
-0.10
+0.08
-0.04
B
0.1
5.4
0.9
A
0.1
1
0...0.15
0.15 max
per side
+0.08
-0.04
0.5
0.1
5x0.6
1.14
0.1
4.56
M
0.25
A B
GPT09161
All metal surfaces tin plated, except area of cut.
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
2001-10-18
SMD = Surface Mounted Device
Data Sheet Rev. 1.4
13
TLE 4290
P-TO263-5-1-1 (SMD)
(Plastic Transistor Single Outline)
0.2
10
4.4
0.15
9.8
0.1
1.27
B
A
8.5 1)
0.1
0.05
2.4
0...0.15
5x0.8 0.1
0.5
0.1
4x1.7
8
˚
max.
M
0.25
A B
0.1
1)
Typical
All metal surfaces tin plated, except area of cut.
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
2001-10-18
SMD = Surface Mounted Device
Data Sheet Rev. 1.4
14
TLE 4290
P-TO220-5-11
(Plastic Transistor Single Outline)
0.2
10
A
0.15
9.8
8.51)
4.4
3.7-0.15
1.27 0.1
0.05
C
0.5 0.1
3.9 0.4
0...0.15
2.4
0.8 0.1
1.7
M
0.25
A C
8.4 0.4
1)
Typical
All metal surfaces tin plated, except area of cut.
gpt09064_ma
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
2001-10-18
Data Sheet Rev. 1.4
15
TLE 4290
Data Sheet Rev. 1.4
16
2001-10-18
TLE 4290
Data Sheet Rev. 1.4
17
2001-10-18
TLE 4290
Edition 2001-10-18
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe
certain components and shall not be consid-
ered as warranted characteristics.
Terms of delivery and rights to technical
change reserved.
We hereby disclaim any and all warranties,
including but not limited to warranties of
non-infringement, regarding circuits, descrip-
tions and charts stated herein.
Infineon Technologies is an approved CECC
manufacturer.
Information
For further information on technology, deliv-
ery terms and conditions and prices please
contact your nearest Infineon Technologies
Office in Germany or our Infineon Technolo-
gies Representatives worldwide (see ad-
dress list).
Warnings
Due to technical requirements components
may contain dangerous substances. For in-
formation on the types in question please
contact your nearest Infineon Technologies
Office.
Infineon Technologies Components may only
be used in life-support devices or systems
with the express written approval of Infineon
Technologies, if a failure of such components
can reasonably be expected to cause the fail-
ure of that life-support device or system, or to
affect the safety or effectiveness of that de-
vice or system. Life support devices or sys-
tems are intended to be implanted in the hu-
man body, or to support and/or maintain and
sustain and/or protect human life. If they fail, it
is reasonable to assume that the health of the
user or other persons may be endangered.
Data Sheet Rev. 1.4
18
2001-10-18
相关型号：
©2020 ICPDF网 联系我们和版权申明